From fe7297bf011bf6910d76010ba1763daf1286cbf4 Mon Sep 17 00:00:00 2001 From: Biju Das Date: Wed, 12 Jul 2023 16:11:53 +0100 Subject: [PATCH] arm64: dts: renesas: rzg2lc-smarc-som: Add PHY interrupt support for ETH0 The PHY interrupt (INT_N) pin is connected to IRQ0 for ETH0. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230712151153.81965-1-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven --- arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi index 79279ff..a09e13d 100644 --- a/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg2lc-smarc-som.dtsi @@ -6,6 +6,7 @@ */ #include +#include #include / { @@ -74,6 +75,8 @@ compatible = "ethernet-phy-id0022.1640", "ethernet-phy-ieee802.3-c22"; reg = <7>; + interrupt-parent = <&irqc>; + interrupts = ; rxc-skew-psec = <2400>; txc-skew-psec = <2400>; rxdv-skew-psec = <0>; @@ -121,7 +124,8 @@ , /* ET0_RXD0 */ , /* ET0_RXD1 */ , /* ET0_RXD2 */ - ; /* ET0_RXD3 */ + , /* ET0_RXD3 */ + ; /* IRQ0 */ }; gpio-sd0-pwr-en-hog { -- 2.7.4