From fe6f68e2bb8ba87612605cc0f6b55b188f002491 Mon Sep 17 00:00:00 2001 From: James Greenhalgh Date: Thu, 5 Sep 2013 15:53:37 +0000 Subject: [PATCH] [AArch64] Fix categorisation of the frecp* insns. gcc/ * config/aarch64/aarch64.md (type): Remove frecpe, frecps, frecpx. (aarch64_frecp): Move to aarch64-simd.md, fix to be a TARGET_SIMD instruction. (aarch64_frecps): Remove. * config/aarch64/aarch64-simd.md (aarch64_frecp): New, moved from aarch64.md (aarch64_frecps): Handle all float/vector of float modes. From-SVN: r202292 --- gcc/ChangeLog | 11 +++++++++++ gcc/config/aarch64/aarch64-simd.md | 18 ++++++++++++++---- gcc/config/aarch64/aarch64.md | 26 -------------------------- 3 files changed, 25 insertions(+), 30 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index f6c6b3b..91f41b1 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,4 +1,15 @@ 2013-09-05 James Greenhalgh + + * config/aarch64/aarch64.md + (type): Remove frecpe, frecps, frecpx. + (aarch64_frecp): Move to aarch64-simd.md, + fix to be a TARGET_SIMD instruction. + (aarch64_frecps): Remove. + * config/aarch64/aarch64-simd.md + (aarch64_frecp): New, moved from aarch64.md + (aarch64_frecps): Handle all float/vector of float modes. + +2013-09-05 James Greenhalgh Sofiane Naci * config/arm/types.md (define_attr "type"): diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index f4b929e..c085fb9 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -4179,13 +4179,23 @@ (set_attr "simd_mode" "")] ) +(define_insn "aarch64_frecp" + [(set (match_operand:GPF 0 "register_operand" "=w") + (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] + FRECP))] + "TARGET_SIMD" + "frecp\\t%0, %1" + [(set_attr "simd_type" "simd_frecp") + (set_attr "mode" "")] +) + (define_insn "aarch64_frecps" - [(set (match_operand:VDQF 0 "register_operand" "=w") - (unspec:VDQF [(match_operand:VDQF 1 "register_operand" "w") - (match_operand:VDQF 2 "register_operand" "w")] + [(set (match_operand:VALLF 0 "register_operand" "=w") + (unspec:VALLF [(match_operand:VALLF 1 "register_operand" "w") + (match_operand:VALLF 2 "register_operand" "w")] UNSPEC_FRECPS))] "TARGET_SIMD" - "frecps\\t%0., %1., %2." + "frecps\\t%0, %1, %2" [(set_attr "simd_type" "simd_frecps") (set_attr "simd_mode" "")] ) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 6cdff87..4dfd2ab 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -240,9 +240,6 @@ fmovf2i,\ fmovi2f,\ fmul,\ - frecpe,\ - frecps,\ - frecpx,\ frint,\ fsqrt,\ load_acq,\ @@ -3946,29 +3943,6 @@ (set_attr "mode" "")] ) -(define_insn "aarch64_frecp" - [(set (match_operand:GPF 0 "register_operand" "=w") - (unspec:GPF [(match_operand:GPF 1 "register_operand" "w")] - FRECP))] - "TARGET_FLOAT" - "frecp\\t%0, %1" - [(set_attr "v8type" "frecp") - (set_attr "type" "ffarith") - (set_attr "mode" "")] -) - -(define_insn "aarch64_frecps" - [(set (match_operand:GPF 0 "register_operand" "=w") - (unspec:GPF [(match_operand:GPF 1 "register_operand" "w") - (match_operand:GPF 2 "register_operand" "w")] - UNSPEC_FRECPS))] - "TARGET_FLOAT" - "frecps\\t%0, %1, %2" - [(set_attr "v8type" "frecps") - (set_attr "type" "ffarith") - (set_attr "mode" "")] -) - ;; ------------------------------------------------------------------- ;; Reload support ;; ------------------------------------------------------------------- -- 2.7.4