From fe282170487a7f021aca0af774091fcdf9a9c41b Mon Sep 17 00:00:00 2001 From: Roger Ferrer Ibanez Date: Mon, 27 Aug 2018 07:08:18 +0000 Subject: [PATCH] [RISCV] atomic_store_nn have a different layout to regular store We cannot directy reuse the patterns of StPat because for some reason the store DAG node and the atomic_store_nn DAG nodes put the ptr and the value in different positions. Currently we attempt to store the address to an address formed by the value. Differential Revision: https://reviews.llvm.org/D51217 llvm-svn: 340722 --- llvm/lib/Target/RISCV/RISCVInstrInfoA.td | 19 +++++++++++++++---- llvm/test/CodeGen/RISCV/atomic-load-store.ll | 24 ++++++++++++------------ 2 files changed, 27 insertions(+), 16 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td index 3793220..ef46892 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoA.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoA.td @@ -44,6 +44,17 @@ multiclass AMO_rr_aq_rl funct5, bits<3> funct3, string opcodestr> { def _AQ_RL : AMO_rr; } +multiclass AtomicStPat { + def : Pat<(StoreOp GPR:$rs1, StTy:$rs2), (Inst StTy:$rs2, GPR:$rs1, 0)>; + def : Pat<(StoreOp AddrFI:$rs1, StTy:$rs2), (Inst StTy:$rs2, AddrFI:$rs1, 0)>; + def : Pat<(StoreOp (add GPR:$rs1, simm12:$imm12), StTy:$rs2), + (Inst StTy:$rs2, GPR:$rs1, simm12:$imm12)>; + def : Pat<(StoreOp (add AddrFI:$rs1, simm12:$imm12), StTy:$rs2), + (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>; + def : Pat<(StoreOp (IsOrAdd AddrFI:$rs1, simm12:$imm12), StTy:$rs2), + (Inst StTy:$rs2, AddrFI:$rs1, simm12:$imm12)>; +} + //===----------------------------------------------------------------------===// // Instructions //===----------------------------------------------------------------------===// @@ -91,7 +102,7 @@ defm : LdPat; defm : LdPat; defm : LdPat; -defm : StPat; -defm : StPat; -defm : StPat; -} // Predicates = [HasStdExtF] +defm : AtomicStPat; +defm : AtomicStPat; +defm : AtomicStPat; +} // Predicates = [HasStdExtA] diff --git a/llvm/test/CodeGen/RISCV/atomic-load-store.ll b/llvm/test/CodeGen/RISCV/atomic-load-store.ll index 4e4a046..ba2b594 100644 --- a/llvm/test/CodeGen/RISCV/atomic-load-store.ll +++ b/llvm/test/CodeGen/RISCV/atomic-load-store.ll @@ -350,7 +350,7 @@ define void @atomic_store_i8_unordered(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomic_store_i8_unordered: ; RV32IA: # %bb.0: -; RV32IA-NEXT: sb a0, 0(a1) +; RV32IA-NEXT: sb a1, 0(a0) ; RV32IA-NEXT: ret store atomic i8 %b, i8* %a unordered, align 1 ret void @@ -369,7 +369,7 @@ define void @atomic_store_i8_monotonic(i8 *%a, i8 %b) nounwind { ; ; RV32IA-LABEL: atomic_store_i8_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: sb a0, 0(a1) +; RV32IA-NEXT: sb a1, 0(a0) ; RV32IA-NEXT: ret store atomic i8 %b, i8* %a monotonic, align 1 ret void @@ -389,7 +389,7 @@ define void @atomic_store_i8_release(i8 *%a, i8 %b) nounwind { ; RV32IA-LABEL: atomic_store_i8_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: fence rw, w -; RV32IA-NEXT: sb a0, 0(a1) +; RV32IA-NEXT: sb a1, 0(a0) ; RV32IA-NEXT: ret store atomic i8 %b, i8* %a release, align 1 ret void @@ -409,7 +409,7 @@ define void @atomic_store_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; RV32IA-LABEL: atomic_store_i8_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: fence rw, w -; RV32IA-NEXT: sb a0, 0(a1) +; RV32IA-NEXT: sb a1, 0(a0) ; RV32IA-NEXT: ret store atomic i8 %b, i8* %a seq_cst, align 1 ret void @@ -428,7 +428,7 @@ define void @atomic_store_i16_unordered(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomic_store_i16_unordered: ; RV32IA: # %bb.0: -; RV32IA-NEXT: sh a0, 0(a1) +; RV32IA-NEXT: sh a1, 0(a0) ; RV32IA-NEXT: ret store atomic i16 %b, i16* %a unordered, align 2 ret void @@ -447,7 +447,7 @@ define void @atomic_store_i16_monotonic(i16 *%a, i16 %b) nounwind { ; ; RV32IA-LABEL: atomic_store_i16_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: sh a0, 0(a1) +; RV32IA-NEXT: sh a1, 0(a0) ; RV32IA-NEXT: ret store atomic i16 %b, i16* %a monotonic, align 2 ret void @@ -467,7 +467,7 @@ define void @atomic_store_i16_release(i16 *%a, i16 %b) nounwind { ; RV32IA-LABEL: atomic_store_i16_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: fence rw, w -; RV32IA-NEXT: sh a0, 0(a1) +; RV32IA-NEXT: sh a1, 0(a0) ; RV32IA-NEXT: ret store atomic i16 %b, i16* %a release, align 2 ret void @@ -487,7 +487,7 @@ define void @atomic_store_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; RV32IA-LABEL: atomic_store_i16_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: fence rw, w -; RV32IA-NEXT: sh a0, 0(a1) +; RV32IA-NEXT: sh a1, 0(a0) ; RV32IA-NEXT: ret store atomic i16 %b, i16* %a seq_cst, align 2 ret void @@ -506,7 +506,7 @@ define void @atomic_store_i32_unordered(i32 *%a, i32 %b) nounwind { ; ; RV32IA-LABEL: atomic_store_i32_unordered: ; RV32IA: # %bb.0: -; RV32IA-NEXT: sw a0, 0(a1) +; RV32IA-NEXT: sw a1, 0(a0) ; RV32IA-NEXT: ret store atomic i32 %b, i32* %a unordered, align 4 ret void @@ -525,7 +525,7 @@ define void @atomic_store_i32_monotonic(i32 *%a, i32 %b) nounwind { ; ; RV32IA-LABEL: atomic_store_i32_monotonic: ; RV32IA: # %bb.0: -; RV32IA-NEXT: sw a0, 0(a1) +; RV32IA-NEXT: sw a1, 0(a0) ; RV32IA-NEXT: ret store atomic i32 %b, i32* %a monotonic, align 4 ret void @@ -545,7 +545,7 @@ define void @atomic_store_i32_release(i32 *%a, i32 %b) nounwind { ; RV32IA-LABEL: atomic_store_i32_release: ; RV32IA: # %bb.0: ; RV32IA-NEXT: fence rw, w -; RV32IA-NEXT: sw a0, 0(a1) +; RV32IA-NEXT: sw a1, 0(a0) ; RV32IA-NEXT: ret store atomic i32 %b, i32* %a release, align 4 ret void @@ -565,7 +565,7 @@ define void @atomic_store_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; RV32IA-LABEL: atomic_store_i32_seq_cst: ; RV32IA: # %bb.0: ; RV32IA-NEXT: fence rw, w -; RV32IA-NEXT: sw a0, 0(a1) +; RV32IA-NEXT: sw a1, 0(a0) ; RV32IA-NEXT: ret store atomic i32 %b, i32* %a seq_cst, align 4 ret void -- 2.7.4