From fe0152e21602bde2feae1b521f719d5856f2c2d2 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Mon, 15 Aug 2022 18:12:54 -0700 Subject: [PATCH] iris: Pass devinfo to iris_resource_level_has_hiz() This will let us enforce 8x4 alignment rules differently based on the specific hardware generation in question. Reviewed-by: Nanley Chery Part-of: --- src/gallium/drivers/iris/iris_clear.c | 2 +- src/gallium/drivers/iris/iris_resolve.c | 16 +++++++++++----- src/gallium/drivers/iris/iris_resource.h | 3 ++- src/gallium/drivers/iris/iris_state.c | 6 ++++-- 4 files changed, 18 insertions(+), 9 deletions(-) diff --git a/src/gallium/drivers/iris/iris_clear.c b/src/gallium/drivers/iris/iris_clear.c index 409a0ef..300d576 100644 --- a/src/gallium/drivers/iris/iris_clear.c +++ b/src/gallium/drivers/iris/iris_clear.c @@ -405,7 +405,7 @@ can_fast_clear_depth(struct iris_context *ice, return false; } - if (!iris_resource_level_has_hiz(res, level)) + if (!iris_resource_level_has_hiz(devinfo, res, level)) return false; if (!blorp_can_hiz_clear_depth(devinfo, &res->surf, res->aux.usage, diff --git a/src/gallium/drivers/iris/iris_resolve.c b/src/gallium/drivers/iris/iris_resolve.c index 1b485f5..cee24f9 100644 --- a/src/gallium/drivers/iris/iris_resolve.c +++ b/src/gallium/drivers/iris/iris_resolve.c @@ -515,7 +515,7 @@ iris_sample_with_depth_aux(const struct intel_device_info *devinfo, } for (unsigned level = 0; level < res->surf.levels; ++level) { - if (!iris_resource_level_has_hiz(res, level)) + if (!iris_resource_level_has_hiz(devinfo, res, level)) return false; } @@ -548,7 +548,9 @@ iris_hiz_exec(struct iris_context *ice, unsigned int num_layers, enum isl_aux_op op, bool update_clear_depth) { - assert(iris_resource_level_has_hiz(res, level)); + struct intel_device_info *devinfo = &batch->screen->devinfo; + + assert(iris_resource_level_has_hiz(devinfo, res, level)); assert(op != ISL_AUX_OP_NONE); UNUSED const char *name = NULL; @@ -632,7 +634,8 @@ iris_hiz_exec(struct iris_context *ice, * Does the resource's slice have hiz enabled? */ bool -iris_resource_level_has_hiz(const struct iris_resource *res, uint32_t level) +iris_resource_level_has_hiz(const struct intel_device_info *devinfo, + const struct iris_resource *res, uint32_t level) { iris_resource_check_level_layer(res, level, 0); @@ -831,10 +834,13 @@ iris_resource_set_aux_state(struct iris_context *ice, uint32_t start_layer, uint32_t num_layers, enum isl_aux_state aux_state) { + struct iris_screen *screen = (void *) ice->ctx.screen; + struct intel_device_info *devinfo = &screen->devinfo; + num_layers = miptree_layer_range_length(res, level, start_layer, num_layers); if (res->surf.usage & ISL_SURF_USAGE_DEPTH_BIT) { - assert(iris_resource_level_has_hiz(res, level) || + assert(iris_resource_level_has_hiz(devinfo, res, level) || !isl_aux_state_has_valid_aux(aux_state)); } else { assert(res->surf.samples == 1 || @@ -1051,7 +1057,7 @@ iris_resource_render_aux_usage(struct iris_context *ice, case ISL_AUX_USAGE_HIZ_CCS: case ISL_AUX_USAGE_HIZ_CCS_WT: assert(render_format == res->surf.format); - return iris_resource_level_has_hiz(res, level) ? + return iris_resource_level_has_hiz(devinfo, res, level) ? res->aux.usage : ISL_AUX_USAGE_NONE; case ISL_AUX_USAGE_STC_CCS: diff --git a/src/gallium/drivers/iris/iris_resource.h b/src/gallium/drivers/iris/iris_resource.h index c188dde..660f335 100644 --- a/src/gallium/drivers/iris/iris_resource.h +++ b/src/gallium/drivers/iris/iris_resource.h @@ -481,7 +481,8 @@ bool iris_has_invalid_primary(const struct iris_resource *res, void iris_resource_check_level_layer(const struct iris_resource *res, uint32_t level, uint32_t layer); -bool iris_resource_level_has_hiz(const struct iris_resource *res, +bool iris_resource_level_has_hiz(const struct intel_device_info *devinfo, + const struct iris_resource *res, uint32_t level); bool iris_sample_with_depth_aux(const struct intel_device_info *devinfo, diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 727fec3..de36a29 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -1678,7 +1678,8 @@ want_pma_fix(struct iris_context *ice) /* 3DSTATE_DEPTH_BUFFER::SURFACE_TYPE != NULL && * 3DSTATE_DEPTH_BUFFER::HIZ Enable && */ - if (!zres || !iris_resource_level_has_hiz(zres, cso_fb->zsbuf->u.tex.level)) + if (!zres || + !iris_resource_level_has_hiz(devinfo, zres, cso_fb->zsbuf->u.tex.level)) return false; /* 3DSTATE_WM::EDSC_Mode != EDSC_PREPS */ @@ -3216,6 +3217,7 @@ iris_set_framebuffer_state(struct pipe_context *ctx, { struct iris_context *ice = (struct iris_context *) ctx; struct iris_screen *screen = (struct iris_screen *)ctx->screen; + const struct intel_device_info *devinfo = &screen->devinfo; struct isl_device *isl_dev = &screen->isl_dev; struct pipe_framebuffer_state *cso = &ice->state.framebuffer; struct iris_resource *zres; @@ -3285,7 +3287,7 @@ iris_set_framebuffer_state(struct pipe_context *ctx, view.format = zres->surf.format; - if (iris_resource_level_has_hiz(zres, view.base_level)) { + if (iris_resource_level_has_hiz(devinfo, zres, view.base_level)) { info.hiz_usage = zres->aux.usage; info.hiz_surf = &zres->aux.surf; info.hiz_address = zres->aux.bo->address + zres->aux.offset; -- 2.7.4