From fdfbed383e48f9a6fce6ef1e0e0defea0363ac3f Mon Sep 17 00:00:00 2001 From: Li Jia He Date: Wed, 26 Jun 2019 08:23:06 +0000 Subject: [PATCH] [RS6000] Change maddld match_operand from DI to GPR From PowerPC ISA3.0, the description of `maddld RT, RA.RB, RC` is as follows: 64-bit RA and RB are multiplied and then the RC is signed extend to 128 bits, and add them together. We only apply it to 64-bit mode (DI) when implementing maddld. However, if we can guarantee that the result of the maddld operation will be limited to 32-bit mode (SI), we can still apply it to 32-bit mode (SI). gcc/ChangeLog 2019-06-26 Li Jia He * config/rs6000/rs6000.h (TARGET_MADDLD): Remove the restriction of TARGET_POWERPC64. * config/rs6000/rs6000.md (maddld): Change maddld match_operand from DI to GPR. gcc/testsuite/ChangeLog 2019-06-26 Li Jia He * gcc.target/powerpc/maddld-1.c: New testcase. From-SVN: r272673 --- gcc/ChangeLog | 7 +++++++ gcc/config/rs6000/rs6000.h | 2 +- gcc/config/rs6000/rs6000.md | 10 +++++----- gcc/testsuite/ChangeLog | 4 ++++ gcc/testsuite/gcc.target/powerpc/maddld-1.c | 21 +++++++++++++++++++++ 5 files changed, 38 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/powerpc/maddld-1.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 896ca57..f8d3574 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,10 @@ +2019-06-26 Li Jia He + + * config/rs6000/rs6000.h (TARGET_MADDLD): Remove the restriction of + TARGET_POWERPC64. + * config/rs6000/rs6000.md (maddld): Change maddld match_operand from DI + to GPR. + 2019-06-26 Segher Boessenkool * doc/invoke.texi (Warning Options): Fix some @opindex syntax. diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index a211171..0a2c0bc 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -453,7 +453,7 @@ extern int rs6000_vector_align[]; #define TARGET_FCTIWUZ TARGET_POPCNTD #define TARGET_CTZ TARGET_MODULO #define TARGET_EXTSWSLI (TARGET_MODULO && TARGET_POWERPC64) -#define TARGET_MADDLD (TARGET_MODULO && TARGET_POWERPC64) +#define TARGET_MADDLD TARGET_MODULO #define TARGET_XSCVDPSPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) #define TARGET_XSCVSPDPN (TARGET_DIRECT_MOVE || TARGET_P8_VECTOR) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index b04c7055..9445d5f 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3062,11 +3062,11 @@ DONE; }) -(define_insn "*maddld4" - [(set (match_operand:DI 0 "gpc_reg_operand" "=r") - (plus:DI (mult:DI (match_operand:DI 1 "gpc_reg_operand" "r") - (match_operand:DI 2 "gpc_reg_operand" "r")) - (match_operand:DI 3 "gpc_reg_operand" "r")))] +(define_insn "*maddld4" + [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") + (plus:GPR (mult:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") + (match_operand:GPR 2 "gpc_reg_operand" "r")) + (match_operand:GPR 3 "gpc_reg_operand" "r")))] "TARGET_MADDLD" "maddld %0,%1,%2,%3" [(set_attr "type" "mul")]) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index fd34b5e..5b54f28 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,7 @@ +2019-06-26 Li Jia He + + * gcc.target/powerpc/maddld-1.c: New testcase. + 2019-06-06 Hongtao Liu Olga Makhotina diff --git a/gcc/testsuite/gcc.target/powerpc/maddld-1.c b/gcc/testsuite/gcc.target/powerpc/maddld-1.c new file mode 100644 index 0000000..4edecf1 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/maddld-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ + +/* This file tests the maddld instruction can be used in SI mode + on power9 machine. */ + +int +s_madd (int a, int b, int c) +{ + return (a * b) + c; +} + +unsigned int +u_madd (unsigned int a, unsigned int b, unsigned int c) +{ + return (a * b) + c; +} + +/* { dg-final { scan-assembler-times {\mmaddld\s} 2 } } */ +/* { dg-final { scan-assembler-not {\mmul} } } */ +/* { dg-final { scan-assembler-not {\madd} } } */ -- 2.7.4