From fdf589321c5acfce67c18dc2455fc3a54fd86135 Mon Sep 17 00:00:00 2001 From: Qiang Yu Date: Mon, 23 May 2022 17:23:57 +0800 Subject: [PATCH] ac/nir: add nir_intrinsic_load_hs_out_patch_data_offset_amd MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Also add radv and radeonsi implementation. Will be used in tess lowering. Reviewed-by: Marek Olšák Acked-by: Pierre-Eric Pelloux-Prayer Reviewed-by: Timur Kristóf Signed-off-by: Qiang Yu Part-of: --- src/amd/llvm/ac_nir_to_llvm.c | 1 + src/amd/vulkan/radv_nir_lower_abi.c | 12 +++++++++++- src/compiler/nir/nir_divergence_analysis.c | 1 + src/compiler/nir/nir_intrinsics.py | 3 +++ src/gallium/drivers/radeonsi/si_shader_llvm.c | 3 +++ 5 files changed, 19 insertions(+), 1 deletion(-) diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index c116543..fd6fa80 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -3638,6 +3638,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins case nir_intrinsic_load_ring_esgs_amd: case nir_intrinsic_load_lshs_vertex_stride_amd: case nir_intrinsic_load_tcs_num_patches_amd: + case nir_intrinsic_load_hs_out_patch_data_offset_amd: result = ctx->abi->intrinsic_load(ctx->abi, instr->intrinsic); break; case nir_intrinsic_load_vertex_id: diff --git a/src/amd/vulkan/radv_nir_lower_abi.c b/src/amd/vulkan/radv_nir_lower_abi.c index 3aac76b..0cd9fec 100644 --- a/src/amd/vulkan/radv_nir_lower_abi.c +++ b/src/amd/vulkan/radv_nir_lower_abi.c @@ -197,6 +197,15 @@ lower_abi_instr(nir_builder *b, nir_instr *instr, void *state) return nir_imm_int(b, io_num * 16); } + case nir_intrinsic_load_hs_out_patch_data_offset_amd: { + unsigned num_patches = s->info->num_tess_patches; + unsigned out_vertices_per_patch = b->shader->info.tess.tcs_vertices_out; + unsigned num_tcs_outputs = stage == MESA_SHADER_TESS_CTRL ? + s->info->tcs.num_linked_outputs : s->info->tes.num_linked_inputs; + int per_vertex_output_patch_size = out_vertices_per_patch * num_tcs_outputs * 16u; + return nir_imm_int(b, num_patches * per_vertex_output_patch_size); + } + default: unreachable("invalid NIR RADV ABI intrinsic."); } @@ -243,7 +252,8 @@ filter_abi_instr(const nir_instr *instr, intrin->intrinsic == nir_intrinsic_load_task_ring_entry_amd || intrin->intrinsic == nir_intrinsic_load_task_ib_addr || intrin->intrinsic == nir_intrinsic_load_task_ib_stride || - intrin->intrinsic == nir_intrinsic_load_lshs_vertex_stride_amd; + intrin->intrinsic == nir_intrinsic_load_lshs_vertex_stride_amd || + intrin->intrinsic == nir_intrinsic_load_hs_out_patch_data_offset_amd; } void diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index 48033cc..6099e93 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -180,6 +180,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_load_mesh_inline_data_intel: case nir_intrinsic_load_ray_num_dss_rt_stacks_intel: case nir_intrinsic_load_lshs_vertex_stride_amd: + case nir_intrinsic_load_hs_out_patch_data_offset_amd: is_divergent = false; break; diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index b599594..197ae59 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1399,6 +1399,9 @@ intrinsic("store_shared2_amd", [2, 1], indices=[OFFSET0, OFFSET1, ST64]) # Vertex stride in LS-HS buffer system_value("lshs_vertex_stride_amd", 1) +# Per patch data offset in HS VRAM output buffer +system_value("hs_out_patch_data_offset_amd", 1) + # V3D-specific instrinc for tile buffer color reads. # # The hardware requires that we read the samples and components of a pixel diff --git a/src/gallium/drivers/radeonsi/si_shader_llvm.c b/src/gallium/drivers/radeonsi/si_shader_llvm.c index dd48b83..e00aeda 100644 --- a/src/gallium/drivers/radeonsi/si_shader_llvm.c +++ b/src/gallium/drivers/radeonsi/si_shader_llvm.c @@ -785,6 +785,9 @@ static LLVMValueRef si_llvm_load_intrinsic(struct ac_shader_abi *abi, nir_intrin si_unpack_param(ctx, ctx->tcs_offchip_layout, 0, 6), ctx->ac.i32_1, ""); + case nir_intrinsic_load_hs_out_patch_data_offset_amd: + return si_unpack_param(ctx, ctx->tcs_offchip_layout, 11, 21); + default: return NULL; } -- 2.7.4