From fdc0de19cb228bb1768b3dd882e79f8a0c5d6112 Mon Sep 17 00:00:00 2001
From: Sanjay Patel <spatel@rotateright.com>
Date: Wed, 19 Sep 2018 21:48:30 +0000
Subject: [PATCH] [SelectionDAG] allow vector types with isBitwiseNot()

The test diff in not-and-simplify.ll is from a use in SimplifyDemandedBits,
and the test diff in add.ll is from a DAGCombiner transform.

llvm-svn: 342594
---
 llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp  |  4 +---
 llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp |  5 ++++-
 llvm/test/CodeGen/X86/add.ll                   | 12 +++++-------
 llvm/test/CodeGen/X86/not-and-simplify.ll      |  2 +-
 4 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index df01543..1c80c38 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2009,10 +2009,8 @@ static SDValue foldAddSubOfSignBit(SDNode *N, SelectionDAG &DAG) {
     return SDValue();
 
   // The shift must be of a 'not' value.
-  // TODO: Use isBitwiseNot() if it works with vectors.
   SDValue Not = ShiftOp.getOperand(0);
-  if (!Not.hasOneUse() || Not.getOpcode() != ISD::XOR ||
-      !isAllOnesConstantOrAllOnesSplatConstant(Not.getOperand(1)))
+  if (!Not.hasOneUse() || !isBitwiseNot(Not))
     return SDValue();
 
   // The shift must be moving the sign bit to the least-significant-bit.
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index afe7bfb..5c8e8e5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -8191,7 +8191,10 @@ bool llvm::isOneConstant(SDValue V) {
 }
 
 bool llvm::isBitwiseNot(SDValue V) {
-  return V.getOpcode() == ISD::XOR && isAllOnesConstant(V.getOperand(1));
+  if (V.getOpcode() != ISD::XOR)
+    return false;
+  ConstantSDNode *C = isConstOrConstSplat(V.getOperand(1));
+  return C && C->isAllOnesValue();
 }
 
 ConstantSDNode *llvm::isConstOrConstSplat(SDValue N) {
diff --git a/llvm/test/CodeGen/X86/add.ll b/llvm/test/CodeGen/X86/add.ll
index 9feb45a..a8c254f 100644
--- a/llvm/test/CodeGen/X86/add.ll
+++ b/llvm/test/CodeGen/X86/add.ll
@@ -430,17 +430,15 @@ define <4 x i32> @inc_not_vec(<4 x i32> %a) nounwind {
 ;
 ; X64-LINUX-LABEL: inc_not_vec:
 ; X64-LINUX:       # %bb.0:
-; X64-LINUX-NEXT:    pcmpeqd %xmm1, %xmm1
-; X64-LINUX-NEXT:    pxor %xmm1, %xmm0
-; X64-LINUX-NEXT:    psubd %xmm1, %xmm0
+; X64-LINUX-NEXT:    pxor %xmm1, %xmm1
+; X64-LINUX-NEXT:    psubd %xmm0, %xmm1
+; X64-LINUX-NEXT:    movdqa %xmm1, %xmm0
 ; X64-LINUX-NEXT:    retq
 ;
 ; X64-WIN32-LABEL: inc_not_vec:
 ; X64-WIN32:       # %bb.0:
-; X64-WIN32-NEXT:    pcmpeqd %xmm1, %xmm1
-; X64-WIN32-NEXT:    movdqa (%rcx), %xmm0
-; X64-WIN32-NEXT:    pxor %xmm1, %xmm0
-; X64-WIN32-NEXT:    psubd %xmm1, %xmm0
+; X64-WIN32-NEXT:    pxor %xmm0, %xmm0
+; X64-WIN32-NEXT:    psubd (%rcx), %xmm0
 ; X64-WIN32-NEXT:    retq
   %nota = xor <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
   %r = add <4 x i32> %nota, <i32 1, i32 1, i32 1, i32 1>
diff --git a/llvm/test/CodeGen/X86/not-and-simplify.ll b/llvm/test/CodeGen/X86/not-and-simplify.ll
index 8fbe6e7..dfd22df 100644
--- a/llvm/test/CodeGen/X86/not-and-simplify.ll
+++ b/llvm/test/CodeGen/X86/not-and-simplify.ll
@@ -21,7 +21,7 @@ define <4 x i32> @shrink_xor_constant1_splat(<4 x i32> %x) {
 ; ALL-LABEL: shrink_xor_constant1_splat:
 ; ALL:       # %bb.0:
 ; ALL-NEXT:    psrld $31, %xmm0
-; ALL-NEXT:    pandn {{.*}}(%rip), %xmm0
+; ALL-NEXT:    pxor {{.*}}(%rip), %xmm0
 ; ALL-NEXT:    retq
   %sh = lshr <4 x i32> %x, <i32 31, i32 31, i32 31, i32 31>
   %not = xor <4 x i32> %sh, <i32 -1, i32 -1, i32 -1, i32 -1>
-- 
2.7.4