From fdba86972f23cab99710e19a04f36f170d1870e0 Mon Sep 17 00:00:00 2001 From: Michal Simek Date: Thu, 29 Nov 2018 10:31:02 +0100 Subject: [PATCH] ARM: zynq: Wire SPL configuration for cse nor/nand targets These symlinks are here only for testing purpose where SPL is used for soc configuration. Signed-off-by: Michal Simek --- board/xilinx/zynq/zynq-cse-nand | 1 + board/xilinx/zynq/zynq-cse-nor | 1 + 2 files changed, 2 insertions(+) create mode 120000 board/xilinx/zynq/zynq-cse-nand create mode 120000 board/xilinx/zynq/zynq-cse-nor diff --git a/board/xilinx/zynq/zynq-cse-nand b/board/xilinx/zynq/zynq-cse-nand new file mode 120000 index 0000000..9d89a99 --- /dev/null +++ b/board/xilinx/zynq/zynq-cse-nand @@ -0,0 +1 @@ +zynq-zc770-xm011 \ No newline at end of file diff --git a/board/xilinx/zynq/zynq-cse-nor b/board/xilinx/zynq/zynq-cse-nor new file mode 120000 index 0000000..bb80693 --- /dev/null +++ b/board/xilinx/zynq/zynq-cse-nor @@ -0,0 +1 @@ +zynq-zc770-xm012 \ No newline at end of file -- 2.7.4