From fd0f9d1196305a73859702e49bb304cc1e0af244 Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Wed, 22 Jan 2020 12:39:51 -0600 Subject: [PATCH] anv: Make AUX table invalidate a PIPE_* bit This commit moves it in with all the other cache invalidation operations as if it were done by PIPE_CONTROL even though it's a pair of register writes. This means we only have to write the GFX_AUX_TABLE_BASE_ADDR register once at device initialization instead of every invalidate. Invalidates are now a single LRI instead of two. Reviewed-by: Lionel Landwerlin Reviewed-by: Jordan Justen Part-of: --- src/intel/vulkan/anv_genX.h | 2 -- src/intel/vulkan/anv_private.h | 9 ++++++- src/intel/vulkan/genX_blorp_exec.c | 2 +- src/intel/vulkan/genX_cmd_buffer.c | 48 ++++++++++++++------------------------ src/intel/vulkan/genX_state.c | 14 +++++++++++ 5 files changed, 41 insertions(+), 34 deletions(-) diff --git a/src/intel/vulkan/anv_genX.h b/src/intel/vulkan/anv_genX.h index 8c2a0e4..142b083 100644 --- a/src/intel/vulkan/anv_genX.h +++ b/src/intel/vulkan/anv_genX.h @@ -62,8 +62,6 @@ void genX(flush_pipeline_select_gpgpu)(struct anv_cmd_buffer *cmd_buffer); void genX(cmd_buffer_config_l3)(struct anv_cmd_buffer *cmd_buffer, const struct gen_l3_config *cfg); -void genX(cmd_buffer_aux_map_state)(struct anv_cmd_buffer *cmd_buffer); - void genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer); void genX(cmd_buffer_flush_dynamic_state)(struct anv_cmd_buffer *cmd_buffer); diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 6b4698d..477e891 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -2224,6 +2224,12 @@ enum anv_pipe_bits { * before they can proceed with the copy. */ ANV_PIPE_RENDER_TARGET_BUFFER_WRITES = (1 << 22), + + /* This bit does not exist directly in PIPE_CONTROL. It means that Gen12 + * AUX-TT data has changed and we need to invalidate AUX-TT data. This is + * done by writing the AUX-TT register. + */ + ANV_PIPE_AUX_TABLE_INVALIDATE_BIT = (1 << 23), }; #define ANV_PIPE_FLUSH_BITS ( \ @@ -2243,7 +2249,8 @@ enum anv_pipe_bits { ANV_PIPE_VF_CACHE_INVALIDATE_BIT | \ ANV_PIPE_DATA_CACHE_FLUSH_BIT | \ ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT | \ - ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT) + ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT | \ + ANV_PIPE_AUX_TABLE_INVALIDATE_BIT) static inline enum anv_pipe_bits anv_pipe_flush_bits_for_access_flags(VkAccessFlags flags) diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c index fed4455..e2f846a 100644 --- a/src/intel/vulkan/genX_blorp_exec.c +++ b/src/intel/vulkan/genX_blorp_exec.c @@ -260,7 +260,7 @@ genX(blorp_exec)(struct blorp_batch *batch, genX(flush_pipeline_select_3d)(cmd_buffer); #if GEN_GEN >= 12 - genX(cmd_buffer_aux_map_state)(cmd_buffer); + cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT; #endif genX(cmd_buffer_emit_gen7_depth_flush)(cmd_buffer); diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 5fbdf93..ff213dc 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1457,6 +1457,12 @@ genX(BeginCommandBuffer)( */ cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT; + /* Re-emit the aux table register in every command buffer. This way we're + * ensured that we have the table even if this command buffer doesn't + * initialize any images. + */ + cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT; + /* We send an "Indirect State Pointers Disable" packet at * EndCommandBuffer, so all push contant packets are ignored during a * context restore. Documentation says after that command, we need to @@ -2012,6 +2018,16 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer) } } +#if GEN_GEN == 12 + if ((bits & ANV_PIPE_AUX_TABLE_INVALIDATE_BIT) && + cmd_buffer->device->info.has_aux_map) { + anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(GFX_CCS_AUX_INV_num); + lri.DataDWord = 1; + } + } +#endif + bits &= ~ANV_PIPE_INVALIDATE_BITS; } @@ -2847,34 +2863,6 @@ cmd_buffer_flush_push_constants(struct anv_cmd_buffer *cmd_buffer, cmd_buffer->state.push_constants_dirty &= ~flushed; } -#if GEN_GEN >= 12 -void -genX(cmd_buffer_aux_map_state)(struct anv_cmd_buffer *cmd_buffer) -{ - void *aux_map_ctx = cmd_buffer->device->aux_map_ctx; - if (!aux_map_ctx) - return; - uint32_t aux_map_state_num = gen_aux_map_get_state_num(aux_map_ctx); - if (cmd_buffer->state.last_aux_map_state != aux_map_state_num) { - /* If the aux-map state number increased, then we need to rewrite the - * register. Rewriting the register is used to both set the aux-map - * translation table address, and also to invalidate any previously - * cached translations. - */ - uint64_t base_addr = gen_aux_map_get_base(aux_map_ctx); - anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) { - lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num); - lri.DataDWord = base_addr & 0xffffffff; - } - anv_batch_emit(&cmd_buffer->batch, GENX(MI_LOAD_REGISTER_IMM), lri) { - lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num) + 4; - lri.DataDWord = base_addr >> 32; - } - cmd_buffer->state.last_aux_map_state = aux_map_state_num; - } -} -#endif - void genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) { @@ -2894,7 +2882,7 @@ genX(cmd_buffer_flush_state)(struct anv_cmd_buffer *cmd_buffer) genX(flush_pipeline_select_3d)(cmd_buffer); #if GEN_GEN >= 12 - genX(cmd_buffer_aux_map_state)(cmd_buffer); + cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT; #endif if (vb_emit) { @@ -3787,7 +3775,7 @@ genX(cmd_buffer_flush_compute_state)(struct anv_cmd_buffer *cmd_buffer) genX(flush_pipeline_select_gpgpu)(cmd_buffer); #if GEN_GEN >= 12 - genX(cmd_buffer_aux_map_state)(cmd_buffer); + cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_AUX_TABLE_INVALIDATE_BIT; #endif if (cmd_buffer->state.compute.pipeline_dirty) { diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index 877d3c0..84c4347 100644 --- a/src/intel/vulkan/genX_state.c +++ b/src/intel/vulkan/genX_state.c @@ -29,6 +29,7 @@ #include "anv_private.h" +#include "common/gen_aux_map.h" #include "common/gen_sample_positions.h" #include "genxml/gen_macros.h" #include "genxml/genX_pack.h" @@ -238,6 +239,19 @@ genX(init_device_state)(struct anv_device *device) } #endif +#if GEN_GEN == 12 + uint64_t aux_base_addr = gen_aux_map_get_base(device->aux_map_ctx); + assert(aux_base_addr % (32 * 1024) == 0); + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num); + lri.DataDWord = aux_base_addr & 0xffffffff; + } + anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) { + lri.RegisterOffset = GENX(GFX_AUX_TABLE_BASE_ADDR_num) + 4; + lri.DataDWord = aux_base_addr >> 32; + } +#endif + /* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so * 3DSTATE_CONSTANT_XS buffer 0 is an absolute address. * -- 2.7.4