From fc99e1a82b8728e1afbd6f9824d106f7153a5218 Mon Sep 17 00:00:00 2001 From: Marek Szyprowski Date: Fri, 8 Dec 2017 15:53:55 +0100 Subject: [PATCH] ARM: dts: exynos: Add audio power domain to Exynos5250 Audio power domain includes following hardware modules: Pin controller for GPZ bank, AudioSS clock controller and three Exynos I2S controller. Signed-off-by: Marek Szyprowski Signed-off-by: Krzysztof Kozlowski --- arch/arm/boot/dts/exynos5250.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 95f1104..327f748 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -204,6 +204,13 @@ clock-names = "oscclk", "clk0", "clk1"; }; + pd_mau: power-domain@100440C0 { + compatible = "samsung,exynos4210-pd"; + reg = <0x100440C0 0x20>; + #power-domain-cells = <0>; + label = "MAU"; + }; + clock: clock-controller@10010000 { compatible = "samsung,exynos5250-clock"; reg = <0x10010000 0x30000>; @@ -217,6 +224,7 @@ clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in"; + power-domains = <&pd_mau>; }; timer { @@ -291,6 +299,7 @@ compatible = "samsung,exynos5250-pinctrl"; reg = <0x03860000 0x1000>; interrupts = ; + power-domains = <&pd_mau>; }; pmu_system_controller: system-controller@10040000 { @@ -554,6 +563,7 @@ samsung,idma-addr = <0x03000000>; pinctrl-names = "default"; pinctrl-0 = <&i2s0_bus>; + power-domains = <&pd_mau>; }; i2s1: i2s@12D60000 { @@ -567,6 +577,7 @@ clock-names = "iis", "i2s_opclk0"; pinctrl-names = "default"; pinctrl-0 = <&i2s1_bus>; + power-domains = <&pd_mau>; }; i2s2: i2s@12D70000 { @@ -580,6 +591,7 @@ clock-names = "iis", "i2s_opclk0"; pinctrl-names = "default"; pinctrl-0 = <&i2s2_bus>; + power-domains = <&pd_mau>; }; usb_dwc3 { -- 2.7.4