From fc371558a0e51e0690c37659f7f88d56c16ec698 Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Mon, 24 Oct 2016 21:36:43 +0000 Subject: [PATCH] Use MachineInstr::mop_iterator instead of MIOperands; NFC (Const)?MIOperands is equivalent to the C++ style MachineInstr::mop_iterator. Use the latter for consistency except for a few callers of MIOperands::analyzePhysReg(). llvm-svn: 285029 --- llvm/lib/CodeGen/MachinePipeliner.cpp | 12 ++++---- llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp | 34 +++++++++++----------- llvm/lib/Target/Hexagon/HexagonGenInsert.cpp | 6 ++-- llvm/lib/Target/Hexagon/HexagonGenMux.cpp | 8 ++--- llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp | 6 ++-- .../lib/Target/Hexagon/HexagonHazardRecognizer.cpp | 6 ++-- 6 files changed, 36 insertions(+), 36 deletions(-) diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index 516296c..37455c5 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -1726,9 +1726,9 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker, const MachineInstr *MI = SU->getInstr(); if (MI->isPHI()) continue; - for (ConstMIOperands MO(*MI); MO.isValid(); ++MO) - if (MO->isReg() && MO->isUse()) { - unsigned Reg = MO->getReg(); + for (const MachineOperand &MO : MI->operands()) + if (MO.isReg() && MO.isUse()) { + unsigned Reg = MO.getReg(); if (TargetRegisterInfo::isVirtualRegister(Reg)) Uses.insert(Reg); else if (MRI.isAllocatable(Reg)) @@ -1737,9 +1737,9 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker, } } for (SUnit *SU : NS) - for (ConstMIOperands MO(*SU->getInstr()); MO.isValid(); ++MO) - if (MO->isReg() && MO->isDef() && !MO->isDead()) { - unsigned Reg = MO->getReg(); + for (const MachineOperand &MO : SU->getInstr()->operands()) + if (MO.isReg() && MO.isDef() && !MO.isDead()) { + unsigned Reg = MO.getReg(); if (TargetRegisterInfo::isVirtualRegister(Reg)) { if (!Uses.count(Reg)) LiveOutRegs.push_back(RegisterMaskPair(Reg, 0)); diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp index 77b3aeb..d9a6f05 100644 --- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp +++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp @@ -357,10 +357,10 @@ bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B) // update the use of it after predication). PHI uses will be updated // to use a result of a MUX, and a MUX cannot be created for predicate // registers. - for (ConstMIOperands MO(MI); MO.isValid(); ++MO) { - if (!MO->isReg() || !MO->isDef()) + for (const MachineOperand &MO : MI.operands()) { + if (!MO.isReg() || !MO.isDef()) continue; - unsigned R = MO->getReg(); + unsigned R = MO.getReg(); if (!TargetRegisterInfo::isVirtualRegister(R)) continue; if (MRI->getRegClass(R) != &Hexagon::PredRegsRegClass) @@ -375,10 +375,10 @@ bool HexagonEarlyIfConversion::isValidCandidate(const MachineBasicBlock *B) bool HexagonEarlyIfConversion::usesUndefVReg(const MachineInstr *MI) const { - for (ConstMIOperands MO(*MI); MO.isValid(); ++MO) { - if (!MO->isReg() || !MO->isUse()) + for (const MachineOperand &MO : MI->operands()) { + if (!MO.isReg() || !MO.isUse()) continue; - unsigned R = MO->getReg(); + unsigned R = MO.getReg(); if (!TargetRegisterInfo::isVirtualRegister(R)) continue; const MachineInstr *DefI = MRI->getVRegDef(R); @@ -454,10 +454,10 @@ unsigned HexagonEarlyIfConversion::countPredicateDefs( const MachineBasicBlock *B) const { unsigned PredDefs = 0; for (auto &MI : *B) { - for (ConstMIOperands MO(MI); MO.isValid(); ++MO) { - if (!MO->isReg() || !MO->isDef()) + for (const MachineOperand &MO : MI.operands()) { + if (!MO.isReg() || !MO.isDef()) continue; - unsigned R = MO->getReg(); + unsigned R = MO.getReg(); if (!TargetRegisterInfo::isVirtualRegister(R)) continue; if (MRI->getRegClass(R) == &Hexagon::PredRegsRegClass) @@ -669,14 +669,14 @@ void HexagonEarlyIfConversion::predicateInstr(MachineBasicBlock *ToB, unsigned COpc = getCondStoreOpcode(Opc, IfTrue); assert(COpc); MachineInstrBuilder MIB = BuildMI(*ToB, At, DL, HII->get(COpc)); - MIOperands MO(*MI); + MachineInstr::mop_iterator MOI = MI->operands_begin(); if (HII->isPostIncrement(*MI)) { - MIB.addOperand(*MO); - ++MO; + MIB.addOperand(*MOI); + ++MOI; } MIB.addReg(PredR); - for (; MO.isValid(); ++MO) - MIB.addOperand(*MO); + for (const MachineOperand &MO : make_range(MOI, MI->operands_end())) + MIB.addOperand(MO); // Set memory references. MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); @@ -949,9 +949,9 @@ void HexagonEarlyIfConversion::replacePhiEdges(MachineBasicBlock *OldB, MachineBasicBlock::iterator P, N = SB->getFirstNonPHI(); for (P = SB->begin(); P != N; ++P) { MachineInstr &PN = *P; - for (MIOperands MO(PN); MO.isValid(); ++MO) - if (MO->isMBB() && MO->getMBB() == OldB) - MO->setMBB(NewB); + for (MachineOperand &MO : PN.operands()) + if (MO.isMBB() && MO.getMBB() == OldB) + MO.setMBB(NewB); } } } diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp index ae45fb3..302ccad 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp @@ -1444,10 +1444,10 @@ bool HexagonGenInsert::removeDeadCode(MachineDomTreeNode *N) { bool AllDead = true; SmallVector Regs; - for (ConstMIOperands Op(*MI); Op.isValid(); ++Op) { - if (!Op->isReg() || !Op->isDef()) + for (const MachineOperand &MO : MI->operands()) { + if (!MO.isReg() || !MO.isDef()) continue; - unsigned R = Op->getReg(); + unsigned R = MO.getReg(); if (!TargetRegisterInfo::isVirtualRegister(R) || !MRI->use_nodbg_empty(R)) { AllDead = false; diff --git a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp index a0f1c7e..c780db8 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenMux.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenMux.cpp @@ -132,11 +132,11 @@ void HexagonGenMux::getDefsUses(const MachineInstr *MI, BitVector &Defs, expandReg(*R++, Uses); // Look over all operands, and collect explicit defs and uses. - for (ConstMIOperands Mo(*MI); Mo.isValid(); ++Mo) { - if (!Mo->isReg() || Mo->isImplicit()) + for (const MachineOperand &MO : MI->operands()) { + if (!MO.isReg() || MO.isImplicit()) continue; - unsigned R = Mo->getReg(); - BitVector &Set = Mo->isDef() ? Defs : Uses; + unsigned R = MO.getReg(); + BitVector &Set = MO.isDef() ? Defs : Uses; expandReg(R, Set); } } diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp index cb07f07..52a25d6 100644 --- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp +++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp @@ -330,9 +330,9 @@ bool HexagonGenPredicate::isScalarPred(Register PredReg) { case Hexagon::C4_or_orn: case Hexagon::C2_xor: // Add operands to the queue. - for (ConstMIOperands Mo(*DefI); Mo.isValid(); ++Mo) - if (Mo->isReg() && Mo->isUse()) - WorkQ.push(Register(Mo->getReg())); + for (const MachineOperand &MO : DefI->operands()) + if (MO.isReg() && MO.isUse()) + WorkQ.push(Register(MO.getReg())); break; // All non-vector compares are ok, everything else is bad. diff --git a/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp b/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp index 8fcd782..712030b 100644 --- a/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp +++ b/llvm/lib/Target/Hexagon/HexagonHazardRecognizer.cpp @@ -96,9 +96,9 @@ void HexagonHazardRecognizer::EmitInstruction(SUnit *SU) { // Keep the set of definitions for each packet, which is used to determine // if a .new can be used. - for (ConstMIOperands MO(*MI); MO.isValid(); ++MO) - if (MO->isReg() && MO->isDef() && !MO->isImplicit()) - RegDefs.insert(MO->getReg()); + for (const MachineOperand &MO : MI->operands()) + if (MO.isReg() && MO.isDef() && !MO.isImplicit()) + RegDefs.insert(MO.getReg()); if (TII->isZeroCost(MI->getOpcode())) return; -- 2.7.4