From fc0892c1f9a3e223f18d2cc38ca83c95d2415d54 Mon Sep 17 00:00:00 2001 From: Michael Roe Date: Fri, 30 Oct 2020 10:57:22 +0300 Subject: [PATCH] [mips] Implement add.ps, mul.ps and sub.ps Differential revision: https://reviews.llvm.org/D90321 --- llvm/lib/Target/Mips/MipsInstrFPU.td | 9 +++++++++ llvm/lib/Target/Mips/MipsSchedule.td | 3 +++ llvm/lib/Target/Mips/MipsScheduleGeneric.td | 5 +++-- llvm/lib/Target/Mips/MipsScheduleP5600.td | 4 ++-- llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s | 3 --- llvm/test/MC/Mips/mips1/invalid-mips5.s | 3 +++ llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s | 3 --- llvm/test/MC/Mips/mips2/invalid-mips5.s | 3 +++ llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s | 4 ---- llvm/test/MC/Mips/mips3/invalid-mips5.s | 3 +++ llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s | 3 --- llvm/test/MC/Mips/mips4/invalid-mips5.s | 3 +++ llvm/test/MC/Mips/mips64r2/valid-xfail.s | 3 --- llvm/test/MC/Mips/mips64r2/valid.s | 3 +++ llvm/test/MC/Mips/mips64r3/valid-xfail.s | 3 --- llvm/test/MC/Mips/mips64r3/valid.s | 2 ++ llvm/test/MC/Mips/mips64r5/valid-xfail.s | 3 --- llvm/test/MC/Mips/mips64r5/valid.s | 2 ++ llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s | 3 --- llvm/test/MC/Mips/mips64r6/invalid-mips5.s | 3 +++ 20 files changed, 39 insertions(+), 29 deletions(-) diff --git a/llvm/lib/Target/Mips/MipsInstrFPU.td b/llvm/lib/Target/Mips/MipsInstrFPU.td index 5696df9..14590dd 100644 --- a/llvm/lib/Target/Mips/MipsInstrFPU.td +++ b/llvm/lib/Target/Mips/MipsInstrFPU.td @@ -452,6 +452,12 @@ let AdditionalPredicates = [NotInMicroMips] in { let DecoderNamespace = "MipsFP64" in { let AdditionalPredicates = [NotInMicroMips] in { + def FADD_PS64 : ADDS_FT<"add.ps", FGR64Opnd, II_ADD_PS, 0>, + ADDS_FM<0x0, 22>, + ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; + def FMUL_PS64 : ADDS_FT<"mul.ps", FGR64Opnd, II_MUL_PS, 0>, + ADDS_FM<0x2, 22>, + ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; def PLL_PS64 : ADDS_FT<"pll.ps", FGR64Opnd, II_CVT, 0>, ADDS_FM<0x2C, 22>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; @@ -464,6 +470,9 @@ let DecoderNamespace = "MipsFP64" in { def PUU_PS64 : ADDS_FT<"puu.ps", FGR64Opnd, II_CVT, 0>, ADDS_FM<0x2F, 22>, ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; + def FSUB_PS64 : ADDS_FT<"sub.ps", FGR64Opnd, II_SUB_PS, 0>, + ADDS_FM<0x1, 22>, + ISA_MIPS32R2_NOT_32R6_64R6, FGR_64; def CVT_S_PU64 : ABSS_FT<"cvt.s.pu", FGR32Opnd, FGR64Opnd, II_CVT>, ABSS_FM<0x20, 22>, diff --git a/llvm/lib/Target/Mips/MipsSchedule.td b/llvm/lib/Target/Mips/MipsSchedule.td index 568c85a..3a5b3fe 100644 --- a/llvm/lib/Target/Mips/MipsSchedule.td +++ b/llvm/lib/Target/Mips/MipsSchedule.td @@ -26,6 +26,7 @@ def II_ADDIUPC : InstrItinClass; def II_ADD : InstrItinClass; def II_ADDU : InstrItinClass; def II_ADD_D : InstrItinClass; +def II_ADD_PS : InstrItinClass; def II_ADD_S : InstrItinClass; def II_ADDR_PS : InstrItinClass; def II_ALIGN : InstrItinClass; @@ -279,6 +280,7 @@ def II_MUL : InstrItinClass; def II_MUH : InstrItinClass; def II_MUHU : InstrItinClass; def II_MULU : InstrItinClass; +def II_MUL_PS : InstrItinClass; def II_MULR_PS : InstrItinClass; def II_MULT : InstrItinClass; def II_MULTU : InstrItinClass; @@ -341,6 +343,7 @@ def II_SRLV : InstrItinClass; def II_SUB : InstrItinClass; def II_SUBU : InstrItinClass; def II_SUB_D : InstrItinClass; +def II_SUB_PS : InstrItinClass; def II_SUB_S : InstrItinClass; def II_SUXC1 : InstrItinClass; def II_SW : InstrItinClass; diff --git a/llvm/lib/Target/Mips/MipsScheduleGeneric.td b/llvm/lib/Target/Mips/MipsScheduleGeneric.td index 3888ca4..f076f2f 100644 --- a/llvm/lib/Target/Mips/MipsScheduleGeneric.td +++ b/llvm/lib/Target/Mips/MipsScheduleGeneric.td @@ -829,10 +829,11 @@ def : InstRW<[GenericWriteFPUL], (instrs ADDR_PS64, CVT_L_S, CVT_S_D32, CVT_S_D64, CVT_S_L, CVT_S_W, CVT_W_D32, CVT_W_D64, CVT_W_S, CVT_PS_S64, CVT_S_PL64, CVT_S_PU64, - CVT_PS_PW64, CVT_PW_PS64, + CVT_PS_PW64, CVT_PW_PS64, FADD_PS64, FLOOR_L_D64, FLOOR_L_S, FLOOR_W_D32, FLOOR_W_D64, FLOOR_W_S, FMUL_D32, FMUL_D64, - MADD_D32, MADD_D64, MSUB_D32, MSUB_D64, MULR_PS64, + FMUL_PS64, FSUB_PS64, MADD_D32, MADD_D64, + MSUB_D32, MSUB_D64, MULR_PS64, NMADD_D32, NMADD_D64, NMSUB_D32, NMSUB_D64, PLL_PS64, PLU_PS64, PUL_PS64, PUU_PS64, ROUND_L_D64, ROUND_L_S, ROUND_W_D32, diff --git a/llvm/lib/Target/Mips/MipsScheduleP5600.td b/llvm/lib/Target/Mips/MipsScheduleP5600.td index 3d159d4..466b5c6 100644 --- a/llvm/lib/Target/Mips/MipsScheduleP5600.td +++ b/llvm/lib/Target/Mips/MipsScheduleP5600.td @@ -449,8 +449,8 @@ def : InstRW<[P5600WriteMSAShortLogic], (instregex "^(NLOC|NLZC)_[BHWD]$")>; // cvt.ps.[sw], cvt.s.(pl|pu), c..[ds], c..ps, mul.[ds], mul.ps, // pl[lu].ps, sub.[ds], sub.ps, trunc.w.[ds], trunc.w.ps def : InstRW<[P5600WriteFPUL], - (instrs FADD_D32, FADD_D64, FADD_S, FMUL_D32, FMUL_D64, FMUL_S, - FSUB_D32, FSUB_D64, FSUB_S)>; + (instrs FADD_D32, FADD_D64, FADD_PS64, FADD_S, FMUL_D32, FMUL_D64, + FMUL_PS64, FMUL_S, FSUB_D32, FSUB_D64, FSUB_PS64, FSUB_S)>; def : InstRW<[P5600WriteFPUL], (instregex "^TRUNC_(L|W)_(S|D32|D64)$")>; def : InstRW<[P5600WriteFPUL], (instregex "^CVT_(S|D32|D64|L|W)_(S|D32|D64|L|W)$")>; diff --git a/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s index cb590a7..6dc09d2 100644 --- a/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s +++ b/llvm/test/MC/Mips/mips1/invalid-mips5-wrong-error.s @@ -7,7 +7,6 @@ .set noat abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction @@ -32,11 +31,9 @@ movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.f.s $fcc4, $f2, $f7 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level c.le.s $fcc6, $f2, $f4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level diff --git a/llvm/test/MC/Mips/mips1/invalid-mips5.s b/llvm/test/MC/Mips/mips1/invalid-mips5.s index bfce1e5..82abc06 100644 --- a/llvm/test/MC/Mips/mips1/invalid-mips5.s +++ b/llvm/test/MC/Mips/mips1/invalid-mips5.s @@ -5,6 +5,7 @@ # RUN: FileCheck %s < %t1 .set noat + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -71,6 +72,7 @@ movz $a1,$s6,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$a3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -81,6 +83,7 @@ round.w.s $f27,$f28 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sqrt.d $f17,$f22 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sqrt.s $f0,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled teqi $s5,-17504 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled tgei $s1,5025 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s index 0bd2ef6..9ef69c8 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips5-wrong-error.s @@ -7,7 +7,6 @@ .set noat abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction @@ -32,8 +31,6 @@ movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/llvm/test/MC/Mips/mips2/invalid-mips5.s b/llvm/test/MC/Mips/mips2/invalid-mips5.s index ad5f2b5..c9fb27a 100644 --- a/llvm/test/MC/Mips/mips2/invalid-mips5.s +++ b/llvm/test/MC/Mips/mips2/invalid-mips5.s @@ -5,6 +5,7 @@ # RUN: FileCheck %s < %t1 .set noat + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level ceil.l.d $f1,$f3 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -67,6 +68,7 @@ movz $a1,$s6,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$a1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -76,6 +78,7 @@ trunc.l.d $f23,$f23 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled trunc.l.s $f28,$f31 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sdxc1 $f11,$a2($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level diff --git a/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s index 19711ba..e8108a0 100644 --- a/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s +++ b/llvm/test/MC/Mips/mips3/invalid-mips5-wrong-error.s @@ -7,7 +7,6 @@ .set noat abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction @@ -32,9 +31,6 @@ movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - diff --git a/llvm/test/MC/Mips/mips3/invalid-mips5.s b/llvm/test/MC/Mips/mips3/invalid-mips5.s index 31896e0..efa6840 100644 --- a/llvm/test/MC/Mips/mips3/invalid-mips5.s +++ b/llvm/test/MC/Mips/mips3/invalid-mips5.s @@ -5,6 +5,7 @@ # RUN: FileCheck %s < %t1 .set noat + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bc1f $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level bc1t $fcc1, 4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled @@ -30,11 +31,13 @@ movz $a1,$s6,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.d $f12,$f29,$a5 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled movz.s $f25,$f7,$v1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled sdxc1 $f11,$a6($t2) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled swxc1 $f19,$t0($k0) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled c.eq.s $fcc1, $f2, $f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: non-zero fcc register doesn't exist in current ISA level diff --git a/llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s index 1a2f020..632f7c1 100644 --- a/llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s +++ b/llvm/test/MC/Mips/mips4/invalid-mips5-wrong-error.s @@ -7,7 +7,6 @@ .set noat abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction alnv.ps $f12,$f18,$f30,$t0 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.eq.ps $fcc5,$f0,$f9 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction c.f.ps $fcc6,$f11,$f11 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction @@ -32,8 +31,6 @@ movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/llvm/test/MC/Mips/mips4/invalid-mips5.s b/llvm/test/MC/Mips/mips4/invalid-mips5.s index 2dc7681..2ec0f84 100644 --- a/llvm/test/MC/Mips/mips4/invalid-mips5.s +++ b/llvm/test/MC/Mips/mips4/invalid-mips5.s @@ -5,12 +5,15 @@ # RUN: FileCheck %s < %t1 .set noat + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled suxc1 $f12,$k1($t1) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.ps.s $f3,$f18,$f19 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.s.pl $f30,$f1 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.s.pu $f14,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled diff --git a/llvm/test/MC/Mips/mips64r2/valid-xfail.s b/llvm/test/MC/Mips/mips64r2/valid-xfail.s index 7c7ed52..5faf361 100644 --- a/llvm/test/MC/Mips/mips64r2/valid-xfail.s +++ b/llvm/test/MC/Mips/mips64r2/valid-xfail.s @@ -8,7 +8,6 @@ .set noat abs.ps $f22,$f8 - add.ps $f25,$f27,$f13 addqh.w $s7,$s7,$k1 addqh_r.w $8,$v1,$zero alnv.ps $f12,$f18,$f30,$12 @@ -59,7 +58,6 @@ msub.ps $f12,$f14,$f29,$f17 mtc0 $9,c0_datahi1 mtgc0 $s4,$21,7 - mul.ps $f14,$f0,$f16 neg.ps $f19,$f13 nmadd.ps $f27,$f4,$f9,$f25 nmsub.ps $f6,$f12,$f14,$f17 @@ -70,7 +68,6 @@ sbe $s7,33($s1) sce $sp,189($10) she $24,105($v0) - sub.ps $f5,$f14,$f26 swe $24,94($k0) swle $v1,-209($gp) swre $k0,-202($s2) diff --git a/llvm/test/MC/Mips/mips64r2/valid.s b/llvm/test/MC/Mips/mips64r2/valid.s index e1ce6ac..df33aee 100644 --- a/llvm/test/MC/Mips/mips64r2/valid.s +++ b/llvm/test/MC/Mips/mips64r2/valid.s @@ -9,6 +9,7 @@ a: add $9,$14,15176 # CHECK: addi $9, $14, 15176 # encoding: [0x21,0xc9,0x3b,0x48] add $24,-7193 # CHECK: addi $24, $24, -7193 # encoding: [0x23,0x18,0xe3,0xe7] add.d $f1,$f7,$f29 + add.ps $f25,$f27,$f13 # CHECK: add.ps $f25, $f27, $f13 # encoding: [0x46,0xcd,0xde,0x40] add.s $f8,$f21,$f24 addi $13,$9,26322 addi $8,$8,~1 # CHECK: addi $8, $8, -2 # encoding: [0x21,0x08,0xff,0xfe] @@ -267,6 +268,7 @@ a: mtlo $25 mul $s0,$s4,$at mul.d $f20,$f20,$f16 + mul.ps $f14, $f0, $f16 # CHECK: mul.ps $f14, $f0, $f16 # encoding: [0x46,0xd0,0x03,0x82] mul.s $f30,$f10,$f2 mult $sp,$s4 mult $sp,$v0 @@ -405,6 +407,7 @@ a: sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub.d $f18,$f3,$f17 + sub.ps $f5,$f14,$f26 # CHECK: sub.ps $f5, $f14, $f26 # encoding: [0x46,0xda,0x71,0x41] sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 suxc1 $f12,$k1($13) diff --git a/llvm/test/MC/Mips/mips64r3/valid-xfail.s b/llvm/test/MC/Mips/mips64r3/valid-xfail.s index 4c368e5..7931ee5 100644 --- a/llvm/test/MC/Mips/mips64r3/valid-xfail.s +++ b/llvm/test/MC/Mips/mips64r3/valid-xfail.s @@ -8,7 +8,6 @@ .set noat abs.ps $f22,$f8 - add.ps $f25,$f27,$f13 addqh.w $s7,$s7,$k1 addqh_r.w $8,$v1,$zero alnv.ob $v22,$v19,$v30,$v1 @@ -62,7 +61,6 @@ msub.ps $f12,$f14,$f29,$f17 mtc0 $9,c0_datahi1 mtgc0 $s4,$21,7 - mul.ps $f14,$f0,$f16 neg.ps $f19,$f13 nmadd.ps $f27,$f4,$f9,$f25 nmsub.ps $f6,$f12,$f14,$f17 @@ -73,7 +71,6 @@ sbe $s7,33($s1) sce $sp,189($10) she $24,105($v0) - sub.ps $f5,$f14,$f26 swe $24,94($k0) swle $v1,-209($gp) swre $k0,-202($s2) diff --git a/llvm/test/MC/Mips/mips64r3/valid.s b/llvm/test/MC/Mips/mips64r3/valid.s index fc4c58d..6e85870 100644 --- a/llvm/test/MC/Mips/mips64r3/valid.s +++ b/llvm/test/MC/Mips/mips64r3/valid.s @@ -261,6 +261,7 @@ a: mtlo $25 mul $s0,$s4,$at mul.d $f20,$f20,$f16 + mul.ps $f14,$f0,$f16 # CHECK: mul.ps $f14, $f0, $f16 # encoding: [0x46,0xd0,0x03,0x82] mul.s $f30,$f10,$f2 mult $sp,$s4 mult $sp,$v0 @@ -393,6 +394,7 @@ a: sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub.d $f18,$f3,$f17 + sub.ps $f5,$f14,$f26 # CHECK: sub.ps $f5, $f14, $f26 # encoding: [0x46,0xda,0x71,0x41] sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 suxc1 $f12,$k1($13) diff --git a/llvm/test/MC/Mips/mips64r5/valid-xfail.s b/llvm/test/MC/Mips/mips64r5/valid-xfail.s index d75f2b2..1e9b7b7 100644 --- a/llvm/test/MC/Mips/mips64r5/valid-xfail.s +++ b/llvm/test/MC/Mips/mips64r5/valid-xfail.s @@ -8,7 +8,6 @@ .set noat abs.ps $f22,$f8 - add.ps $f25,$f27,$f13 addqh.w $s7,$s7,$k1 addqh_r.w $8,$v1,$zero alnv.ob $v22,$v19,$v30,$v1 @@ -62,7 +61,6 @@ msub.ps $f12,$f14,$f29,$f17 mtc0 $9,c0_datahi1 mtgc0 $s4,$21,7 - mul.ps $f14,$f0,$f16 neg.ps $f19,$f13 nmadd.ps $f27,$f4,$f9,$f25 nmsub.ps $f6,$f12,$f14,$f17 @@ -73,7 +71,6 @@ sbe $s7,33($s1) sce $sp,189($10) she $24,105($v0) - sub.ps $f5,$f14,$f26 swe $24,94($k0) swle $v1,-209($gp) swre $k0,-202($s2) diff --git a/llvm/test/MC/Mips/mips64r5/valid.s b/llvm/test/MC/Mips/mips64r5/valid.s index 41515b1..bbd7fa9 100644 --- a/llvm/test/MC/Mips/mips64r5/valid.s +++ b/llvm/test/MC/Mips/mips64r5/valid.s @@ -263,6 +263,7 @@ a: mtlo $25 mul $s0,$s4,$at mul.d $f20,$f20,$f16 + mul.ps $f14,$f0,$f16 # CHECK: mul.ps $f14, $f0, $f16 # encoding: [0x46,0xd0,0x03,0x82] mul.s $f30,$f10,$f2 mult $sp,$s4 mult $sp,$v0 @@ -399,6 +400,7 @@ a: sub $22,$17,-3126 # CHECK: addi $22, $17, 3126 # encoding: [0x22,0x36,0x0c,0x36] sub $13,6512 # CHECK: addi $13, $13, -6512 # encoding: [0x21,0xad,0xe6,0x90] sub.d $f18,$f3,$f17 + sub.ps $f5,$f14,$f26 # CHECK: sub.ps $f5, $f14, $f26 # encoding: [0x46,0xda,0x71,0x41] sub.s $f23,$f22,$f22 subu $sp,$s6,$s6 suxc1 $f12,$k1($13) diff --git a/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s b/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s index 5125d07..974a756 100644 --- a/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s +++ b/llvm/test/MC/Mips/mips64r6/invalid-mips5-wrong-error.s @@ -6,7 +6,6 @@ .set noat abs.ps $f22,$f8 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction alnv.ps $f12,$f18,$f30,$12 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc1any2f $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction bc1any2t $fcc2,4 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction @@ -35,8 +34,6 @@ movt.ps $f20,$f25,$fcc2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction movz.ps $f18,$f17,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction msub.ps $f12,$f14,$f29,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction neg.ps $f19,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmadd.ps $f27,$f4,$f9,$f25 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction nmsub.ps $f6,$f12,$f14,$f17 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction - sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: unknown instruction diff --git a/llvm/test/MC/Mips/mips64r6/invalid-mips5.s b/llvm/test/MC/Mips/mips64r6/invalid-mips5.s index 3d8daf3..dca8e9e32 100644 --- a/llvm/test/MC/Mips/mips64r6/invalid-mips5.s +++ b/llvm/test/MC/Mips/mips64r6/invalid-mips5.s @@ -5,14 +5,17 @@ # RUN: FileCheck %s < %t1 .set noat + add.ps $f25,$f27,$f13 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgezal $0, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bgezal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled bltzal $6, 21100 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.ps.pw $f3,$f18 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled cvt.pw.ps $f1, $f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled luxc1 $f19,$s6($s5) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + mul.ps $f14,$f0,$f16 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pll.ps $f25,$f9,$f30 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled plu.ps $f1,$f26,$f29 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled pul.ps $f9,$f30,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled puu.ps $f24,$f9,$f2 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled + sub.ps $f5,$f14,$f26 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled suxc1 $f12,$k1($13) # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled -- 2.7.4