From fbc8134df62e51a0ce5f91b319214ccb8b74ae6a Mon Sep 17 00:00:00 2001 From: Doug Evans Date: Tue, 21 Jul 1998 20:59:23 +0000 Subject: [PATCH] * cgen-opc.in (@arch@_cgen_lookup_insn): Update call to CGEN_EXTRACT_FN. (@arch@_cgen_get_insn_operands): @arch@_cgen_get_operand renamed to @arch_cgen_get_int_operand. * cgen-asm.in (insert_insn_normal): New arg `pc', callers updated. Update call to @arch@_cgen_insert_operand. (@arch@_cgen_assemble_insn): Update call to CGEN_INSERT_FN. * cgen-dis.in (print_normal): Delete use of CGEN_PCREL_OFFSET. (extract_insn_normal): New arg `pc', callers updated. Update call to @arch@_cgen_extract_operand. (print_insn): Update call to CGEN_EXTRACT_FN. * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. --- opcodes/ChangeLog | 22 +++ opcodes/cgen-asm.in | 59 +++++--- opcodes/cgen-opc.in | 11 +- opcodes/m32r-asm.c | 35 +++-- opcodes/m32r-opc.c | 419 ++++++++++++++++++++++++++++++++++++++-------------- opcodes/m32r-opc.h | 6 +- 6 files changed, 399 insertions(+), 153 deletions(-) diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 69e2830..96a5fdc 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,4 +1,26 @@ +Tue Jul 21 13:41:07 1998 Doug Evans + +start-sanitize-cygnus + * cgen-opc.in (@arch@_cgen_lookup_insn): Update call to + CGEN_EXTRACT_FN. + (@arch@_cgen_get_insn_operands): @arch@_cgen_get_operand renamed to + @arch_cgen_get_int_operand. + * cgen-asm.in (insert_insn_normal): New arg `pc', callers updated. + Update call to @arch@_cgen_insert_operand. + (@arch@_cgen_assemble_insn): Update call to CGEN_INSERT_FN. + * cgen-dis.in (print_normal): Delete use of CGEN_PCREL_OFFSET. + (extract_insn_normal): New arg `pc', callers updated. + Update call to @arch@_cgen_extract_operand. + (print_insn): Update call to CGEN_EXTRACT_FN. +end-sanitize-cygnus + * m32r-opc.h,m32r-opc.c,m32r-asm.c,m32r-dis.c: Regenerate. + start-sanitize-am33 +Mon Jul 20 12:10:37 1998 Jeffrey A Law (law@cygnus.com) + + * m10300-opc.c: Fix load to sp and store from sp for the am33. + Add more multimedia instructions. + Thu Jul 16 18:04:46 1998 Jeffrey A Law (law@cygnus.com) * m10300-opc.c (mn10300_opcodes): Fix opcode for 4 operand "mul" and diff --git a/opcodes/cgen-asm.in b/opcodes/cgen-asm.in index b714009..681262d 100644 --- a/opcodes/cgen-asm.in +++ b/opcodes/cgen-asm.in @@ -1,7 +1,7 @@ /* Assembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -This file is used to generate @arch@-asm.c. +THIS FILE IS USED TO GENERATE @prefix@-asm.c. Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. @@ -18,8 +18,8 @@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "sysdep.h" #include @@ -27,7 +27,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "ansidecl.h" #include "bfd.h" #include "symcat.h" -#include "@arch@-opc.h" +#include "@prefix@-opc.h" #include "opintl.h" /* ??? The layout of this stuff is still work in progress. @@ -42,7 +42,7 @@ static const char * insert_normal static const char * parse_insn_normal PARAMS ((const CGEN_INSN *, const char **, CGEN_FIELDS *)); static const char * insert_insn_normal - PARAMS ((const CGEN_INSN *, CGEN_FIELDS *, cgen_insn_t *)); + PARAMS ((const CGEN_INSN *, CGEN_FIELDS *, cgen_insn_t *, bfd_vma)); /* -- assembler routines inserted here */ @@ -70,13 +70,21 @@ insert_normal (value, attrs, start, length, total_length, buffer) { bfd_vma x; static char buf[100]; + /* Written this way to avoid undefined behaviour. + Yes, `long' will be bfd_vma but not yet. */ + long mask = (((1L << (length - 1)) - 1) << 1) | 1; + + /* If LENGTH is zero, this operand doesn't contribute to the value. */ + if (length == 0) + return NULL; /* Ensure VALUE will fit. */ - if ((attrs & (1 << CGEN_OPERAND_UNSIGNED)) != 0) + if ((attrs & CGEN_ATTR_MASK (CGEN_OPERAND_UNSIGNED)) != 0) { - unsigned long max = (1 << length) - 1; + unsigned long max = mask; if ((unsigned long) value > max) { + /* xgettext:c-format */ sprintf (buf, _("operand out of range (%lu not between 0 and %lu)"), value, max); return buf; @@ -84,17 +92,20 @@ insert_normal (value, attrs, start, length, total_length, buffer) } else { - long min = - (1 << (length - 1)); - long max = (1 << (length - 1)) - 1; + long min = - (1L << (length - 1)); + long max = (1L << (length - 1)) - 1; if (value < min || value > max) - return sprintf - (buf, _("operand out of range (%ld not between %ld and %ld)"), - value, min, max); + { + sprintf + /* xgettext:c-format */ + (buf, _("operand out of range (%ld not between %ld and %ld)"), + value, min, max); + return buf; + } } #if 0 /*def CGEN_INT_INSN*/ - *buffer |= ((value & ((1 << length) - 1)) - << (total_length - (start + length))); + *buffer |= (value & mask) << (total_length - (start + length)); #else switch (total_length) { @@ -117,8 +128,7 @@ insert_normal (value, attrs, start, length, total_length, buffer) abort (); } - x |= ((value & ((1 << length) - 1)) - << (total_length - (start + length))); + x |= (value & mask) << (total_length - (start + length)); switch (total_length) { @@ -171,6 +181,7 @@ parse_insn_normal (insn, strp, fields) const char * p; const unsigned char * syn; #ifdef CGEN_MNEMONIC_OPERANDS + /* FIXME: wip */ int past_opcode_p; #endif @@ -202,7 +213,6 @@ parse_insn_normal (insn, strp, fields) while (* syn != 0) { /* Non operand chars must match exactly. */ - /* FIXME: Need to better handle whitespace. */ if (CGEN_SYNTAX_CHAR_P (* syn)) { if (*str == CGEN_SYNTAX_CHAR (* syn)) @@ -260,10 +270,11 @@ parse_insn_normal (insn, strp, fields) /* FIXME: change buffer to char *? */ static const char * -insert_insn_normal (insn, fields, buffer) +insert_insn_normal (insn, fields, buffer, pc) const CGEN_INSN * insn; CGEN_FIELDS * fields; cgen_insn_t * buffer; + bfd_vma pc; { const CGEN_SYNTAX * syntax = CGEN_INSN_SYNTAX (insn); bfd_vma value; @@ -312,7 +323,7 @@ insert_insn_normal (insn, fields, buffer) continue; errmsg = @arch@_cgen_insert_operand (CGEN_SYNTAX_FIELD (*syn), fields, - (char *) buffer); + (char *) buffer, pc); if (errmsg) return errmsg; } @@ -364,13 +375,11 @@ const CGEN_INSN * continue; #endif -#if 1 /* FIXME: wip */ /* If the RELAX attribute is set, this is an insn that shouldn't be chosen immediately. Instead, it is used during assembler/linker relaxation if possible. */ if (CGEN_INSN_ATTR (insn, CGEN_INSN_RELAX) != 0) continue; -#endif str = start; @@ -381,7 +390,8 @@ const CGEN_INSN * if (! CGEN_PARSE_FN (insn) (insn, & str, fields)) { - if (CGEN_INSERT_FN (insn) (insn, fields, buf) != NULL) + /* ??? 0 is passed for `pc' */ + if (CGEN_INSERT_FN (insn) (insn, fields, buf, (bfd_vma) 0) != NULL) continue; /* It is up to the caller to actually output the insn and any queued relocs. */ @@ -395,10 +405,11 @@ const CGEN_INSN * Need to track why it failed and pick the right one. */ { static char errbuf[100]; - /* xgettext:c-format */ if (strlen (start) > 50) + /* xgettext:c-format */ sprintf (errbuf, _("bad instruction `%.50s...'"), start); - else + else + /* xgettext:c-format */ sprintf (errbuf, _("bad instruction `%.50s'"), start); *errmsg = errbuf; diff --git a/opcodes/cgen-opc.in b/opcodes/cgen-opc.in index 8a88898..57a03dd 100644 --- a/opcodes/cgen-opc.in +++ b/opcodes/cgen-opc.in @@ -96,8 +96,10 @@ const CGEN_INSN * extract handler. */ if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn)) { + /* ??? 0 is passed for `pc' */ int elength = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, - insn_value, fields); + insn_value, fields, + (bfd_vma) 0); if (elength > 0) { /* sanity check */ @@ -121,7 +123,9 @@ const CGEN_INSN * if (length != CGEN_INSN_BITSIZE (insn)) abort (); - length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields); + /* ??? 0 is passed for `pc' */ + length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields, + (bfd_vma) 0); /* Sanity check: must succeed. Could relax this later if it ever proves useful. */ if (length == 0) @@ -154,7 +158,8 @@ void if (op == NULL) indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst); else - indices[i] = @arch@_cgen_get_operand (CGEN_OPERAND_INDEX (op), fields); + indices[i] = @arch@_cgen_get_int_operand (CGEN_OPERAND_INDEX (op), + fields); } } diff --git a/opcodes/m32r-asm.c b/opcodes/m32r-asm.c index 3318233..8f73dc5 100644 --- a/opcodes/m32r-asm.c +++ b/opcodes/m32r-asm.c @@ -1,7 +1,7 @@ /* Assembler interface for targets using CGEN. -*- C -*- CGEN: Cpu tools GENerator -This file is used to generate m32r-asm.c. +THIS FILE IS USED TO GENERATE m32r-asm.c. Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc. @@ -18,8 +18,8 @@ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License -along with this program; if not, write to the Free Software -Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ +along with this program; if not, write to the Free Software Foundation, Inc., +59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "sysdep.h" #include @@ -42,7 +42,7 @@ static const char * insert_normal static const char * parse_insn_normal PARAMS ((const CGEN_INSN *, const char **, CGEN_FIELDS *)); static const char * insert_insn_normal - PARAMS ((const CGEN_INSN *, CGEN_FIELDS *, cgen_insn_t *)); + PARAMS ((const CGEN_INSN *, CGEN_FIELDS *, cgen_insn_t *, bfd_vma)); /* -- assembler routines inserted here */ /* -- asm.c */ @@ -309,10 +309,11 @@ m32r_cgen_parse_operand (opindex, strp, fields) */ const char * -m32r_cgen_insert_operand (opindex, fields, buffer) +m32r_cgen_insert_operand (opindex, fields, buffer, pc) int opindex; CGEN_FIELDS * fields; char * buffer; + bfd_vma pc; { const char * errmsg; @@ -354,7 +355,8 @@ m32r_cgen_insert_operand (opindex, fields, buffer) /* start-sanitize-m32rx */ case M32R_OPERAND_IMM1 : { - long value = ((fields->f_imm1) - (1)); + long value = fields->f_imm1; + value = ((value) - (1)); errmsg = insert_normal (value, 0|(1<f_disp8) >> (2)); + long value = fields->f_disp8; + value = ((((value) - (((pc) & (-4))))) >> (2)); errmsg = insert_normal (value, 0|(1<f_disp16) >> (2)); + long value = fields->f_disp16; + value = ((((value) - (pc))) >> (2)); errmsg = insert_normal (value, 0|(1<f_disp24) >> (2)); + long value = fields->f_disp24; + value = ((((value) - (pc))) >> (2)); errmsg = insert_normal (value, 0|(1< @@ -28,6 +28,7 @@ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ #include "bfd.h" #include "symcat.h" #include "m32r-opc.h" +#include "opintl.h" /* Look up instruction INSN_VALUE and extract its fields. INSN, if non-null, is the insn table entry. @@ -95,8 +96,10 @@ m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p) extract handler. */ if ((insn_value & CGEN_INSN_MASK (insn)) == CGEN_INSN_VALUE (insn)) { + /* ??? 0 is passed for `pc' */ int elength = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, - insn_value, fields); + insn_value, fields, + (bfd_vma) 0); if (elength > 0) { /* sanity check */ @@ -120,7 +123,9 @@ m32r_cgen_lookup_insn (insn, insn_value, length, fields, alias_p) if (length != CGEN_INSN_BITSIZE (insn)) abort (); - length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields); + /* ??? 0 is passed for `pc' */ + length = (*CGEN_EXTRACT_FN (insn)) (insn, NULL, insn_value, fields, + (bfd_vma) 0); /* Sanity check: must succeed. Could relax this later if it ever proves useful. */ if (length == 0) @@ -153,7 +158,7 @@ m32r_cgen_get_insn_operands (insn, fields, indices) if (op == NULL) indices[i] = CGEN_OPERAND_INSTANCE_INDEX (opinst); else - indices[i] = m32r_cgen_get_operand (CGEN_OPERAND_INDEX (op), fields); + indices[i] = m32r_cgen_get_int_operand (CGEN_OPERAND_INDEX (op), fields); } } @@ -213,7 +218,6 @@ const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[] = { "FAKE", NULL }, { "HASH-PREFIX", NULL }, { "NEGATIVE", NULL }, - { "PC", NULL }, { "PCREL-ADDR", NULL }, { "RELAX", NULL }, { "RELOC", NULL }, @@ -235,6 +239,7 @@ const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[] = { "PARALLEL", NULL }, { "RELAX", NULL }, { "RELAXABLE", NULL }, + { "SPECIAL", NULL }, { "UNCOND-CTI", NULL }, { 0, 0 } }; @@ -334,9 +339,6 @@ static const CGEN_HW_ENTRY m32r_cgen_hw_entries[] = /* start-sanitize-m32rx */ { HW_H_ACCUMS, & HW_ENT (HW_H_ACCUMS + 1), "h-accums", CGEN_ASM_KEYWORD, (PTR) & m32r_cgen_opval_h_accums }, /* end-sanitize-m32rx */ -/* start-sanitize-m32rx */ - { HW_H_ABORT, & HW_ENT (HW_H_ABORT + 1), "h-abort", CGEN_ASM_KEYWORD, (PTR) 0 }, -/* end-sanitize-m32rx */ { HW_H_COND, & HW_ENT (HW_H_COND + 1), "h-cond", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_SM, & HW_ENT (HW_H_SM + 1), "h-sm", CGEN_ASM_KEYWORD, (PTR) 0 }, { HW_H_BSM, & HW_ENT (HW_H_BSM + 1), "h-bsm", CGEN_ASM_KEYWORD, (PTR) 0 }, @@ -357,7 +359,7 @@ const CGEN_OPERAND m32r_cgen_operand_table[MAX_OPERANDS] = { /* pc: program counter */ { "pc", & HW_ENT (HW_H_PC), 0, 0, - { 0, 0|(1<f_r2 = * valuep; + value = fields->f_r2; break; case M32R_OPERAND_DR : - fields->f_r1 = * valuep; + value = fields->f_r1; break; case M32R_OPERAND_SRC1 : - fields->f_r1 = * valuep; + value = fields->f_r1; break; case M32R_OPERAND_SRC2 : - fields->f_r2 = * valuep; + value = fields->f_r2; break; case M32R_OPERAND_SCR : - fields->f_r2 = * valuep; + value = fields->f_r2; break; case M32R_OPERAND_DCR : - fields->f_r1 = * valuep; + value = fields->f_r1; break; case M32R_OPERAND_SIMM8 : - fields->f_simm8 = * valuep; + value = fields->f_simm8; break; case M32R_OPERAND_SIMM16 : - fields->f_simm16 = * valuep; + value = fields->f_simm16; break; case M32R_OPERAND_UIMM4 : - fields->f_uimm4 = * valuep; + value = fields->f_uimm4; break; case M32R_OPERAND_UIMM5 : - fields->f_uimm5 = * valuep; + value = fields->f_uimm5; break; case M32R_OPERAND_UIMM16 : - fields->f_uimm16 = * valuep; + value = fields->f_uimm16; break; /* start-sanitize-m32rx */ case M32R_OPERAND_IMM1 : - fields->f_imm1 = * valuep; + value = fields->f_imm1; break; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ case M32R_OPERAND_ACCD : - fields->f_accd = * valuep; + value = fields->f_accd; break; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ case M32R_OPERAND_ACCS : - fields->f_accs = * valuep; + value = fields->f_accs; break; /* end-sanitize-m32rx */ /* start-sanitize-m32rx */ case M32R_OPERAND_ACC : - fields->f_acc = * valuep; + value = fields->f_acc; break; /* end-sanitize-m32rx */ case M32R_OPERAND_HASH : - fields->f_nil = * valuep; + value = fields->f_nil; break; case M32R_OPERAND_HI16 : - fields->f_hi16 = * valuep; + value = fields->f_hi16; break; case M32R_OPERAND_SLO16 : - fields->f_simm16 = * valuep; + value = fields->f_simm16; break; case M32R_OPERAND_ULO16 : - fields->f_uimm16 = * valuep; + value = fields->f_uimm16; break; case M32R_OPERAND_UIMM24 : - fields->f_uimm24 = * valuep; + value = fields->f_uimm24; break; case M32R_OPERAND_DISP8 : - fields->f_disp8 = * valuep; + value = fields->f_disp8; break; case M32R_OPERAND_DISP16 : - fields->f_disp16 = * valuep; + value = fields->f_disp16; break; case M32R_OPERAND_DISP24 : - fields->f_disp24 = * valuep; + value = fields->f_disp24; break; default : - fprintf (stderr, "Unrecognized field %d while setting operand.\n", + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting int operand.\n"), opindex); abort (); } -} -/* Main entry point for getting values from cgen_fields. */ + return value; +} -long -m32r_cgen_get_operand (opindex, fields) +bfd_vma +m32r_cgen_get_vma_operand (opindex, fields) int opindex; const CGEN_FIELDS * fields; { - long value; + bfd_vma value; switch (opindex) { @@ -2831,7 +2838,8 @@ m32r_cgen_get_operand (opindex, fields) break; default : - fprintf (stderr, "Unrecognized field %d while getting operand.\n", + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while getting vma operand.\n"), opindex); abort (); } @@ -2839,3 +2847,196 @@ m32r_cgen_get_operand (opindex, fields) return value; } +/* Stuffing values in cgen_fields is handled by a collection of functions. + They are distinguished by the type of the VALUE argument they accept. + TODO: floating point, inlining support, remove cases where argument type + not appropriate. */ + +void +m32r_cgen_set_int_operand (opindex, fields, value) + int opindex; + CGEN_FIELDS * fields; + int value; +{ + switch (opindex) + { + case M32R_OPERAND_SR : + fields->f_r2 = value; + break; + case M32R_OPERAND_DR : + fields->f_r1 = value; + break; + case M32R_OPERAND_SRC1 : + fields->f_r1 = value; + break; + case M32R_OPERAND_SRC2 : + fields->f_r2 = value; + break; + case M32R_OPERAND_SCR : + fields->f_r2 = value; + break; + case M32R_OPERAND_DCR : + fields->f_r1 = value; + break; + case M32R_OPERAND_SIMM8 : + fields->f_simm8 = value; + break; + case M32R_OPERAND_SIMM16 : + fields->f_simm16 = value; + break; + case M32R_OPERAND_UIMM4 : + fields->f_uimm4 = value; + break; + case M32R_OPERAND_UIMM5 : + fields->f_uimm5 = value; + break; + case M32R_OPERAND_UIMM16 : + fields->f_uimm16 = value; + break; +/* start-sanitize-m32rx */ + case M32R_OPERAND_IMM1 : + fields->f_imm1 = value; + break; +/* end-sanitize-m32rx */ +/* start-sanitize-m32rx */ + case M32R_OPERAND_ACCD : + fields->f_accd = value; + break; +/* end-sanitize-m32rx */ +/* start-sanitize-m32rx */ + case M32R_OPERAND_ACCS : + fields->f_accs = value; + break; +/* end-sanitize-m32rx */ +/* start-sanitize-m32rx */ + case M32R_OPERAND_ACC : + fields->f_acc = value; + break; +/* end-sanitize-m32rx */ + case M32R_OPERAND_HASH : + fields->f_nil = value; + break; + case M32R_OPERAND_HI16 : + fields->f_hi16 = value; + break; + case M32R_OPERAND_SLO16 : + fields->f_simm16 = value; + break; + case M32R_OPERAND_ULO16 : + fields->f_uimm16 = value; + break; + case M32R_OPERAND_UIMM24 : + fields->f_uimm24 = value; + break; + case M32R_OPERAND_DISP8 : + fields->f_disp8 = value; + break; + case M32R_OPERAND_DISP16 : + fields->f_disp16 = value; + break; + case M32R_OPERAND_DISP24 : + fields->f_disp24 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting int operand.\n"), + opindex); + abort (); + } +} + +void +m32r_cgen_set_vma_operand (opindex, fields, value) + int opindex; + CGEN_FIELDS * fields; + bfd_vma value; +{ + switch (opindex) + { + case M32R_OPERAND_SR : + fields->f_r2 = value; + break; + case M32R_OPERAND_DR : + fields->f_r1 = value; + break; + case M32R_OPERAND_SRC1 : + fields->f_r1 = value; + break; + case M32R_OPERAND_SRC2 : + fields->f_r2 = value; + break; + case M32R_OPERAND_SCR : + fields->f_r2 = value; + break; + case M32R_OPERAND_DCR : + fields->f_r1 = value; + break; + case M32R_OPERAND_SIMM8 : + fields->f_simm8 = value; + break; + case M32R_OPERAND_SIMM16 : + fields->f_simm16 = value; + break; + case M32R_OPERAND_UIMM4 : + fields->f_uimm4 = value; + break; + case M32R_OPERAND_UIMM5 : + fields->f_uimm5 = value; + break; + case M32R_OPERAND_UIMM16 : + fields->f_uimm16 = value; + break; +/* start-sanitize-m32rx */ + case M32R_OPERAND_IMM1 : + fields->f_imm1 = value; + break; +/* end-sanitize-m32rx */ +/* start-sanitize-m32rx */ + case M32R_OPERAND_ACCD : + fields->f_accd = value; + break; +/* end-sanitize-m32rx */ +/* start-sanitize-m32rx */ + case M32R_OPERAND_ACCS : + fields->f_accs = value; + break; +/* end-sanitize-m32rx */ +/* start-sanitize-m32rx */ + case M32R_OPERAND_ACC : + fields->f_acc = value; + break; +/* end-sanitize-m32rx */ + case M32R_OPERAND_HASH : + fields->f_nil = value; + break; + case M32R_OPERAND_HI16 : + fields->f_hi16 = value; + break; + case M32R_OPERAND_SLO16 : + fields->f_simm16 = value; + break; + case M32R_OPERAND_ULO16 : + fields->f_uimm16 = value; + break; + case M32R_OPERAND_UIMM24 : + fields->f_uimm24 = value; + break; + case M32R_OPERAND_DISP8 : + fields->f_disp8 = value; + break; + case M32R_OPERAND_DISP16 : + fields->f_disp16 = value; + break; + case M32R_OPERAND_DISP24 : + fields->f_disp24 = value; + break; + + default : + /* xgettext:c-format */ + fprintf (stderr, _("Unrecognized field %d while setting vma operand.\n"), + opindex); + abort (); + } +} + diff --git a/opcodes/m32r-opc.h b/opcodes/m32r-opc.h index b9a7f2c..bdd7fe7 100644 --- a/opcodes/m32r-opc.h +++ b/opcodes/m32r-opc.h @@ -39,9 +39,11 @@ with this program; if not, write to the Free Software Foundation, Inc., #define CGEN_WORD_BITSIZE 32 #define CGEN_DEFAULT_INSN_BITSIZE 32 #define CGEN_BASE_INSN_BITSIZE 32 +#define CGEN_MIN_INSN_BITSIZE 16 #define CGEN_MAX_INSN_BITSIZE 32 #define CGEN_DEFAULT_INSN_SIZE (CGEN_DEFAULT_INSN_BITSIZE / 8) #define CGEN_BASE_INSN_SIZE (CGEN_BASE_INSN_BITSIZE / 8) +#define CGEN_MIN_INSN_SIZE (CGEN_MIN_INSN_BITSIZE / 8) #define CGEN_MAX_INSN_SIZE (CGEN_MAX_INSN_BITSIZE / 8) #define CGEN_INT_INSN @@ -152,8 +154,8 @@ typedef enum pipe_attr { /* Enum declaration for cgen_operand attrs. */ typedef enum cgen_operand_attr { CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_FAKE, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_NEGATIVE - , CGEN_OPERAND_PC, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC - , CGEN_OPERAND_SIGN_OPT, CGEN_OPERAND_UNSIGNED + , CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_RELAX, CGEN_OPERAND_RELOC, CGEN_OPERAND_SIGN_OPT + , CGEN_OPERAND_UNSIGNED } CGEN_OPERAND_ATTR; /* Number of non-boolean elements in cgen_operand. */ -- 2.7.4