From fbb119412f143530a23d22b6b0f90d4cf2303fbf Mon Sep 17 00:00:00 2001 From: David Sherwood Date: Thu, 15 Sep 2022 12:18:14 +0000 Subject: [PATCH] [AArch64] Add Neoverse V2 CPU support Adds support for the Neoverse V2 CPU to the AArch64 backend. Differential Revision: https://reviews.llvm.org/D134352 --- clang/docs/ReleaseNotes.rst | 2 ++ clang/test/Driver/aarch64-mcpu.c | 2 ++ clang/test/Misc/target-invalid-cpu-note.c | 4 ++-- llvm/include/llvm/Support/AArch64TargetParser.def | 6 ++++++ llvm/lib/Support/Host.cpp | 1 + llvm/lib/Target/AArch64/AArch64.td | 12 ++++++++++++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 1 + llvm/lib/Target/AArch64/AArch64Subtarget.h | 1 + llvm/test/CodeGen/AArch64/cpus.ll | 1 + llvm/unittests/Support/TargetParserTest.cpp | 13 ++++++++++++- 10 files changed, 40 insertions(+), 3 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 5fe86f8..0dd3b54 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -404,6 +404,8 @@ Arm and AArch64 Support in Clang - ``-march`` values for targeting armv2, armv2A, armv3 and armv3M have been removed. Their presence gave the impression that Clang can correctly generate code for them, which it cannot. +- Add driver and tuning support for Neoverse V2 via the flag ``-mcpu=neoverse-v2``. + Native detection is also supported via ``-mcpu=native``. Floating Point Support in Clang ------------------------------- diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c index d3c30b3..8b2701f 100644 --- a/clang/test/Driver/aarch64-mcpu.c +++ b/clang/test/Driver/aarch64-mcpu.c @@ -49,6 +49,8 @@ // NEOVERSE-E1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-e1" // RUN: %clang -target aarch64 -mcpu=neoverse-v1 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-V1 %s // NEOVERSE-V1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v1" +// RUN: %clang -target aarch64 -mcpu=neoverse-v2 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-V2 %s +// NEOVERSE-V2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v2" // RUN: %clang -target aarch64 -mcpu=neoverse-n1 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-N1 %s // NEOVERSE-N1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-n1" // RUN: %clang -target aarch64 -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-N2 %s diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 1f5899f..0fa4d31 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -5,11 +5,11 @@ // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64 // AARCH64: error: unknown target CPU 'not-a-cpu' -// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1{{$}} +// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1{{$}} // RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64 // TUNE_AARCH64: error: unknown target CPU 'not-a-cpu' -// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1{{$}} +// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78c, cortex-a710, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-m1, apple-m2, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1{{$}} // RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86 // X86: error: unknown target CPU 'not-a-cpu' diff --git a/llvm/include/llvm/Support/AArch64TargetParser.def b/llvm/include/llvm/Support/AArch64TargetParser.def index b281cb2..c11a1a9 100644 --- a/llvm/include/llvm/Support/AArch64TargetParser.def +++ b/llvm/include/llvm/Support/AArch64TargetParser.def @@ -235,6 +235,12 @@ AARCH64_CPU_NAME("neoverse-v1", ARMV8_4A, FK_CRYPTO_NEON_FP_ARMV8, false, AArch64::AEK_FP16 | AArch64::AEK_BF16 | AArch64::AEK_DOTPROD | AArch64::AEK_PROFILE | AArch64::AEK_RAND | AArch64::AEK_FP16FML | AArch64::AEK_I8MM)) +AARCH64_CPU_NAME("neoverse-v2", ARMV9A, FK_NEON_FP_ARMV8, false, + (AArch64::AEK_SVE | AArch64::AEK_SVE2 | AArch64::AEK_SSBS | + AArch64::AEK_FP16 | AArch64::AEK_BF16 | AArch64::AEK_RAND | + AArch64::AEK_DOTPROD | AArch64::AEK_PROFILE | + AArch64::AEK_SVE2BITPERM | AArch64::AEK_FP16FML | + AArch64::AEK_I8MM | AArch64::AEK_MTE)) AARCH64_CPU_NAME("cyclone", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, (AArch64::AEK_NONE)) AARCH64_CPU_NAME("apple-a7", ARMV8A, FK_CRYPTO_NEON_FP_ARMV8, false, diff --git a/llvm/lib/Support/Host.cpp b/llvm/lib/Support/Host.cpp index f163c82..5949930 100644 --- a/llvm/lib/Support/Host.cpp +++ b/llvm/lib/Support/Host.cpp @@ -218,6 +218,7 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { .Case("0xd0c", "neoverse-n1") .Case("0xd49", "neoverse-n2") .Case("0xd40", "neoverse-v1") + .Case("0xd4f", "neoverse-v2") .Default("generic"); } diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index 68d3366..51a8f95 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -984,6 +984,12 @@ def TuneNeoverseV1 : SubtargetFeature<"neoversev1", "ARMProcFamily", "NeoverseV1 FeatureLSLFast, FeaturePostRAScheduler]>; +def TuneNeoverseV2 : SubtargetFeature<"neoversev2", "ARMProcFamily", "NeoverseV2", + "Neoverse V2 ARM processors", [ + FeatureFuseAES, + FeatureLSLFast, + FeaturePostRAScheduler]>; + def TuneSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", "Qualcomm Saphira processors", [ FeatureCustomCheapAsMoveHandling, @@ -1155,6 +1161,10 @@ def ProcessorFeatures { FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, FeaturePerfMon, FeatureRandGen, FeatureSPE, FeatureSSBS, FeatureSVE]; + list NeoverseV2 = [HasV9_0aOps, FeatureBF16, FeatureSPE, + FeaturePerfMon, FeatureETE, FeatureMatMulInt8, + FeatureNEON, FeatureSVE2BitPerm, FeatureFP16FML, + FeatureMTE, FeatureRandGen]; list Saphira = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeatureSPE, FeaturePerfMon]; list ThunderX = [HasV8_0aOps, FeatureCRC, FeatureCrypto, @@ -1233,6 +1243,8 @@ def : ProcessorModel<"neoverse-512tvb", NeoverseN2Model, ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>; def : ProcessorModel<"neoverse-v1", NeoverseN2Model, ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>; +def : ProcessorModel<"neoverse-v2", NeoverseN2Model, + ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>; def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3, [TuneExynosM3]>; def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4, diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index 46e2f19..a9c7635 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -201,6 +201,7 @@ void AArch64Subtarget::initializeProperties() { MaxBytesForLoopAlignment = 16; break; case NeoverseN2: + case NeoverseV2: PrefFunctionLogAlignment = 4; PrefLoopLogAlignment = 5; MaxBytesForLoopAlignment = 16; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index 83fd73f..96ef935 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -76,6 +76,7 @@ public: NeoverseN2, Neoverse512TVB, NeoverseV1, + NeoverseV2, Saphira, ThunderX2T99, ThunderX, diff --git a/llvm/test/CodeGen/AArch64/cpus.ll b/llvm/test/CodeGen/AArch64/cpus.ll index 9167f12..e3975e0 100644 --- a/llvm/test/CodeGen/AArch64/cpus.ll +++ b/llvm/test/CodeGen/AArch64/cpus.ll @@ -23,6 +23,7 @@ ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-n2 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-512tvb 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-v1 2>&1 | FileCheck %s +; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=neoverse-v2 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m3 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m4 2>&1 | FileCheck %s ; RUN: llc < %s -mtriple=arm64-unknown-unknown -mcpu=exynos-m5 2>&1 | FileCheck %s diff --git a/llvm/unittests/Support/TargetParserTest.cpp b/llvm/unittests/Support/TargetParserTest.cpp index 46533b9..f25b72e 100644 --- a/llvm/unittests/Support/TargetParserTest.cpp +++ b/llvm/unittests/Support/TargetParserTest.cpp @@ -1026,6 +1026,17 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_PROFILE | AArch64::AEK_RAND | AArch64::AEK_FP16FML | AArch64::AEK_I8MM, "8.4-A"), + ARMCPUTestParams( + "neoverse-v2", "armv9-a", "neon-fp-armv8", + AArch64::AEK_RAS | AArch64::AEK_SVE | AArch64::AEK_SSBS | + AArch64::AEK_RCPC | AArch64::AEK_CRC | AArch64::AEK_FP | + AArch64::AEK_SIMD | AArch64::AEK_MTE | AArch64::AEK_LSE | + AArch64::AEK_RDM | AArch64::AEK_RCPC | AArch64::AEK_DOTPROD | + AArch64::AEK_FP16 | AArch64::AEK_BF16 | AArch64::AEK_SVE2 | + AArch64::AEK_PROFILE | AArch64::AEK_FP16FML | + AArch64::AEK_I8MM | AArch64::AEK_SVE2BITPERM | + AArch64::AEK_RAND, + "9-A"), ARMCPUTestParams("cortex-r82", "armv8-r", "crypto-neon-fp-armv8", AArch64::AEK_CRC | AArch64::AEK_RDM | AArch64::AEK_SSBS | AArch64::AEK_DOTPROD | @@ -1284,7 +1295,7 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_LSE | AArch64::AEK_RDM, "8.2-A"))); -static constexpr unsigned NumAArch64CPUArchs = 57; +static constexpr unsigned NumAArch64CPUArchs = 58; TEST(TargetParserTest, testAArch64CPUArchList) { SmallVector List; -- 2.7.4