From fbab8df43fe20fffcdfbdffea60dc40254ec9766 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Tue, 18 Apr 2023 16:07:43 +0200 Subject: [PATCH] radv: emit PIXEL_PIPE_STAT_CONTROL in the gfx preamble for GFX11 This is more optimal than emitting for every BeginOcclusionQuery(). Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_query.c | 12 ------------ src/amd/vulkan/si_cmd_buffer.c | 9 +++++++++ 2 files changed, 9 insertions(+), 12 deletions(-) diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c index fd0e8f3..77851e2 100644 --- a/src/amd/vulkan/radv_query.c +++ b/src/amd/vulkan/radv_query.c @@ -1807,18 +1807,6 @@ emit_begin_query(struct radv_cmd_buffer *cmd_buffer, struct radv_query_pool *poo } } - if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11) { - uint64_t rb_mask = - BITFIELD64_MASK(cmd_buffer->device->physical_device->rad_info.max_render_backends); - - radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); - radeon_emit(cs, EVENT_TYPE(V_028A90_PIXEL_PIPE_STAT_CONTROL) | EVENT_INDEX(1)); - radeon_emit(cs, PIXEL_PIPE_STATE_CNTL_COUNTER_ID(0) | - PIXEL_PIPE_STATE_CNTL_STRIDE(2) | - PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_LO(rb_mask)); - radeon_emit(cs, PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_HI(rb_mask)); - } - if (cmd_buffer->device->physical_device->rad_info.gfx_level >= GFX11 && cmd_buffer->device->physical_device->rad_info.pfp_fw_version >= EVENT_WRITE_ZPASS_PFP_VERSION) { radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_ZPASS, 1, 0)); diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index dede9a8..93041c6 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -625,6 +625,15 @@ si_emit_graphics(struct radv_device *device, struct radeon_cmdbuf *cs) radeon_set_context_reg(cs, R_028620_PA_RATE_CNTL, S_028620_VERTEX_RATE(2) | S_028620_PRIM_RATE(1)); + uint64_t rb_mask = BITFIELD64_MASK(physical_device->rad_info.max_render_backends); + + radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 2, 0)); + radeon_emit(cs, EVENT_TYPE(V_028A90_PIXEL_PIPE_STAT_CONTROL) | EVENT_INDEX(1)); + radeon_emit(cs, PIXEL_PIPE_STATE_CNTL_COUNTER_ID(0) | + PIXEL_PIPE_STATE_CNTL_STRIDE(2) | + PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_LO(rb_mask)); + radeon_emit(cs, PIXEL_PIPE_STATE_CNTL_INSTANCE_EN_HI(rb_mask)); + radeon_set_uconfig_reg(cs, R_031110_SPI_GS_THROTTLE_CNTL1, 0x12355123); radeon_set_uconfig_reg(cs, R_031114_SPI_GS_THROTTLE_CNTL2, 0x1544D); } -- 2.7.4