From fba0367e031650401e39bcfdbc374c85cd663f2f Mon Sep 17 00:00:00 2001 From: Alexander Shaposhnikov Date: Fri, 19 Aug 2022 00:13:32 +0000 Subject: [PATCH] [AArch64] Enable AdrpAdd fusion for neoverse-n1 AdrpAdd fusion is already enabled for "generic" and it helps the linker apply relocation relaxations for more adrp+add pairs. This patch enables it for -mtune=neoverse-n1. Differential revision: https://reviews.llvm.org/D132075 --- llvm/lib/Target/AArch64/AArch64.td | 3 ++- llvm/test/CodeGen/AArch64/misched-fusion-lit.ll | 14 ++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index ff39749..13b238d 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -908,7 +908,8 @@ def TuneNeoverseE1 : SubtargetFeature<"neoversee1", "ARMProcFamily", "NeoverseE1 def TuneNeoverseN1 : SubtargetFeature<"neoversen1", "ARMProcFamily", "NeoverseN1", "Neoverse N1 ARM processors", [ FeaturePostRAScheduler, - FeatureFuseAES + FeatureFuseAES, + FeatureFuseAdrpAdd ]>; def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2", diff --git a/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll b/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll index 7dc123f..9cea331 100644 --- a/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll +++ b/llvm/test/CodeGen/AArch64/misched-fusion-lit.ll @@ -6,6 +6,7 @@ ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m3 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m4 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE ; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=exynos-m5 | FileCheck %s --check-prefix=CHECK --check-prefix=CHECKFUSE +; RUN: llc %s -o - -mtriple=aarch64-unknown -mcpu=neoverse-n1 | FileCheck %s --check-prefix=CHECKFUSE-NEOVERSE @g = common local_unnamed_addr global i8* null, align 8 @@ -35,6 +36,19 @@ entry: ; CHECK-NEXT: add {{x[0-9]+}}, [[R]], :lo12:litp_tune_generic } +define dso_local i8* @litp_tune_neoverse_n1(i32 %a, i32 %b) "tune-cpu"="neoverse-n1" { +entry: + %add = add nsw i32 %b, %a + %idx.ext = sext i32 %add to i64 + %add.ptr = getelementptr i8, i8* bitcast (i8* (i32, i32)* @litp_tune_generic to i8*), i64 %idx.ext + store i8* %add.ptr, i8** @g, align 8 + ret i8* %add.ptr + +; CHECKFUSE-NEOVERSE-LABEL: litp_tune_neoverse_n1: +; CHECKFUSE-NEOVERSE: adrp [[R:x[0-9]+]], litp_tune_generic +; CHECKFUSE-NEOVERSE-NEXT: add {{x[0-9]+}}, [[R]], :lo12:litp_tune_generic +} + define dso_local i32 @liti(i32 %a, i32 %b) { entry: %add = add i32 %a, -262095121 -- 2.7.4