From fb9c5c3dce27b352534641dbb6e3cb8c05da7bc9 Mon Sep 17 00:00:00 2001
From: Hafiz Abid Qadeer <abidh@codesourcery.com>
Date: Tue, 13 Jul 2021 19:28:00 +0100
Subject: [PATCH] [lld][AMDGPU] Handle R_AMDGPU_REL16 relocation.

This patch is a followup patch to https://reviews.llvm.org/D105760 which adds this relocation. This handles the relocation in lld.

The s_branch family of instruction does the following:
PC = PC + signext(simm * 4) + 4

so we we do the opposite on the target address before writing it in the instruction stream.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D105761
---
 lld/ELF/Arch/AMDGPU.cpp       |  7 +++++++
 lld/test/ELF/amdgpu-relocs2.s | 38 ++++++++++++++++++++++++++++++++++++++
 2 files changed, 45 insertions(+)
 create mode 100644 lld/test/ELF/amdgpu-relocs2.s

diff --git a/lld/ELF/Arch/AMDGPU.cpp b/lld/ELF/Arch/AMDGPU.cpp
index c765d6e..466ad81 100644
--- a/lld/ELF/Arch/AMDGPU.cpp
+++ b/lld/ELF/Arch/AMDGPU.cpp
@@ -139,6 +139,12 @@ void AMDGPU::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
   case R_AMDGPU_REL32_HI:
     write32le(loc, val >> 32);
     break;
+  case R_AMDGPU_REL16: {
+    int64_t simm = (static_cast<int64_t>(val) - 4) / 4;
+    checkInt(loc, simm, 16, rel);
+    write16le(loc, simm);
+    break;
+  }
   default:
     llvm_unreachable("unknown relocation");
   }
@@ -154,6 +160,7 @@ RelExpr AMDGPU::getRelExpr(RelType type, const Symbol &s,
   case R_AMDGPU_REL32_LO:
   case R_AMDGPU_REL32_HI:
   case R_AMDGPU_REL64:
+  case R_AMDGPU_REL16:
     return R_PC;
   case R_AMDGPU_GOTPCREL:
   case R_AMDGPU_GOTPCREL32_LO:
diff --git a/lld/test/ELF/amdgpu-relocs2.s b/lld/test/ELF/amdgpu-relocs2.s
new file mode 100644
index 0000000..12099b8
--- /dev/null
+++ b/lld/test/ELF/amdgpu-relocs2.s
@@ -0,0 +1,38 @@
+# REQUIRES: amdgpu
+# RUN: split-file %s %t
+# RUN: llvm-mc -filetype=obj -triple=amdgcn--amdhsa -mcpu=fiji %t/asm -o %t.o
+# RUN: ld.lld %t.o -o %t/out --script %t/script
+# RUN: llvm-objdump -d %t/out | FileCheck %s
+
+
+#--- script
+SECTIONS {
+  . = 0x1000;
+  .text.likely : { *(.text.likely) }
+  . = 0x2000;
+  .text : { *(.text) }
+  . = 0x3000;
+  .text.unlikely : { *(.text.unlikely) }
+}
+
+
+#--- asm
+.section .text.likely
+hot1:
+  s_add_i32 s15, s15, 1
+hot2:
+  s_add_i32 s13, s13, 1
+.text
+foo:
+  s_branch cold2
+  s_branch hot2
+.section .text.unlikely
+cold1:
+  s_add_i32 s15, s15, 1
+  s_add_i32 s14, s14, 1
+cold2:
+  s_add_i32 s13, s13, 1
+
+# CHECK:  <foo>
+# CHECK-NEXT: s_branch 1025
+# CHECK-NEXT: s_branch 64511
-- 
2.7.4