From fb84aa2a8f52272cd0cb9510bac5404a3d4ec565 Mon Sep 17 00:00:00 2001 From: =?utf8?q?D=C3=A1vid=20Bolvansk=C3=BD?= Date: Sun, 3 Oct 2021 14:52:42 +0200 Subject: [PATCH] Fixed warnings in target/parser codes produced by -Wbitwise-instead-of-logicala --- clang/lib/Lex/PPExpressions.cpp | 4 ++-- llvm/lib/AsmParser/LLParser.cpp | 10 +++++----- llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp | 5 +++-- llvm/lib/Target/Lanai/LanaiAluCode.h | 2 +- llvm/lib/Target/Mips/MipsSubtarget.cpp | 2 +- 5 files changed, 12 insertions(+), 11 deletions(-) diff --git a/clang/lib/Lex/PPExpressions.cpp b/clang/lib/Lex/PPExpressions.cpp index 1ebfae6..424cccf 100644 --- a/clang/lib/Lex/PPExpressions.cpp +++ b/clang/lib/Lex/PPExpressions.cpp @@ -662,7 +662,7 @@ static bool EvaluateDirectiveSubExpr(PPValue &LHS, unsigned MinPrec, case tok::ampamp: // Logical && does not do UACs. break; // No UAC default: - Res.setIsUnsigned(LHS.isUnsigned()|RHS.isUnsigned()); + Res.setIsUnsigned(LHS.isUnsigned() || RHS.isUnsigned()); // If this just promoted something from signed to unsigned, and if the // value was negative, warn about it. if (ValueLive && Res.isUnsigned()) { @@ -822,7 +822,7 @@ static bool EvaluateDirectiveSubExpr(PPValue &LHS, unsigned MinPrec, // Usual arithmetic conversions (C99 6.3.1.8p1): result is unsigned if // either operand is unsigned. - Res.setIsUnsigned(RHS.isUnsigned() | AfterColonVal.isUnsigned()); + Res.setIsUnsigned(RHS.isUnsigned() || AfterColonVal.isUnsigned()); // Figure out the precedence of the token after the : part. PeekPrec = getPrecedence(PeekTok.getKind()); diff --git a/llvm/lib/AsmParser/LLParser.cpp b/llvm/lib/AsmParser/LLParser.cpp index 75dcc66..ebca7f3 100644 --- a/llvm/lib/AsmParser/LLParser.cpp +++ b/llvm/lib/AsmParser/LLParser.cpp @@ -8529,8 +8529,8 @@ bool LLParser::parseOptionalFFlags(FunctionSummary::FFlags &FFlags) { assert(Lex.getKind() == lltok::kw_funcFlags); Lex.Lex(); - if ((int)parseToken(lltok::colon, "expected ':' in funcFlags") | - (int)parseToken(lltok::lparen, "expected '(' in funcFlags")) + if (parseToken(lltok::colon, "expected ':' in funcFlags") || + parseToken(lltok::lparen, "expected '(' in funcFlags")) return true; do { @@ -8609,7 +8609,7 @@ bool LLParser::parseOptionalCalls(std::vector &Calls) { assert(Lex.getKind() == lltok::kw_calls); Lex.Lex(); - if (parseToken(lltok::colon, "expected ':' in calls") | + if (parseToken(lltok::colon, "expected ':' in calls") || parseToken(lltok::lparen, "expected '(' in calls")) return true; @@ -8701,8 +8701,8 @@ bool LLParser::parseOptionalVTableFuncs(VTableFuncList &VTableFuncs) { assert(Lex.getKind() == lltok::kw_vTableFuncs); Lex.Lex(); - if ((int)parseToken(lltok::colon, "expected ':' in vTableFuncs") | - (int)parseToken(lltok::lparen, "expected '(' in vTableFuncs")) + if (parseToken(lltok::colon, "expected ':' in vTableFuncs") || + parseToken(lltok::lparen, "expected '(' in vTableFuncs")) return true; IdToIndexMapType IdToIndexMap; diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp index 3c4191a..50e515d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp @@ -1826,8 +1826,9 @@ bool AMDGPUInstructionSelector::selectG_SELECT(MachineInstr &I) const { .add(I.getOperand(2)) .add(I.getOperand(3)); - bool Ret = constrainSelectedInstRegOperands(*Select, TII, TRI, RBI) | - constrainSelectedInstRegOperands(*CopySCC, TII, TRI, RBI); + bool Ret = false; + Ret |= constrainSelectedInstRegOperands(*Select, TII, TRI, RBI); + Ret |= constrainSelectedInstRegOperands(*CopySCC, TII, TRI, RBI); I.eraseFromParent(); return Ret; } diff --git a/llvm/lib/Target/Lanai/LanaiAluCode.h b/llvm/lib/Target/Lanai/LanaiAluCode.h index 728332b..69be055 100644 --- a/llvm/lib/Target/Lanai/LanaiAluCode.h +++ b/llvm/lib/Target/Lanai/LanaiAluCode.h @@ -70,7 +70,7 @@ inline static unsigned makePostOp(unsigned AluOp) { } inline static bool modifiesOp(unsigned AluOp) { - return isPreOp(AluOp) | isPostOp(AluOp); + return isPreOp(AluOp) || isPostOp(AluOp); } inline static const char *lanaiAluCodeToString(unsigned AluOp) { diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp index 8bb9d75..0ae2d58 100644 --- a/llvm/lib/Target/Mips/MipsSubtarget.cpp +++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp @@ -78,7 +78,7 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false), HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false), InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false), - HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16), + HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 || Mips_Os16), Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false), HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false), HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false), -- 2.7.4