From fae1d31c09172313f96e16791e823ef4b6badc5d Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 23 Apr 2021 09:33:09 -0700 Subject: [PATCH] [RISCV] Have assembler check that the temp register is different than dest register for vmsgeu.vx pseudo. Reviewed By: HsiangKai Differential Revision: https://reviews.llvm.org/D101015 --- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp | 11 +++++++++++ llvm/test/MC/RISCV/rvv/invalid.s | 6 ++++++ 2 files changed, 17 insertions(+) diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 1130e754..e96a4c0 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -2461,6 +2461,17 @@ std::unique_ptr RISCVAsmParser::defaultMaskRegOp() const { bool RISCVAsmParser::validateInstruction(MCInst &Inst, OperandVector &Operands) { + if (Inst.getOpcode() == RISCV::PseudoVMSGEU_VX_M_T || + Inst.getOpcode() == RISCV::PseudoVMSGE_VX_M_T) { + unsigned DestReg = Inst.getOperand(0).getReg(); + unsigned TempReg = Inst.getOperand(1).getReg(); + if (DestReg == TempReg) { + SMLoc Loc = Operands.back()->getStartLoc(); + return Error(Loc, "The temporary vector register cannot be the same as " + "the destination register."); + } + } + const MCInstrDesc &MCID = MII.get(Inst.getOpcode()); unsigned Constraints = (MCID.TSFlags & RISCVII::ConstraintMask) >> RISCVII::ConstraintShift; diff --git a/llvm/test/MC/RISCV/rvv/invalid.s b/llvm/test/MC/RISCV/rvv/invalid.s index 35a88e4..501cbe2 100644 --- a/llvm/test/MC/RISCV/rvv/invalid.s +++ b/llvm/test/MC/RISCV/rvv/invalid.s @@ -666,3 +666,9 @@ vmsge.vx v2, v4, a0, v0.t, v0 vmsgeu.vx v2, v4, a0, v0.t, v0 # CHECK-ERROR: invalid operand for instruction + +vmsge.vx v2, v4, a0, v0.t, v2 +# CHECK-ERROR: The temporary vector register cannot be the same as the destination register. + +vmsgeu.vx v2, v4, a0, v0.t, v2 +# CHECK-ERROR: The temporary vector register cannot be the same as the destination register. -- 2.7.4