From faad567589a3de43b02a4cdb27fb00f79b567d4c Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Wed, 31 Aug 2022 14:01:41 +0100 Subject: [PATCH] [LV] Add test case where SCEV is needed to remove vector backedge. Test case mentioned in the discussion for D115261. --- .../vector-loop-backedge-elimination.ll | 37 ++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination.ll diff --git a/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination.ll b/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination.ll new file mode 100644 index 0000000..9cb78e4 --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/vector-loop-backedge-elimination.ll @@ -0,0 +1,37 @@ +; RUN: opt -passes=loop-vectorize -force-vector-width=8 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=CHECK,VF8UF1 %s +; RUN: opt -passes=loop-vectorize -force-vector-width=8 -force-vector-interleave=2 -S %s | FileCheck --check-prefixes=CHECK,VF8UF2 %s +; RUN: opt -passes=loop-vectorize -force-vector-width=16 -force-vector-interleave=1 -S %s | FileCheck --check-prefixes=CHECK,VF16UF1 %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" + +; Check if the vector loop condition can be simplified to true for a given +; VF/IC combination. +define void @test_tc_less_than_16(ptr %A, i64 %N) { +; CHECK-LABEL: define void @test_tc_less_than_16( +; VF8UF1: [[CMP:%.+]] = icmp eq i64 %index.next, %n.vec +; VF8UF1-NEXT: br i1 [[CMP]], label %middle.block, label %vector.body +; +; VF8UF2: [[CMP:%.+]] = icmp eq i64 %index.next, %n.vec +; VF8UF2-NEXT: br i1 [[CMP]], label %middle.block, label %vector.body +; +; VF16UF1: [[CMP:%.+]] = icmp eq i64 %index.next, %n.vec +; VF16UF1-NEXT: br i1 [[CMP]], label %middle.block, label %vector.body +; +entry: + %and = and i64 %N, 15 + br label %loop + +loop: + %iv = phi i64 [ %and, %entry ], [ %iv.next, %loop ] + %p.src = phi ptr [ %A, %entry ], [ %p.src.next, %loop ] + %p.src.next = getelementptr inbounds i8, ptr %p.src, i64 1 + %l = load i8, ptr %p.src, align 1 + %add = add nsw i8 %l, 10 + store i8 %add, ptr %p.src + %iv.next = add nsw i64 %iv, -1 + %cmp = icmp eq i64 %iv.next, 0 + br i1 %cmp, label %exit, label %loop + +exit: + ret void +} -- 2.7.4