From fa331559f189aaec90bd951ffcab65ccc69ad2d4 Mon Sep 17 00:00:00 2001 From: Heesub Shin Date: Thu, 1 Jun 2017 11:18:44 +0900 Subject: [PATCH] s5j/timerisr: add missing initialization on RTC The first stage bootloader is initializing RTCCON[7:4] to 0x4 before it jumps to subsequent stages. This is no harm if we clear it while initializing the RTC, but it is not cleared when CONFIG_RTC is not set and causing OS timetick to be generated at 2048Hz. To avoid this issue, we need to clear it always before enabling the timer isr. Change-Id: Id27a079e35f5d0a93d6a6428117daa3d45b71a61 Signed-off-by: Heesub Shin --- os/arch/arm/src/s5j/s5j_timerisr.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/os/arch/arm/src/s5j/s5j_timerisr.c b/os/arch/arm/src/s5j/s5j_timerisr.c index 0240a33..ef53455 100644 --- a/os/arch/arm/src/s5j/s5j_timerisr.c +++ b/os/arch/arm/src/s5j/s5j_timerisr.c @@ -117,7 +117,8 @@ void up_timer_initialize(void) /* Configure the RTC timetick to generate periodic interrupts */ modifyreg32(S5J_RTC_RTCCON, RTC_RTCCON_TICKEN0_ENABLE, 0); putreg32(SYSTICK_RELOAD, S5J_RTC_TICCNT0); - modifyreg32(S5J_RTC_RTCCON, 0, RTC_RTCCON_TICKEN0_ENABLE); + modifyreg32(S5J_RTC_RTCCON, RTC_RTCCON_TICCKSEL0_MASK, + RTC_RTCCON_TICKEN0_ENABLE | RTC_RTCCON_TICCKSEL0_32768HZ); /* Attach the timer interrupt vector */ irq_attach(IRQ_TOP_RTC_TIC, up_timerisr, NULL); -- 2.7.4