From f9ee1898eccb5ac0b164a4d6c7a06bf002d23c0e Mon Sep 17 00:00:00 2001 From: "yanhong.wang" Date: Wed, 8 Jun 2022 11:08:16 +0800 Subject: [PATCH] clk:starfive:jh7110: Change uart3-uart5 clk register info The core_clk division register of uart3-uart5 include fractional and integral parts,but now only use the integral part,so include shift operation. The integral part include 8 bit,so the max value can be configed is 255.In order to support 115200 bandrate,so limit the max value to 10. Signed-off-by: yanhong.wang --- drivers/clk/starfive/clk-starfive-jh7110-gen.c | 10 ++++++++++ drivers/clk/starfive/clk-starfive-jh7110-sys.c | 6 +++--- 2 files changed, 13 insertions(+), 3 deletions(-) mode change 100755 => 100644 drivers/clk/starfive/clk-starfive-jh7110-gen.c mode change 100755 => 100644 drivers/clk/starfive/clk-starfive-jh7110-sys.c diff --git a/drivers/clk/starfive/clk-starfive-jh7110-gen.c b/drivers/clk/starfive/clk-starfive-jh7110-gen.c old mode 100755 new mode 100644 index 437065b..f017d33 --- a/drivers/clk/starfive/clk-starfive-jh7110-gen.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-gen.c @@ -63,6 +63,11 @@ static void jh7110_clk_reg_rmw(struct jh7110_clk *clk, u32 mask, u32 value) unsigned long flags; spin_lock_irqsave(&priv->rmw_lock, flags); + if ((clk->idx == JH7110_UART3_CLK_CORE + || clk->idx == JH7110_UART4_CLK_CORE + || clk->idx == JH7110_UART5_CLK_CORE) + && (value != JH7110_CLK_ENABLE)) + value <<= 8; value |= readl_relaxed(reg) & ~mask; writel_relaxed(value, reg); spin_unlock_irqrestore(&priv->rmw_lock, flags); @@ -96,6 +101,11 @@ static unsigned long jh7110_clk_recalc_rate(struct clk_hw *hw, struct jh7110_clk *clk = jh7110_clk_from(hw); u32 div = jh7110_clk_reg_get(clk) & JH7110_CLK_DIV_MASK; + if (clk->idx == JH7110_UART3_CLK_CORE + || clk->idx == JH7110_UART4_CLK_CORE + || clk->idx == JH7110_UART5_CLK_CORE) + div = div >> 8; + return div ? parent_rate / div : 0; } diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c old mode 100755 new mode 100644 index 0676b47..cbcbc47 --- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c +++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c @@ -352,15 +352,15 @@ static const struct jh7110_clk_data jh7110_clk_sys_data[] __initconst = { JH7110_GATE(JH7110_UART3_CLK_APB, "u3_dw_uart_clk_apb", GATE_FLAG_NORMAL, JH7110_APB0), JH7110_GDIV(JH7110_UART3_CLK_CORE, "u3_dw_uart_clk_core", - GATE_FLAG_NORMAL, 131071, JH7110_PERH_ROOT), + GATE_FLAG_NORMAL, 10, JH7110_PERH_ROOT), JH7110_GATE(JH7110_UART4_CLK_APB, "u4_dw_uart_clk_apb", GATE_FLAG_NORMAL, JH7110_APB0), JH7110_GDIV(JH7110_UART4_CLK_CORE, "u4_dw_uart_clk_core", - GATE_FLAG_NORMAL, 131071, JH7110_PERH_ROOT), + GATE_FLAG_NORMAL, 10, JH7110_PERH_ROOT), JH7110_GATE(JH7110_UART5_CLK_APB, "u5_dw_uart_clk_apb", GATE_FLAG_NORMAL, JH7110_APB0), JH7110_GDIV(JH7110_UART5_CLK_CORE, "u5_dw_uart_clk_core", - GATE_FLAG_NORMAL, 131071, JH7110_PERH_ROOT), + GATE_FLAG_NORMAL, 10, JH7110_PERH_ROOT), //PWMDAC JH7110_GATE(JH7110_PWMDAC_CLK_APB, "u0_pwmdac_clk_apb", GATE_FLAG_NORMAL, JH7110_APB0), -- 2.7.4