From f95dcc81045c8eb1bd86f7223704c14690f7d401 Mon Sep 17 00:00:00 2001 From: Alexander Ivchenko Date: Wed, 24 Sep 2014 08:00:35 +0000 Subject: [PATCH] AVX-512. Add widening pmov. gcc/ * config/i386/sse.md (define_insn "avx2_v16qiv16hi2"): Add masking. (define_insn "avx512bw_v32qiv32hi2"): New. (define_insn "sse4_1_v8qiv8hi2"): Add masking. (define_insn "avx2_v8qiv8si2"): Ditto. (define_insn "sse4_1_v4qiv4si2"): Ditto. (define_insn "avx2_v8hiv8si2"): Ditto. (define_insn "sse4_1_v4hiv4si2"): Ditto. (define_insn "avx2_v4qiv4di2"): Ditto. (define_insn "sse4_1_v2qiv2di2"): Ditto. (define_insn "avx2_v4hiv4di2"): Ditto. (define_insn "sse4_1_v2hiv2di2"): Ditto. (define_insn "avx2_v4siv4di2"): Ditto. (define_insn "sse4_1_v2siv2di2"): Ditto. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin From-SVN: r215541 --- gcc/ChangeLog | 24 +++++++++ gcc/config/i386/sse.md | 142 +++++++++++++++++++++++++++---------------------- 2 files changed, 101 insertions(+), 65 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 10dbc52..05e1411 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,27 @@ +2014-09-24 Alexander Ivchenko + Maxim Kuznetsov + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/sse.md + (define_insn "avx2_v16qiv16hi2"): Add masking. + (define_insn "avx512bw_v32qiv32hi2"): New. + (define_insn "sse4_1_v8qiv8hi2"): Add masking. + (define_insn "avx2_v8qiv8si2"): Ditto. + (define_insn "sse4_1_v4qiv4si2"): Ditto. + (define_insn "avx2_v8hiv8si2"): Ditto. + (define_insn "sse4_1_v4hiv4si2"): Ditto. + (define_insn "avx2_v4qiv4di2"): Ditto. + (define_insn "sse4_1_v2qiv2di2"): Ditto. + (define_insn "avx2_v4hiv4di2"): Ditto. + (define_insn "sse4_1_v2hiv2di2"): Ditto. + (define_insn "avx2_v4siv4di2"): Ditto. + (define_insn "sse4_1_v2siv2di2"): Ditto. + 2014-09-24 Zhenqiang Chen PR rtl-optimization/63210 diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 9e0c0e8..a7cc5ad 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -13330,28 +13330,39 @@ (set_attr "prefix" "maybe_vex") (set_attr "mode" "TI")]) -(define_insn "avx2_v16qiv16hi2" - [(set (match_operand:V16HI 0 "register_operand" "=x") +(define_insn "avx2_v16qiv16hi2" + [(set (match_operand:V16HI 0 "register_operand" "=v") (any_extend:V16HI - (match_operand:V16QI 1 "nonimmediate_operand" "xm")))] - "TARGET_AVX2" - "vpmovbw\t{%1, %0|%0, %1}" + (match_operand:V16QI 1 "nonimmediate_operand" "vm")))] + "TARGET_AVX2 && && " + "vpmovbw\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "vex") + (set_attr "prefix" "maybe_evex") (set_attr "mode" "OI")]) -(define_insn "sse4_1_v8qiv8hi2" - [(set (match_operand:V8HI 0 "register_operand" "=x") +(define_insn "avx512bw_v32qiv32hi2" + [(set (match_operand:V32HI 0 "register_operand" "=v") + (any_extend:V32HI + (match_operand:V32QI 1 "nonimmediate_operand" "vm")))] + "TARGET_AVX512BW" + "vpmovbw\t{%1, %0|%0, %1}" + [(set_attr "type" "ssemov") + (set_attr "prefix_extra" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "XI")]) + +(define_insn "sse4_1_v8qiv8hi2" + [(set (match_operand:V8HI 0 "register_operand" "=v") (any_extend:V8HI (vec_select:V8QI - (match_operand:V16QI 1 "nonimmediate_operand" "xm") + (match_operand:V16QI 1 "nonimmediate_operand" "vm") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3) (const_int 4) (const_int 5) (const_int 6) (const_int 7)]))))] - "TARGET_SSE4_1" - "%vpmovbw\t{%1, %0|%0, %q1}" + "TARGET_SSE4_1 && && " + "%vpmovbw\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") (set_attr "ssememalign" "64") (set_attr "prefix_extra" "1") @@ -13368,31 +13379,31 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "avx2_v8qiv8si2" - [(set (match_operand:V8SI 0 "register_operand" "=x") +(define_insn "avx2_v8qiv8si2" + [(set (match_operand:V8SI 0 "register_operand" "=v") (any_extend:V8SI (vec_select:V8QI - (match_operand:V16QI 1 "nonimmediate_operand" "xm") + (match_operand:V16QI 1 "nonimmediate_operand" "vm") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3) (const_int 4) (const_int 5) (const_int 6) (const_int 7)]))))] - "TARGET_AVX2" - "vpmovbd\t{%1, %0|%0, %q1}" + "TARGET_AVX2 && " + "vpmovbd\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "vex") + (set_attr "prefix" "maybe_evex") (set_attr "mode" "OI")]) -(define_insn "sse4_1_v4qiv4si2" - [(set (match_operand:V4SI 0 "register_operand" "=x") +(define_insn "sse4_1_v4qiv4si2" + [(set (match_operand:V4SI 0 "register_operand" "=v") (any_extend:V4SI (vec_select:V4QI - (match_operand:V16QI 1 "nonimmediate_operand" "xm") + (match_operand:V16QI 1 "nonimmediate_operand" "vm") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))] - "TARGET_SSE4_1" - "%vpmovbd\t{%1, %0|%0, %k1}" + "TARGET_SSE4_1 && " + "%vpmovbd\t{%1, %0|%0, %k1}" [(set_attr "type" "ssemov") (set_attr "ssememalign" "32") (set_attr "prefix_extra" "1") @@ -13409,26 +13420,26 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "avx2_v8hiv8si2" - [(set (match_operand:V8SI 0 "register_operand" "=x") +(define_insn "avx2_v8hiv8si2" + [(set (match_operand:V8SI 0 "register_operand" "=v") (any_extend:V8SI - (match_operand:V8HI 1 "nonimmediate_operand" "xm")))] - "TARGET_AVX2" - "vpmovwd\t{%1, %0|%0, %1}" + (match_operand:V8HI 1 "nonimmediate_operand" "vm")))] + "TARGET_AVX2 && " + "vpmovwd\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "vex") + (set_attr "prefix" "maybe_evex") (set_attr "mode" "OI")]) -(define_insn "sse4_1_v4hiv4si2" - [(set (match_operand:V4SI 0 "register_operand" "=x") +(define_insn "sse4_1_v4hiv4si2" + [(set (match_operand:V4SI 0 "register_operand" "=v") (any_extend:V4SI (vec_select:V4HI - (match_operand:V8HI 1 "nonimmediate_operand" "xm") + (match_operand:V8HI 1 "nonimmediate_operand" "vm") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))] - "TARGET_SSE4_1" - "%vpmovwd\t{%1, %0|%0, %q1}" + "TARGET_SSE4_1 && " + "%vpmovwd\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") (set_attr "ssememalign" "64") (set_attr "prefix_extra" "1") @@ -13450,28 +13461,28 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "avx2_v4qiv4di2" - [(set (match_operand:V4DI 0 "register_operand" "=x") +(define_insn "avx2_v4qiv4di2" + [(set (match_operand:V4DI 0 "register_operand" "=v") (any_extend:V4DI (vec_select:V4QI - (match_operand:V16QI 1 "nonimmediate_operand" "xm") + (match_operand:V16QI 1 "nonimmediate_operand" "vm") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))] - "TARGET_AVX2" - "vpmovbq\t{%1, %0|%0, %k1}" + "TARGET_AVX2 && " + "vpmovbq\t{%1, %0|%0, %k1}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "vex") + (set_attr "prefix" "maybe_evex") (set_attr "mode" "OI")]) -(define_insn "sse4_1_v2qiv2di2" - [(set (match_operand:V2DI 0 "register_operand" "=x") +(define_insn "sse4_1_v2qiv2di2" + [(set (match_operand:V2DI 0 "register_operand" "=v") (any_extend:V2DI (vec_select:V2QI - (match_operand:V16QI 1 "nonimmediate_operand" "xm") + (match_operand:V16QI 1 "nonimmediate_operand" "vm") (parallel [(const_int 0) (const_int 1)]))))] - "TARGET_SSE4_1" - "%vpmovbq\t{%1, %0|%0, %w1}" + "TARGET_SSE4_1 && " + "%vpmovbq\t{%1, %0|%0, %w1}" [(set_attr "type" "ssemov") (set_attr "ssememalign" "16") (set_attr "prefix_extra" "1") @@ -13488,28 +13499,28 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "avx2_v4hiv4di2" - [(set (match_operand:V4DI 0 "register_operand" "=x") +(define_insn "avx2_v4hiv4di2" + [(set (match_operand:V4DI 0 "register_operand" "=v") (any_extend:V4DI (vec_select:V4HI - (match_operand:V8HI 1 "nonimmediate_operand" "xm") + (match_operand:V8HI 1 "nonimmediate_operand" "vm") (parallel [(const_int 0) (const_int 1) (const_int 2) (const_int 3)]))))] - "TARGET_AVX2" - "vpmovwq\t{%1, %0|%0, %q1}" + "TARGET_AVX2 && " + "vpmovwq\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") (set_attr "prefix_extra" "1") - (set_attr "prefix" "vex") + (set_attr "prefix" "maybe_evex") (set_attr "mode" "OI")]) -(define_insn "sse4_1_v2hiv2di2" - [(set (match_operand:V2DI 0 "register_operand" "=x") +(define_insn "sse4_1_v2hiv2di2" + [(set (match_operand:V2DI 0 "register_operand" "=v") (any_extend:V2DI (vec_select:V2HI - (match_operand:V8HI 1 "nonimmediate_operand" "xm") + (match_operand:V8HI 1 "nonimmediate_operand" "vm") (parallel [(const_int 0) (const_int 1)]))))] - "TARGET_SSE4_1" - "%vpmovwq\t{%1, %0|%0, %k1}" + "TARGET_SSE4_1 && " + "%vpmovwq\t{%1, %0|%0, %k1}" [(set_attr "type" "ssemov") (set_attr "ssememalign" "32") (set_attr "prefix_extra" "1") @@ -13526,24 +13537,25 @@ (set_attr "prefix" "evex") (set_attr "mode" "XI")]) -(define_insn "avx2_v4siv4di2" - [(set (match_operand:V4DI 0 "register_operand" "=x") +(define_insn "avx2_v4siv4di2" + [(set (match_operand:V4DI 0 "register_operand" "=v") (any_extend:V4DI - (match_operand:V4SI 1 "nonimmediate_operand" "xm")))] - "TARGET_AVX2" - "vpmovdq\t{%1, %0|%0, %1}" + (match_operand:V4SI 1 "nonimmediate_operand" "vm")))] + "TARGET_AVX2 && " + "vpmovdq\t{%1, %0|%0, %1}" [(set_attr "type" "ssemov") + (set_attr "prefix" "maybe_evex") (set_attr "prefix_extra" "1") (set_attr "mode" "OI")]) -(define_insn "sse4_1_v2siv2di2" - [(set (match_operand:V2DI 0 "register_operand" "=x") +(define_insn "sse4_1_v2siv2di2" + [(set (match_operand:V2DI 0 "register_operand" "=v") (any_extend:V2DI (vec_select:V2SI - (match_operand:V4SI 1 "nonimmediate_operand" "xm") + (match_operand:V4SI 1 "nonimmediate_operand" "vm") (parallel [(const_int 0) (const_int 1)]))))] - "TARGET_SSE4_1" - "%vpmovdq\t{%1, %0|%0, %q1}" + "TARGET_SSE4_1 && " + "%vpmovdq\t{%1, %0|%0, %q1}" [(set_attr "type" "ssemov") (set_attr "ssememalign" "64") (set_attr "prefix_extra" "1") -- 2.7.4