From f94c79674105afe08da0e60f937e62b0035d72d7 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Zolt=C3=A1n=20B=C3=B6sz=C3=B6rm=C3=A9nyi?= Date: Fri, 2 Jul 2021 12:18:12 +0200 Subject: [PATCH] crocus: Make the driver loader use PCI IDs for crocus MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Add PCI IDs based in pci_ids/i965_pci_ids.h and move crocus before iris in driver_map[]. This allows Xorg to load the crocus driver since iris would claim the devices handled by crocus (because the i915 kernel driver is used for all Intel devices) then fail during initialization. Signed-off-by: Zoltán Böszörményi Reviewed-by: Dave Airlie Part-of: --- include/pci_ids/crocus_pci_ids.h | 104 +++++++++++++++++++++++++++++++++++++++ src/loader/pci_id_driver_map.h | 8 ++- 2 files changed, 111 insertions(+), 1 deletion(-) create mode 100644 include/pci_ids/crocus_pci_ids.h diff --git a/include/pci_ids/crocus_pci_ids.h b/include/pci_ids/crocus_pci_ids.h new file mode 100644 index 0000000..9c9b6cd --- /dev/null +++ b/include/pci_ids/crocus_pci_ids.h @@ -0,0 +1,104 @@ +CHIPSET(0x29A2, i965, "BW", "Intel(R) 965G") +CHIPSET(0x2992, i965, "BW", "Intel(R) 965Q") +CHIPSET(0x2982, i965, "BW", "Intel(R) 965G") +CHIPSET(0x2972, i965, "BW", "Intel(R) 946GZ") +CHIPSET(0x2A02, i965, "CL", "Intel(R) 965GM") +CHIPSET(0x2A12, i965, "CL", "Intel(R) 965GME/GLE") + +CHIPSET(0x2A42, g4x, "CTG", "Mobile Intel® GM45 Express Chipset") +CHIPSET(0x2E02, g4x, "ELK", "Intel(R) Integrated Graphics Device") +CHIPSET(0x2E12, g4x, "ELK", "Intel(R) Q45/Q43") +CHIPSET(0x2E22, g4x, "ELK", "Intel(R) G45/G43") +CHIPSET(0x2E32, g4x, "ELK", "Intel(R) G41") +CHIPSET(0x2E42, g4x, "ELK", "Intel(R) B43") +CHIPSET(0x2E92, g4x, "ELK", "Intel(R) B43") + +CHIPSET(0x0042, ilk, "ILK", "Intel(R) HD Graphics") +CHIPSET(0x0046, ilk, "ILK", "Intel(R) HD Graphics") + +CHIPSET(0x0102, snb_gt1, "SNB GT1", "Intel(R) HD Graphics 2000") +CHIPSET(0x0112, snb_gt2, "SNB GT2", "Intel(R) HD Graphics 3000") +CHIPSET(0x0122, snb_gt2, "SNB GT2", "Intel(R) HD Graphics 3000") +CHIPSET(0x0106, snb_gt1, "SNB GT1", "Intel(R) HD Graphics 2000") +CHIPSET(0x0116, snb_gt2, "SNB GT2", "Intel(R) HD Graphics 3000") +CHIPSET(0x0126, snb_gt2, "SNB GT2", "Intel(R) HD Graphics 3000") +CHIPSET(0x010A, snb_gt1, "SNB GT1", "Intel(R) HD Graphics 2000") + +CHIPSET(0x0152, ivb_gt1, "IVB GT1", "Intel(R) HD Graphics 2500") +CHIPSET(0x0162, ivb_gt2, "IVB GT2", "Intel(R) HD Graphics 4000") +CHIPSET(0x0156, ivb_gt1, "IVB GT1", "Intel(R) HD Graphics 2500") +CHIPSET(0x0166, ivb_gt2, "IVB GT2", "Intel(R) HD Graphics 4000") +CHIPSET(0x015a, ivb_gt1, "IVB GT1", "Intel(R) HD Graphics") +CHIPSET(0x016a, ivb_gt2, "IVB GT2", "Intel(R) HD Graphics P4000") + +CHIPSET(0x0402, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0412, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics 4600") +CHIPSET(0x0422, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") +CHIPSET(0x0406, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0416, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics 4600") +CHIPSET(0x0426, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") +CHIPSET(0x040A, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x041A, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics P4600/P4700") +CHIPSET(0x042A, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") +CHIPSET(0x040B, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x041B, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") +CHIPSET(0x042B, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") +CHIPSET(0x040E, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x041E, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics 4400") +CHIPSET(0x042E, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") +CHIPSET(0x0C02, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0C12, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") +CHIPSET(0x0C22, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") +CHIPSET(0x0C06, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0C16, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") +CHIPSET(0x0C26, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") +CHIPSET(0x0C0A, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0C1A, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") +CHIPSET(0x0C2A, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") +CHIPSET(0x0C0B, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0C1B, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") +CHIPSET(0x0C2B, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") +CHIPSET(0x0C0E, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0C1E, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") +CHIPSET(0x0C2E, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") +CHIPSET(0x0A02, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0A12, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") +CHIPSET(0x0A22, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") +CHIPSET(0x0A06, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0A16, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics 4400") +CHIPSET(0x0A26, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics 5000") +CHIPSET(0x0A0A, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0A1A, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") +CHIPSET(0x0A2A, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") +CHIPSET(0x0A0B, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0A1B, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") +CHIPSET(0x0A2B, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") +CHIPSET(0x0A0E, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0A1E, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics 4200") +CHIPSET(0x0A2E, hsw_gt3, "HSW GT3", "Intel(R) Iris(R) Graphics 5100") +CHIPSET(0x0D02, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0D12, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics 4600") +CHIPSET(0x0D22, hsw_gt3, "HSW GT3", "Intel(R) Iris(R) Pro Graphics 5200") +CHIPSET(0x0D06, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0D16, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") +CHIPSET(0x0D26, hsw_gt3, "HSW GT3", "Intel(R) Iris(R) Pro Graphics P5200") +CHIPSET(0x0D0A, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0D1A, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") +CHIPSET(0x0D2A, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") +CHIPSET(0x0D0B, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0D1B, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") +CHIPSET(0x0D2B, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") +CHIPSET(0x0D0E, hsw_gt1, "HSW GT1", "Intel(R) HD Graphics") +CHIPSET(0x0D1E, hsw_gt2, "HSW GT2", "Intel(R) HD Graphics") +CHIPSET(0x0D2E, hsw_gt3, "HSW GT3", "Intel(R) HD Graphics") + +CHIPSET(0x0F31, byt, "BYT", "Intel(R) HD Graphics") +CHIPSET(0x0F32, byt, "BYT", "Intel(R) HD Graphics") +CHIPSET(0x0F33, byt, "BYT", "Intel(R) HD Graphics") +CHIPSET(0x0157, byt, "BYT", "Intel(R) HD Graphics") +CHIPSET(0x0155, byt, "BYT", "Intel(R) HD Graphics") + +CHIPSET(0x22B0, chv, "CHV", "Intel(R) HD Graphics") +CHIPSET(0x22B1, chv, "BSW", "Intel(R) HD Graphics XXX") /* Overridden in brw_get_renderer_string */ +CHIPSET(0x22B2, chv, "CHV", "Intel(R) HD Graphics") +CHIPSET(0x22B3, chv, "CHV", "Intel(R) HD Graphics") diff --git a/src/loader/pci_id_driver_map.h b/src/loader/pci_id_driver_map.h index 1cece69..d75b2cc 100644 --- a/src/loader/pci_id_driver_map.h +++ b/src/loader/pci_id_driver_map.h @@ -26,6 +26,12 @@ static const int i965_chip_ids[] = { #undef CHIPSET }; +static const int crocus_chip_ids[] = { +#define CHIPSET(chip, family, family_str, name) chip, +#include "pci_ids/crocus_pci_ids.h" +#undef CHIPSET +}; + static const int r100_chip_ids[] = { #define CHIPSET(chip, name, family) chip, #include "pci_ids/radeon_pci_ids.h" @@ -75,8 +81,8 @@ static const struct { { 0x8086, "i830", i830_chip_ids, ARRAY_SIZE(i830_chip_ids) }, { 0x8086, "i915", i915_chip_ids, ARRAY_SIZE(i915_chip_ids) }, { 0x8086, "i965", i965_chip_ids, ARRAY_SIZE(i965_chip_ids) }, + { 0x8086, "crocus", crocus_chip_ids, ARRAY_SIZE(crocus_chip_ids) }, { 0x8086, "iris", NULL, -1, is_kernel_i915 }, - { 0x8086, "crocus", NULL, -1, is_kernel_i915 }, { 0x1002, "radeon", r100_chip_ids, ARRAY_SIZE(r100_chip_ids) }, { 0x1002, "r200", r200_chip_ids, ARRAY_SIZE(r200_chip_ids) }, { 0x1002, "r300", r300_chip_ids, ARRAY_SIZE(r300_chip_ids) }, -- 2.7.4