From f85bcec31ee578eccf6182be158d6ac6d9b90a4c Mon Sep 17 00:00:00 2001 From: Nicholas Piggin Date: Thu, 20 Oct 2016 17:59:10 +1100 Subject: [PATCH] ppc: fix MSR_ME handling for system reset interrupt MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Power ISA specifies ME bit handling for system reset interrupt: if the interrupt occurred while the thread was in power-saving mode, set to 1; otherwise not altered Power ISA 3.0, section 6.5 "Interrupt Definitions", Figure 64. Signed-off-by: Nicholas Piggin Reviewed-by: Greg Kurz Reviewed-by: Cédric Le Goater Signed-off-by: David Gibson --- target-ppc/excp_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index 921c39d..53c4075 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -385,11 +385,11 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) srr1 = SPR_BOOKE_CSRR1; break; case POWERPC_EXCP_RESET: /* System reset exception */ + /* A power-saving exception sets ME, otherwise it is unchanged */ if (msr_pow) { /* indicate that we resumed from power save mode */ msr |= 0x10000; - } else { - new_msr &= ~((target_ulong)1 << MSR_ME); + new_msr |= ((target_ulong)1 << MSR_ME); } new_msr |= (target_ulong)MSR_HVB; -- 2.7.4