From f8558d1fb5aa8ddc65112a392ee527489b8bb650 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Thu, 30 Mar 2023 17:08:27 +0200 Subject: [PATCH] radv: configure PA_SC_MODE_CNTL_1 during cmdbuf recording Two graphics pipeline parameters need to be copied to the cmdbuf state. Signed-off-by: Samuel Pitoiset Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 25 ++++++++++++++++++++++--- src/amd/vulkan/radv_pipeline.c | 25 +++---------------------- src/amd/vulkan/radv_private.h | 10 +++++++++- 3 files changed, 34 insertions(+), 26 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index c45544a..742f1da 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1887,9 +1887,11 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer) if (cmd_buffer->state.emitted_graphics_pipeline->ms.sample_shading_enable != pipeline->ms.sample_shading_enable || cmd_buffer->state.emitted_graphics_pipeline->ms.min_sample_shading != pipeline->ms.min_sample_shading || - cmd_buffer->state.emitted_graphics_pipeline->pa_sc_mode_cntl_1 != pipeline->pa_sc_mode_cntl_1 || + cmd_buffer->state.emitted_graphics_pipeline->uses_out_of_order_rast != pipeline->uses_out_of_order_rast || + cmd_buffer->state.emitted_graphics_pipeline->uses_vrs_attachment != pipeline->uses_vrs_attachment || cmd_buffer->state.emitted_graphics_pipeline->db_render_control != pipeline->db_render_control || cmd_buffer->state.emitted_graphics_pipeline->rast_prim != pipeline->rast_prim) + cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZATION_SAMPLES; } @@ -2555,15 +2557,29 @@ radv_emit_depth_clamp_enable(struct radv_cmd_buffer *cmd_buffer) static void radv_emit_rasterization_samples(struct radv_cmd_buffer *cmd_buffer) { - const struct radv_graphics_pipeline *pipeline = cmd_buffer->state.graphics_pipeline; const struct radv_physical_device *pdevice = cmd_buffer->device->physical_device; const struct radv_shader *ps = cmd_buffer->state.shaders[MESA_SHADER_FRAGMENT]; unsigned rasterization_samples = radv_get_rasterization_samples(cmd_buffer); const struct radv_rendering_state *render = &cmd_buffer->state.render; - unsigned pa_sc_mode_cntl_1 = pipeline->pa_sc_mode_cntl_1; const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1); unsigned db_render_control = cmd_buffer->state.db_render_control; + unsigned pa_sc_mode_cntl_1; + + pa_sc_mode_cntl_1 = + S_028A4C_WALK_FENCE_ENABLE(1) | // TODO linear dst fixes + S_028A4C_WALK_FENCE_SIZE(pdevice->rad_info.num_tile_pipes == 2 ? 2 : 3) | + S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(cmd_buffer->state.uses_out_of_order_rast) | + S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) | + /* always 1: */ + S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) | S_028A4C_TILE_WALK_ORDER_ENABLE(1) | + S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) | S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | + S_028A4C_FORCE_EOV_REZ_ENABLE(1) | + /* This should only be set when VRS surfaces aren't enabled on GFX11, otherwise the GPU might + * hang. + */ + S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(pdevice->rad_info.gfx_level < GFX11 || + !cmd_buffer->state.uses_vrs_attachment); if (!d->sample_location.count) radv_emit_default_sample_locations(cmd_buffer->cs, rasterization_samples); @@ -6636,6 +6652,9 @@ radv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipeline cmd_buffer->state.rast_prim = graphics_pipeline->rast_prim; cmd_buffer->state.ia_multi_vgt_param = graphics_pipeline->ia_multi_vgt_param; + + cmd_buffer->state.uses_out_of_order_rast = graphics_pipeline->uses_out_of_order_rast; + cmd_buffer->state.uses_vrs_attachment = graphics_pipeline->uses_vrs_attachment; break; } default: diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 6d6f5bc..a75c9f2 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -456,11 +456,7 @@ radv_pipeline_init_multisample_state(const struct radv_device *device, const struct vk_graphics_pipeline_state *state, unsigned rast_prim) { - const struct radv_physical_device *pdevice = device->physical_device; struct radv_multisample_state *ms = &pipeline->ms; - unsigned num_tile_pipes = pdevice->rad_info.num_tile_pipes; - bool out_of_order_rast = - state->rs->rasterization_order_amd == VK_RASTERIZATION_ORDER_RELAXED_AMD; /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading: * @@ -483,24 +479,6 @@ radv_pipeline_init_multisample_state(const struct radv_device *device, ms->min_sample_shading = state->ms->min_sample_shading; } - pipeline->pa_sc_mode_cntl_1 = - S_028A4C_WALK_FENCE_ENABLE(1) | // TODO linear dst fixes - S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) | - S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) | - S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) | - /* always 1: */ - S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) | S_028A4C_TILE_WALK_ORDER_ENABLE(1) | - S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) | S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) | - S_028A4C_FORCE_EOV_REZ_ENABLE(1); - - if (pdevice->rad_info.gfx_level < GFX11 || - !radv_pipeline_uses_vrs_attachment(pCreateInfo, state)) { - /* This should only be set when VRS surfaces aren't enabled on GFX11, otherwise the GPU might - * hang. - */ - pipeline->pa_sc_mode_cntl_1 |= S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1); - } - ms->uses_user_sample_locations = state->ms && state->ms->sample_locations_enable; } @@ -4715,6 +4693,9 @@ radv_graphics_pipeline_init(struct radv_graphics_pipeline *pipeline, struct radv pipeline->force_vrs_per_vertex = pipeline->base.shaders[pipeline->last_vgt_api_stage]->info.force_vrs_per_vertex; pipeline->rast_prim = vgt_gs_out_prim_type; + pipeline->uses_out_of_order_rast = + state.rs->rasterization_order_amd == VK_RASTERIZATION_ORDER_RELAXED_AMD; + pipeline->uses_vrs_attachment = radv_pipeline_uses_vrs_attachment(pCreateInfo, &state); pipeline->base.push_constant_size = pipeline_layout.push_constant_size; pipeline->base.dynamic_offset_count = pipeline_layout.dynamic_offset_count; diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 8d62cb4..ad03861 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -1727,6 +1727,9 @@ struct radv_cmd_state { uint8_t vtx_emit_num; bool uses_drawid; bool uses_baseinstance; + + bool uses_out_of_order_rast; + bool uses_vrs_attachment; }; struct radv_cmd_buffer_upload { @@ -2265,7 +2268,6 @@ struct radv_graphics_pipeline { uint8_t attrib_bindings[MAX_VERTEX_ATTRIBS]; uint32_t attrib_ends[MAX_VERTEX_ATTRIBS]; uint32_t attrib_index_offset[MAX_VERTEX_ATTRIBS]; - uint32_t pa_sc_mode_cntl_1; uint32_t db_render_control; /* Last pre-PS API stage */ @@ -2285,6 +2287,12 @@ struct radv_graphics_pipeline { /* Custom blend mode for internal operations. */ unsigned custom_blend_mode; + /* Whether the pipeline uses out-of-order rasterization. */ + bool uses_out_of_order_rast; + + /* Whether the pipeline uses a VRS attachment. */ + bool uses_vrs_attachment; + /* For graphics pipeline library */ bool retain_shaders; struct { -- 2.7.4