From f829630d2ebbbfceaf6ce54ce8871c77ff9f1834 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Thu, 9 Dec 2021 20:50:38 -0800 Subject: [PATCH] [llvm] Use llvm::count (NFC) --- llvm/lib/CodeGen/PostRASchedulerList.cpp | 5 +--- .../CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp | 5 +--- llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp | 29 ++++++++-------------- llvm/lib/Target/X86/X86ISelLowering.cpp | 10 +++----- 4 files changed, 16 insertions(+), 33 deletions(-) diff --git a/llvm/lib/CodeGen/PostRASchedulerList.cpp b/llvm/lib/CodeGen/PostRASchedulerList.cpp index 954396c8..d7cd0a5 100644 --- a/llvm/lib/CodeGen/PostRASchedulerList.cpp +++ b/llvm/lib/CodeGen/PostRASchedulerList.cpp @@ -657,10 +657,7 @@ void SchedulePostRATDList::ListScheduleTopDown() { #ifndef NDEBUG unsigned ScheduledNodes = VerifyScheduledDAG(/*isBottomUp=*/false); - unsigned Noops = 0; - for (unsigned i = 0, e = Sequence.size(); i != e; ++i) - if (!Sequence[i]) - ++Noops; + unsigned Noops = llvm::count(Sequence, nullptr); assert(Sequence.size() - Noops == ScheduledNodes && "The number of nodes scheduled doesn't match the expected number!"); #endif // NDEBUG diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp index 9dfb391..aec2cf3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -721,10 +721,7 @@ void ScheduleDAGSDNodes::dumpSchedule() const { /// void ScheduleDAGSDNodes::VerifyScheduledSequence(bool isBottomUp) { unsigned ScheduledNodes = ScheduleDAG::VerifyScheduledDAG(isBottomUp); - unsigned Noops = 0; - for (unsigned i = 0, e = Sequence.size(); i != e; ++i) - if (!Sequence[i]) - ++Noops; + unsigned Noops = llvm::count(Sequence, nullptr); assert(Sequence.size() - Noops == ScheduledNodes && "The number of nodes scheduled doesn't match the expected number!"); } diff --git a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp index 3ee5704..6bae556 100644 --- a/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp +++ b/llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp @@ -4428,8 +4428,7 @@ bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, // If exactly one matched, then we treat that as a successful match (and the // instruction will already have been filled in correctly, since the failing // matches won't have modified it). - unsigned NumSuccessfulMatches = - std::count(std::begin(Match), std::end(Match), Match_Success); + unsigned NumSuccessfulMatches = llvm::count(Match, Match_Success); if (NumSuccessfulMatches == 1) { if (!MatchingInlineAsm && validateInstruction(Inst, Operands)) return true; @@ -4477,7 +4476,7 @@ bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, // If all of the instructions reported an invalid mnemonic, then the original // mnemonic was invalid. - if (std::count(std::begin(Match), std::end(Match), Match_MnemonicFail) == 4) { + if (llvm::count(Match, Match_MnemonicFail) == 4) { if (OriginalError == Match_MnemonicFail) return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'", Op.getLocRange(), MatchingInlineAsm); @@ -4506,16 +4505,14 @@ bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, } // If one instruction matched as unsupported, report this as unsupported. - if (std::count(std::begin(Match), std::end(Match), - Match_Unsupported) == 1) { + if (llvm::count(Match, Match_Unsupported) == 1) { return Error(IDLoc, "unsupported instruction", EmptyRange, MatchingInlineAsm); } // If one instruction matched with a missing feature, report this as a // missing feature. - if (std::count(std::begin(Match), std::end(Match), - Match_MissingFeature) == 1) { + if (llvm::count(Match, Match_MissingFeature) == 1) { ErrorInfo = Match_MissingFeature; return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeatures, MatchingInlineAsm); @@ -4523,8 +4520,7 @@ bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode, // If one instruction matched with an invalid operand, report this as an // operand failure. - if (std::count(std::begin(Match), std::end(Match), - Match_InvalidOperand) == 1) { + if (llvm::count(Match, Match_InvalidOperand) == 1) { return Error(IDLoc, "invalid operand for instruction", EmptyRange, MatchingInlineAsm); } @@ -4672,8 +4668,7 @@ bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode, Op.getLocRange(), MatchingInlineAsm); } - unsigned NumSuccessfulMatches = - std::count(std::begin(Match), std::end(Match), Match_Success); + unsigned NumSuccessfulMatches = llvm::count(Match, Match_Success); // If matching was ambiguous and we had size information from the frontend, // try again with that. This handles cases like "movxz eax, m8/m16". @@ -4719,16 +4714,14 @@ bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode, } // If one instruction matched as unsupported, report this as unsupported. - if (std::count(std::begin(Match), std::end(Match), - Match_Unsupported) == 1) { + if (llvm::count(Match, Match_Unsupported) == 1) { return Error(IDLoc, "unsupported instruction", EmptyRange, MatchingInlineAsm); } // If one instruction matched with a missing feature, report this as a // missing feature. - if (std::count(std::begin(Match), std::end(Match), - Match_MissingFeature) == 1) { + if (llvm::count(Match, Match_MissingFeature) == 1) { ErrorInfo = Match_MissingFeature; return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeatures, MatchingInlineAsm); @@ -4736,14 +4729,12 @@ bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode, // If one instruction matched with an invalid operand, report this as an // operand failure. - if (std::count(std::begin(Match), std::end(Match), - Match_InvalidOperand) == 1) { + if (llvm::count(Match, Match_InvalidOperand) == 1) { return Error(IDLoc, "invalid operand for instruction", EmptyRange, MatchingInlineAsm); } - if (std::count(std::begin(Match), std::end(Match), - Match_InvalidImmUnsignedi4) == 1) { + if (llvm::count(Match, Match_InvalidImmUnsignedi4) == 1) { SMLoc ErrorLoc = ((X86Operand &)*Operands[ErrorInfo]).getStartLoc(); if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 0f784e8..1c23f26 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -15192,12 +15192,10 @@ static SDValue lowerV8I16GeneralSingleInputShuffle( // need // to balance this to ensure we don't form a 3-1 shuffle in the other // half. - int NumFlippedAToBInputs = - std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord) + - std::count(AToBInputs.begin(), AToBInputs.end(), 2 * ADWord + 1); - int NumFlippedBToBInputs = - std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord) + - std::count(BToBInputs.begin(), BToBInputs.end(), 2 * BDWord + 1); + int NumFlippedAToBInputs = llvm::count(AToBInputs, 2 * ADWord) + + llvm::count(AToBInputs, 2 * ADWord + 1); + int NumFlippedBToBInputs = llvm::count(BToBInputs, 2 * BDWord) + + llvm::count(BToBInputs, 2 * BDWord + 1); if ((NumFlippedAToBInputs == 1 && (NumFlippedBToBInputs == 0 || NumFlippedBToBInputs == 2)) || (NumFlippedBToBInputs == 1 && -- 2.7.4