From f7cfb2a176208d3b5139a2e792b40edf1adb43b4 Mon Sep 17 00:00:00 2001
From: ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Thu, 5 Apr 2007 23:14:23 +0000
Subject: [PATCH] 64bit MIPS FPUs have 32 registers.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2610 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-mips/cpu.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index 3849e50..4b17929 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -62,9 +62,8 @@ struct CPUMIPSState {
     target_ulong t2;
 #endif
     target_ulong HI, LO;
-    uint32_t DCR; /* ? */
     /* Floating point registers */
-    fpr_t fpr[16];
+    fpr_t fpr[32];
 #define FPR(cpu, n) ((fpr_t*)&(cpu)->fpr[(n) / 2])
 #define FPR_FD(cpu, n) (FPR(cpu, n)->fd)
 #define FPR_FS(cpu, n) (FPR(cpu, n)->fs[((n) & 1) ^ FP_ENDIAN_IDX])
-- 
2.7.4