From f7b9c09c7cd41dc91c5392e467b71216234e342e Mon Sep 17 00:00:00 2001 From: Axel Davy Date: Mon, 25 Feb 2019 21:02:14 +0100 Subject: [PATCH] st/nine: Disable depth write when nothing gets updated MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit I do not see any perf impact on radeonsi, but it seems iris needs this. It seems something sensible to do. Signed-off-by: Axel Davy Reviewed-by: Timur Kristóf Reviewed-by: Kenneth Graunke Tested-by: Andre Heider --- src/gallium/state_trackers/nine/nine_pipe.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/gallium/state_trackers/nine/nine_pipe.c b/src/gallium/state_trackers/nine/nine_pipe.c index a84a17f..b69ddb6 100644 --- a/src/gallium/state_trackers/nine/nine_pipe.c +++ b/src/gallium/state_trackers/nine/nine_pipe.c @@ -36,8 +36,11 @@ nine_convert_dsa_state(struct pipe_depth_stencil_alpha_state *dsa_state, if (rs[D3DRS_ZENABLE]) { dsa.depth.enabled = 1; - dsa.depth.writemask = !!rs[D3DRS_ZWRITEENABLE]; dsa.depth.func = d3dcmpfunc_to_pipe_func(rs[D3DRS_ZFUNC]); + /* Disable depth write if no change can occur */ + dsa.depth.writemask = !!rs[D3DRS_ZWRITEENABLE] && + dsa.depth.func != PIPE_FUNC_EQUAL && + dsa.depth.func != PIPE_FUNC_NEVER; } if (rs[D3DRS_STENCILENABLE]) { -- 2.7.4