From f799e3f9441c2a348af0357a61020cc1e397e66b Mon Sep 17 00:00:00 2001
From: Stephen Lin <stephenwlin@gmail.com>
Date: Sat, 13 Jul 2013 20:38:47 +0000
Subject: [PATCH] Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for
 easier debugging. No functionality change and all tests pass after
 conversion.

This was done with the following sed invocation to catch label lines demarking function boundaries:
    sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll
which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct.

llvm-svn: 186258
---
 llvm/test/CodeGen/AArch64/adc.ll                   |   8 +-
 llvm/test/CodeGen/AArch64/addsub-shifted.ll        |  10 +-
 llvm/test/CodeGen/AArch64/addsub.ll                |   2 +-
 llvm/test/CodeGen/AArch64/addsub_ext.ll            |   2 +-
 llvm/test/CodeGen/AArch64/alloca.ll                |   8 +-
 llvm/test/CodeGen/AArch64/analyze-branch.ll        |  20 +-
 llvm/test/CodeGen/AArch64/atomic-ops.ll            | 116 +++----
 llvm/test/CodeGen/AArch64/basic-pic.ll             |   2 +-
 llvm/test/CodeGen/AArch64/bitfield-insert-0.ll     |   2 +-
 llvm/test/CodeGen/AArch64/bitfield-insert.ll       |  18 +-
 llvm/test/CodeGen/AArch64/bitfield.ll              |  22 +-
 llvm/test/CodeGen/AArch64/blockaddress.ll          |   2 +-
 llvm/test/CodeGen/AArch64/compare-branch.ll        |   2 +-
 llvm/test/CodeGen/AArch64/cond-sel.ll              |  14 +-
 llvm/test/CodeGen/AArch64/directcond.ll            |  10 +-
 llvm/test/CodeGen/AArch64/dp-3source.ll            |  36 +-
 llvm/test/CodeGen/AArch64/dp2.ll                   |   6 +-
 llvm/test/CodeGen/AArch64/extern-weak.ll           |   2 +-
 llvm/test/CodeGen/AArch64/fcmp.ll                  |   4 +-
 llvm/test/CodeGen/AArch64/fcvt-fixed.ll            |   8 +-
 llvm/test/CodeGen/AArch64/fcvt-int.ll              |  24 +-
 llvm/test/CodeGen/AArch64/flags-multiuse.ll        |   2 +-
 llvm/test/CodeGen/AArch64/floatdp_2source.ll       |   4 +-
 llvm/test/CodeGen/AArch64/fp-cond-sel.ll           |   2 +-
 llvm/test/CodeGen/AArch64/fp-dp3.ll                |   8 +-
 llvm/test/CodeGen/AArch64/fp128-folding.ll         |   4 +-
 llvm/test/CodeGen/AArch64/fp128.ll                 |  30 +-
 llvm/test/CodeGen/AArch64/func-argpassing.ll       |   2 +-
 llvm/test/CodeGen/AArch64/global-alignment.ll      |  10 +-
 llvm/test/CodeGen/AArch64/i128-align.ll            |   2 +-
 llvm/test/CodeGen/AArch64/init-array.ll            |   2 +-
 .../CodeGen/AArch64/inline-asm-constraints-badI.ll |   2 +-
 .../CodeGen/AArch64/inline-asm-constraints-badK.ll |   2 +-
 .../AArch64/inline-asm-constraints-badK2.ll        |   2 +-
 .../CodeGen/AArch64/inline-asm-constraints-badL.ll |   2 +-
 .../test/CodeGen/AArch64/inline-asm-constraints.ll |  26 +-
 llvm/test/CodeGen/AArch64/inline-asm-modifiers.ll  |  14 +-
 llvm/test/CodeGen/AArch64/large-frame.ll           |   6 +-
 llvm/test/CodeGen/AArch64/logical-imm.ll           |   8 +-
 llvm/test/CodeGen/AArch64/movw-consts.ll           |  36 +-
 llvm/test/CodeGen/AArch64/pic-eh-stubs.ll          |   2 +-
 .../CodeGen/AArch64/regress-bitcast-formals.ll     |   2 +-
 llvm/test/CodeGen/AArch64/regress-tail-livereg.ll  |   2 +-
 llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll |   2 +-
 .../AArch64/regress-w29-reserved-with-fp.ll        |   2 +-
 llvm/test/CodeGen/AArch64/setcc-takes-i32.ll       |   4 +-
 llvm/test/CodeGen/AArch64/sincos-expansion.ll      |   2 +-
 llvm/test/CodeGen/AArch64/tls-dynamic-together.ll  |   2 +-
 llvm/test/CodeGen/AArch64/tls-dynamics.ll          |  10 +-
 llvm/test/CodeGen/AArch64/tls-execs.ll             |   8 +-
 llvm/test/CodeGen/AArch64/tst-br.ll                |   2 +-
 llvm/test/CodeGen/AArch64/variadic.ll              |  12 +-
 llvm/test/CodeGen/AArch64/zero-reg.ll              |   6 +-
 llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll     |   2 +-
 .../ARM/2011-11-07-PromoteVectorLoadStore.ll       |   4 +-
 .../CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll  |   2 +-
 .../CodeGen/ARM/2011-11-29-128bitArithmetics.ll    |  22 +-
 llvm/test/CodeGen/ARM/2012-08-09-neon-extload.ll   |  12 +-
 .../CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll   |   4 +-
 .../CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll  |   2 +-
 llvm/test/CodeGen/ARM/atomic-64bit.ll              |  26 +-
 llvm/test/CodeGen/ARM/crash-shufflevector.ll       |   2 +-
 llvm/test/CodeGen/ARM/dagcombine-concatvector.ll   |   2 +-
 llvm/test/CodeGen/ARM/domain-conv-vmovs.ll         |  14 +-
 llvm/test/CodeGen/ARM/fabs-neon.ll                 |   4 +-
 llvm/test/CodeGen/ARM/fabss.ll                     |  10 +-
 llvm/test/CodeGen/ARM/fadds.ll                     |  12 +-
 llvm/test/CodeGen/ARM/fast-isel.ll                 |  12 +-
 llvm/test/CodeGen/ARM/fcopysign.ll                 |  12 +-
 llvm/test/CodeGen/ARM/fdivs.ll                     |  10 +-
 llvm/test/CodeGen/ARM/fmuls.ll                     |  12 +-
 llvm/test/CodeGen/ARM/fnegs.ll                     |  24 +-
 llvm/test/CodeGen/ARM/fp_convert.ll                |  16 +-
 llvm/test/CodeGen/ARM/ldr_post.ll                  |   4 +-
 llvm/test/CodeGen/ARM/ldr_pre.ll                   |   4 +-
 llvm/test/CodeGen/ARM/neon_vabs.ll                 |  20 +-
 llvm/test/CodeGen/ARM/pack.ll                      |   4 +-
 llvm/test/CodeGen/ARM/rev.ll                       |   4 +-
 llvm/test/CodeGen/ARM/shifter_operand.ll           |  16 +-
 llvm/test/CodeGen/ARM/str_post.ll                  |   4 +-
 llvm/test/CodeGen/ARM/swift-atomics.ll             |   6 +-
 llvm/test/CodeGen/ARM/thumb1-varalloc.ll           |   2 +-
 llvm/test/CodeGen/ARM/va_arg.ll                    |   4 +-
 llvm/test/CodeGen/ARM/vbsl.ll                      |   8 +-
 llvm/test/CodeGen/ARM/vext.ll                      |  36 +-
 llvm/test/CodeGen/ARM/vfp.ll                       |  24 +-
 llvm/test/CodeGen/ARM/vget_lane.ll                 |   2 +-
 llvm/test/CodeGen/ARM/vmul.ll                      |  12 +-
 llvm/test/CodeGen/ARM/vrev.ll                      |  36 +-
 llvm/test/CodeGen/Hexagon/adde.ll                  |   2 +-
 llvm/test/CodeGen/Hexagon/i16_VarArg.ll            |   2 +-
 llvm/test/CodeGen/Hexagon/i1_VarArg.ll             |   2 +-
 llvm/test/CodeGen/Hexagon/i8_VarArg.ll             |   2 +-
 llvm/test/CodeGen/Hexagon/indirect-br.ll           |   2 +-
 llvm/test/CodeGen/Hexagon/sube.ll                  |   2 +-
 llvm/test/CodeGen/Hexagon/zextloadi1.ll            |   2 +-
 llvm/test/CodeGen/MSP430/jumptable.ll              |   2 +-
 llvm/test/CodeGen/Mips/align16.ll                  |   2 +-
 llvm/test/CodeGen/Mips/blez_bgez.ll                |   4 +-
 llvm/test/CodeGen/Mips/dsp-patterns.ll             |  30 +-
 llvm/test/CodeGen/Mips/int-to-float-conversion.ll  |  10 +-
 llvm/test/CodeGen/Mips/optimize-fp-math.ll         |   8 +-
 llvm/test/CodeGen/Mips/selnek.ll                   |   2 +-
 llvm/test/CodeGen/NVPTX/ctpop.ll                   |   2 +-
 llvm/test/CodeGen/NVPTX/i8-param.ll                |   2 +-
 llvm/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll     |   2 +-
 llvm/test/CodeGen/NVPTX/rsqrt.ll                   |   2 +-
 llvm/test/CodeGen/NVPTX/sext-in-reg.ll             |   2 +-
 .../PowerPC/2011-12-08-DemandedBitsMiscompile.ll   |   2 +-
 llvm/test/CodeGen/PowerPC/fma.ll                   |  16 +-
 llvm/test/CodeGen/PowerPC/mcm-1.ll                 |   2 +-
 llvm/test/CodeGen/PowerPC/mcm-10.ll                |   2 +-
 llvm/test/CodeGen/PowerPC/mcm-11.ll                |   2 +-
 llvm/test/CodeGen/PowerPC/mcm-12.ll                |   2 +-
 llvm/test/CodeGen/PowerPC/mcm-2.ll                 |   4 +-
 llvm/test/CodeGen/PowerPC/mcm-3.ll                 |   4 +-
 llvm/test/CodeGen/PowerPC/mcm-4.ll                 |   4 +-
 llvm/test/CodeGen/PowerPC/mcm-5.ll                 |   2 +-
 llvm/test/CodeGen/PowerPC/mcm-6.ll                 |   2 +-
 llvm/test/CodeGen/PowerPC/mcm-7.ll                 |   2 +-
 llvm/test/CodeGen/PowerPC/mcm-8.ll                 |   2 +-
 llvm/test/CodeGen/PowerPC/mcm-9.ll                 |   2 +-
 llvm/test/CodeGen/PowerPC/mcm-default.ll           |   2 +-
 .../CodeGen/PowerPC/misched-inorder-latency.ll     |   4 +-
 llvm/test/CodeGen/PowerPC/ppc64-calls.ll           |  10 +-
 llvm/test/CodeGen/PowerPC/rounding-ops.ll          |  20 +-
 llvm/test/CodeGen/PowerPC/vaddsplat.ll             |  24 +-
 llvm/test/CodeGen/PowerPC/varargs.ll               |   4 +-
 llvm/test/CodeGen/PowerPC/vec_constants.ll         |  16 +-
 llvm/test/CodeGen/PowerPC/vec_mul.ll               |   8 +-
 llvm/test/CodeGen/SPARC/basictest.ll               |   6 +-
 llvm/test/CodeGen/SPARC/float.ll                   |   8 +-
 llvm/test/CodeGen/Thumb/ispositive.ll              |   2 +-
 llvm/test/CodeGen/Thumb/large-stack.ll             |   6 +-
 llvm/test/CodeGen/Thumb/rev.ll                     |   4 +-
 llvm/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll   |   4 +-
 .../2013-03-06-vector-sext-operand-scalarize.ll    |   4 +-
 llvm/test/CodeGen/Thumb2/large-stack.ll            |  12 +-
 llvm/test/CodeGen/Thumb2/thumb2-pack.ll            |   2 +-
 llvm/test/CodeGen/Thumb2/thumb2-str_post.ll        |   4 +-
 llvm/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll         |   8 +-
 llvm/test/CodeGen/X86/2007-02-04-OrAddrMode.ll     |   4 +-
 .../X86/2007-02-23-DAGCombine-Miscompile.ll        |   2 +-
 .../CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll |   2 +-
 .../CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll     |   2 +-
 .../2011-12-26-extractelement-duplicate-load.ll    |   2 +-
 llvm/test/CodeGen/X86/3addr-or.ll                  |  10 +-
 llvm/test/CodeGen/X86/add-of-carry.ll              |   6 +-
 llvm/test/CodeGen/X86/add.ll                       |  22 +-
 llvm/test/CodeGen/X86/asm-modifier.ll              |   8 +-
 llvm/test/CodeGen/X86/atom-lea-sp.ll               |  12 +-
 llvm/test/CodeGen/X86/avx-brcond.ll                |  12 +-
 llvm/test/CodeGen/X86/avx-fp2int.ll                |   4 +-
 llvm/test/CodeGen/X86/avx-shuffle.ll               |   8 +-
 llvm/test/CodeGen/X86/avx-varargs-x86_64.ll        |   2 +-
 llvm/test/CodeGen/X86/avx2-arith.ll                |   2 +-
 llvm/test/CodeGen/X86/avx2-palignr.ll              |  16 +-
 llvm/test/CodeGen/X86/avx2-vector-shifts.ll        |  48 +--
 llvm/test/CodeGen/X86/block-placement.ll           |  16 +-
 llvm/test/CodeGen/X86/brcond.ll                    |  18 +-
 llvm/test/CodeGen/X86/btq.ll                       |   4 +-
 llvm/test/CodeGen/X86/cmov-fp.ll                   | 192 +++++------
 llvm/test/CodeGen/X86/cmov-into-branch.ll          |  10 +-
 llvm/test/CodeGen/X86/cmov.ll                      |  14 +-
 llvm/test/CodeGen/X86/cmp.ll                       |  24 +-
 llvm/test/CodeGen/X86/conditional-indecrement.ll   |  16 +-
 llvm/test/CodeGen/X86/critical-edge-split-2.ll     |   2 +-
 llvm/test/CodeGen/X86/ctpop-combine.ll             |   6 +-
 llvm/test/CodeGen/X86/dag-rauw-cse.ll              |   2 +-
 llvm/test/CodeGen/X86/dagcombine-buildvector.ll    |   4 +-
 llvm/test/CodeGen/X86/dbg-value-terminator.ll      |   2 +-
 llvm/test/CodeGen/X86/divide-by-constant.ll        |  18 +-
 llvm/test/CodeGen/X86/fabs.ll                      |  18 +-
 llvm/test/CodeGen/X86/fast-isel-call.ll            |   8 +-
 llvm/test/CodeGen/X86/fast-isel-divrem-x86-64.ll   |   8 +-
 llvm/test/CodeGen/X86/fast-isel-divrem.ll          |  24 +-
 llvm/test/CodeGen/X86/fast-isel-extract.ll         |   4 +-
 llvm/test/CodeGen/X86/fast-isel-gep.ll             |  20 +-
 llvm/test/CodeGen/X86/fast-isel-i1.ll              |   4 +-
 llvm/test/CodeGen/X86/fast-isel-x86-64.ll          |  46 +--
 llvm/test/CodeGen/X86/fast-isel-x86.ll             |  10 +-
 llvm/test/CodeGen/X86/fold-load.ll                 |   4 +-
 llvm/test/CodeGen/X86/iabs.ll                      |   2 +-
 llvm/test/CodeGen/X86/isel-sink.ll                 |   2 +-
 llvm/test/CodeGen/X86/jump_sign.ll                 |   2 +-
 llvm/test/CodeGen/X86/lea.ll                       |   4 +-
 llvm/test/CodeGen/X86/legalize-shift-64.ll         |   8 +-
 llvm/test/CodeGen/X86/longlong-deadload.ll         |   2 +-
 llvm/test/CodeGen/X86/lsr-reuse.ll                 |   2 +-
 llvm/test/CodeGen/X86/memcpy.ll                    |  12 +-
 .../CodeGen/X86/memset-sse-stack-realignment.ll    |  20 +-
 llvm/test/CodeGen/X86/movbe.ll                     |   8 +-
 llvm/test/CodeGen/X86/movgs.ll                     |  10 +-
 llvm/test/CodeGen/X86/narrow-shl-cst.ll            |  22 +-
 llvm/test/CodeGen/X86/narrow-shl-load.ll           |   2 +-
 llvm/test/CodeGen/X86/no-cmov.ll                   |   2 +-
 llvm/test/CodeGen/X86/or-address.ll                |   2 +-
 llvm/test/CodeGen/X86/palignr.ll                   |  18 +-
 llvm/test/CodeGen/X86/peep-setb.ll                 |  18 +-
 llvm/test/CodeGen/X86/peep-test-3.ll               |   2 +-
 llvm/test/CodeGen/X86/pic.ll                       |  16 +-
 llvm/test/CodeGen/X86/pmovsx-inreg.ll              |  48 +--
 llvm/test/CodeGen/X86/pmulld.ll                    |   8 +-
 llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll          |   2 +-
 llvm/test/CodeGen/X86/reverse_branches.ll          |   2 +-
 llvm/test/CodeGen/X86/sdiv-exact.ll                |   4 +-
 llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll  |   4 +-
 llvm/test/CodeGen/X86/select.ll                    |  84 ++---
 llvm/test/CodeGen/X86/select_const.ll              |   2 +-
 llvm/test/CodeGen/X86/sext-load.ll                 |   4 +-
 llvm/test/CodeGen/X86/shift-combine.ll             |   2 +-
 llvm/test/CodeGen/X86/shift-folding.ll             |  10 +-
 llvm/test/CodeGen/X86/shrink-compare.ll            |   8 +-
 llvm/test/CodeGen/X86/sibcall-6.ll                 |   2 +-
 llvm/test/CodeGen/X86/sincos-opt.ll                |  10 +-
 llvm/test/CodeGen/X86/sincos.ll                    |  10 +-
 llvm/test/CodeGen/X86/smul-with-overflow.ll        |  10 +-
 llvm/test/CodeGen/X86/sse1.ll                      |   2 +-
 llvm/test/CodeGen/X86/sse2-mul.ll                  |   2 +-
 llvm/test/CodeGen/X86/sse2-vector-shifts.ll        |  48 +--
 llvm/test/CodeGen/X86/sse2.ll                      |  26 +-
 llvm/test/CodeGen/X86/sse4a.ll                     |  12 +-
 llvm/test/CodeGen/X86/stack-align-memcpy.ll        |   2 +-
 llvm/test/CodeGen/X86/stack-align.ll               |   2 +-
 llvm/test/CodeGen/X86/store-narrow.ll              |  34 +-
 llvm/test/CodeGen/X86/store_op_load_fold.ll        |   2 +-
 llvm/test/CodeGen/X86/sub.ll                       |   2 +-
 llvm/test/CodeGen/X86/switch-bt.ll                 |   4 +-
 llvm/test/CodeGen/X86/switch-order-weight.ll       |   2 +-
 llvm/test/CodeGen/X86/tail-call-got.ll             |   4 +-
 llvm/test/CodeGen/X86/tailcall-disable.ll          |   8 +-
 llvm/test/CodeGen/X86/testl-commute.ll             |   6 +-
 llvm/test/CodeGen/X86/tlv-1.ll                     |   2 +-
 llvm/test/CodeGen/X86/trap.ll                      |   4 +-
 llvm/test/CodeGen/X86/trunc-to-bool.ll             |  10 +-
 llvm/test/CodeGen/X86/twoaddr-lea.ll               |   6 +-
 llvm/test/CodeGen/X86/umul-with-overflow.ll        |   4 +-
 llvm/test/CodeGen/X86/use-add-flags.ll             |   6 +-
 llvm/test/CodeGen/X86/v2f32.ll                     |  30 +-
 llvm/test/CodeGen/X86/vec_compare-sse4.ll          |  12 +-
 llvm/test/CodeGen/X86/vec_compare.ll               |  28 +-
 llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll         |   2 +-
 llvm/test/CodeGen/X86/vec_splat-2.ll               |   2 +-
 llvm/test/CodeGen/X86/vec_splat.ll                 |   8 +-
 llvm/test/CodeGen/X86/vec_ss_load_fold.ll          |  10 +-
 llvm/test/CodeGen/X86/vec_uint_to_fp.ll            |   2 +-
 llvm/test/CodeGen/X86/viabs.ll                     |  50 +--
 llvm/test/CodeGen/X86/vselect-minmax.ll            | 384 ++++++++++-----------
 llvm/test/CodeGen/X86/x86-64-and-mask.ll           |   2 +-
 llvm/test/CodeGen/X86/x86-64-psub.ll               |  14 +-
 llvm/test/CodeGen/X86/xor.ll                       |  36 +-
 llvm/test/CodeGen/XCore/fneg.ll                    |   2 +-
 llvm/test/CodeGen/XCore/getid.ll                   |   2 +-
 llvm/test/CodeGen/XCore/resources.ll               |   4 +-
 llvm/test/CodeGen/XCore/trap.ll                    |   2 +-
 255 files changed, 1492 insertions(+), 1492 deletions(-)

diff --git a/llvm/test/CodeGen/AArch64/adc.ll b/llvm/test/CodeGen/AArch64/adc.ll
index 7cb3732..26fd3e6 100644
--- a/llvm/test/CodeGen/AArch64/adc.ll
+++ b/llvm/test/CodeGen/AArch64/adc.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
 
 define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
-; CHECK: test_simple:
+; CHECK-LABEL: test_simple:
 
   %valadd = add i128 %a, %b
 ; CHECK: adds [[ADDLO:x[0-9]+]], x0, x2
@@ -16,7 +16,7 @@ define i128 @test_simple(i128 %a, i128 %b, i128 %c) {
 }
 
 define i128 @test_imm(i128 %a) {
-; CHECK: test_imm:
+; CHECK-LABEL: test_imm:
 
   %val = add i128 %a, 12
 ; CHECK: adds x0, x0, #12
@@ -27,7 +27,7 @@ define i128 @test_imm(i128 %a) {
 }
 
 define i128 @test_shifted(i128 %a, i128 %b) {
-; CHECK: test_shifted:
+; CHECK-LABEL: test_shifted:
 
   %rhs = shl i128 %b, 45
 
@@ -40,7 +40,7 @@ define i128 @test_shifted(i128 %a, i128 %b) {
 }
 
 define i128 @test_extended(i128 %a, i16 %b) {
-; CHECK: test_extended:
+; CHECK-LABEL: test_extended:
 
   %ext = sext i16 %b to i128
   %rhs = shl i128 %ext, 3
diff --git a/llvm/test/CodeGen/AArch64/addsub-shifted.ll b/llvm/test/CodeGen/AArch64/addsub-shifted.ll
index f2c74f6..269c1e8 100644
--- a/llvm/test/CodeGen/AArch64/addsub-shifted.ll
+++ b/llvm/test/CodeGen/AArch64/addsub-shifted.ll
@@ -4,7 +4,7 @@
 @var64 = global i64 0
 
 define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
-; CHECK: test_lsl_arith:
+; CHECK-LABEL: test_lsl_arith:
 
   %rhs1 = load volatile i32* @var32
   %shift1 = shl i32 %rhs1, 18
@@ -73,7 +73,7 @@ define void @test_lsl_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
 }
 
 define void @test_lsr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
-; CHECK: test_lsr_arith:
+; CHECK-LABEL: test_lsr_arith:
 
   %shift1 = lshr i32 %rhs32, 18
   %val1 = add i32 %lhs32, %shift1
@@ -132,7 +132,7 @@ define void @test_lsr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
 }
 
 define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
-; CHECK: test_asr_arith:
+; CHECK-LABEL: test_asr_arith:
 
   %shift1 = ashr i32 %rhs32, 18
   %val1 = add i32 %lhs32, %shift1
@@ -191,7 +191,7 @@ define void @test_asr_arith(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
 }
 
 define i32 @test_cmp(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
-; CHECK: test_cmp:
+; CHECK-LABEL: test_cmp:
 
   %shift1 = shl i32 %rhs32, 13
   %tst1 = icmp uge i32 %lhs32, %shift1
@@ -237,7 +237,7 @@ end:
 }
 
 define i32 @test_cmn(i32 %lhs32, i32 %rhs32, i64 %lhs64, i64 %rhs64) {
-; CHECK: test_cmn:
+; CHECK-LABEL: test_cmn:
 
   %shift1 = shl i32 %rhs32, 13
   %val1 = sub i32 0, %shift1
diff --git a/llvm/test/CodeGen/AArch64/addsub.ll b/llvm/test/CodeGen/AArch64/addsub.ll
index 5148807..c0e1cc9 100644
--- a/llvm/test/CodeGen/AArch64/addsub.ll
+++ b/llvm/test/CodeGen/AArch64/addsub.ll
@@ -76,7 +76,7 @@ define void @sub_med() {
 }
 
 define void @testing() {
-; CHECK: testing:
+; CHECK-LABEL: testing:
   %val = load i32* @var_i32
 
 ; CHECK: cmp {{w[0-9]+}}, #4095
diff --git a/llvm/test/CodeGen/AArch64/addsub_ext.ll b/llvm/test/CodeGen/AArch64/addsub_ext.ll
index 2dd1662..0bda0f9 100644
--- a/llvm/test/CodeGen/AArch64/addsub_ext.ll
+++ b/llvm/test/CodeGen/AArch64/addsub_ext.ll
@@ -186,4 +186,4 @@ define void @addsub_i32rhs() {
 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw #2
 
     ret void
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AArch64/alloca.ll b/llvm/test/CodeGen/AArch64/alloca.ll
index c62edf6..a84217f 100644
--- a/llvm/test/CodeGen/AArch64/alloca.ll
+++ b/llvm/test/CodeGen/AArch64/alloca.ll
@@ -3,7 +3,7 @@
 declare void @use_addr(i8*)
 
 define void @test_simple_alloca(i64 %n) {
-; CHECK: test_simple_alloca:
+; CHECK-LABEL: test_simple_alloca:
 
   %buf = alloca i8, i64 %n
   ; Make sure we align the stack change to 16 bytes:
@@ -30,7 +30,7 @@ define void @test_simple_alloca(i64 %n) {
 declare void @use_addr_loc(i8*, i64*)
 
 define i64 @test_alloca_with_local(i64 %n) {
-; CHECK: test_alloca_with_local:
+; CHECK-LABEL: test_alloca_with_local:
 ; CHECK: sub sp, sp, #32
 ; CHECK: stp x29, x30, [sp, #16]
 
@@ -66,7 +66,7 @@ define i64 @test_alloca_with_local(i64 %n) {
 }
 
 define void @test_variadic_alloca(i64 %n, ...) {
-; CHECK: test_variadic_alloca:
+; CHECK-LABEL: test_variadic_alloca:
 
 ; CHECK: sub     sp, sp, #208
 ; CHECK: stp     x29, x30, [sp, #192]
@@ -89,7 +89,7 @@ define void @test_variadic_alloca(i64 %n, ...) {
 }
 
 define void @test_alloca_large_frame(i64 %n) {
-; CHECK: test_alloca_large_frame:
+; CHECK-LABEL: test_alloca_large_frame:
 
 ; CHECK: sub sp, sp, #496
 ; CHECK: stp x29, x30, [sp, #480]
diff --git a/llvm/test/CodeGen/AArch64/analyze-branch.ll b/llvm/test/CodeGen/AArch64/analyze-branch.ll
index e10bbb0..36bc2e0 100644
--- a/llvm/test/CodeGen/AArch64/analyze-branch.ll
+++ b/llvm/test/CodeGen/AArch64/analyze-branch.ll
@@ -11,7 +11,7 @@ declare void @test_false()
 !1 = metadata !{metadata !"branch_weights", i32 4, i32 64}
 
 define void @test_Bcc_fallthrough_taken(i32 %in) nounwind {
-; CHECK: test_Bcc_fallthrough_taken:
+; CHECK-LABEL: test_Bcc_fallthrough_taken:
   %tst = icmp eq i32 %in, 42
   br i1 %tst, label %true, label %false, !prof !0
 
@@ -34,7 +34,7 @@ false:
 }
 
 define void @test_Bcc_fallthrough_nottaken(i32 %in) nounwind {
-; CHECK: test_Bcc_fallthrough_nottaken:
+; CHECK-LABEL: test_Bcc_fallthrough_nottaken:
   %tst = icmp eq i32 %in, 42
   br i1 %tst, label %true, label %false, !prof !1
 
@@ -57,7 +57,7 @@ false:
 }
 
 define void @test_CBZ_fallthrough_taken(i32 %in) nounwind {
-; CHECK: test_CBZ_fallthrough_taken:
+; CHECK-LABEL: test_CBZ_fallthrough_taken:
   %tst = icmp eq i32 %in, 0
   br i1 %tst, label %true, label %false, !prof !0
 
@@ -78,7 +78,7 @@ false:
 }
 
 define void @test_CBZ_fallthrough_nottaken(i64 %in) nounwind {
-; CHECK: test_CBZ_fallthrough_nottaken:
+; CHECK-LABEL: test_CBZ_fallthrough_nottaken:
   %tst = icmp eq i64 %in, 0
   br i1 %tst, label %true, label %false, !prof !1
 
@@ -99,7 +99,7 @@ false:
 }
 
 define void @test_CBNZ_fallthrough_taken(i32 %in) nounwind {
-; CHECK: test_CBNZ_fallthrough_taken:
+; CHECK-LABEL: test_CBNZ_fallthrough_taken:
   %tst = icmp ne i32 %in, 0
   br i1 %tst, label %true, label %false, !prof !0
 
@@ -120,7 +120,7 @@ false:
 }
 
 define void @test_CBNZ_fallthrough_nottaken(i64 %in) nounwind {
-; CHECK: test_CBNZ_fallthrough_nottaken:
+; CHECK-LABEL: test_CBNZ_fallthrough_nottaken:
   %tst = icmp ne i64 %in, 0
   br i1 %tst, label %true, label %false, !prof !1
 
@@ -141,7 +141,7 @@ false:
 }
 
 define void @test_TBZ_fallthrough_taken(i32 %in) nounwind {
-; CHECK: test_TBZ_fallthrough_taken:
+; CHECK-LABEL: test_TBZ_fallthrough_taken:
   %bit = and i32 %in, 32768
   %tst = icmp eq i32 %bit, 0
   br i1 %tst, label %true, label %false, !prof !0
@@ -163,7 +163,7 @@ false:
 }
 
 define void @test_TBZ_fallthrough_nottaken(i64 %in) nounwind {
-; CHECK: test_TBZ_fallthrough_nottaken:
+; CHECK-LABEL: test_TBZ_fallthrough_nottaken:
   %bit = and i64 %in, 32768
   %tst = icmp eq i64 %bit, 0
   br i1 %tst, label %true, label %false, !prof !1
@@ -186,7 +186,7 @@ false:
 
 
 define void @test_TBNZ_fallthrough_taken(i32 %in) nounwind {
-; CHECK: test_TBNZ_fallthrough_taken:
+; CHECK-LABEL: test_TBNZ_fallthrough_taken:
   %bit = and i32 %in, 32768
   %tst = icmp ne i32 %bit, 0
   br i1 %tst, label %true, label %false, !prof !0
@@ -208,7 +208,7 @@ false:
 }
 
 define void @test_TBNZ_fallthrough_nottaken(i64 %in) nounwind {
-; CHECK: test_TBNZ_fallthrough_nottaken:
+; CHECK-LABEL: test_TBNZ_fallthrough_nottaken:
   %bit = and i64 %in, 32768
   %tst = icmp ne i64 %bit, 0
   br i1 %tst, label %true, label %false, !prof !1
diff --git a/llvm/test/CodeGen/AArch64/atomic-ops.ll b/llvm/test/CodeGen/AArch64/atomic-ops.ll
index 5e87f21..de84ff4 100644
--- a/llvm/test/CodeGen/AArch64/atomic-ops.ll
+++ b/llvm/test/CodeGen/AArch64/atomic-ops.ll
@@ -6,7 +6,7 @@
 @var64 = global i64 0
 
 define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_add_i8:
+; CHECK-LABEL: test_atomic_load_add_i8:
    %old = atomicrmw add i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -26,7 +26,7 @@ define i8 @test_atomic_load_add_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_add_i16:
+; CHECK-LABEL: test_atomic_load_add_i16:
    %old = atomicrmw add i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -46,7 +46,7 @@ define i16 @test_atomic_load_add_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_add_i32:
+; CHECK-LABEL: test_atomic_load_add_i32:
    %old = atomicrmw add i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -66,7 +66,7 @@ define i32 @test_atomic_load_add_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_add_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_add_i64:
+; CHECK-LABEL: test_atomic_load_add_i64:
    %old = atomicrmw add i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -86,7 +86,7 @@ define i64 @test_atomic_load_add_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_sub_i8:
+; CHECK-LABEL: test_atomic_load_sub_i8:
    %old = atomicrmw sub i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -106,7 +106,7 @@ define i8 @test_atomic_load_sub_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_sub_i16:
+; CHECK-LABEL: test_atomic_load_sub_i16:
    %old = atomicrmw sub i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -126,7 +126,7 @@ define i16 @test_atomic_load_sub_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_sub_i32:
+; CHECK-LABEL: test_atomic_load_sub_i32:
    %old = atomicrmw sub i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -146,7 +146,7 @@ define i32 @test_atomic_load_sub_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_sub_i64:
+; CHECK-LABEL: test_atomic_load_sub_i64:
    %old = atomicrmw sub i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -166,7 +166,7 @@ define i64 @test_atomic_load_sub_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_and_i8:
+; CHECK-LABEL: test_atomic_load_and_i8:
    %old = atomicrmw and i8* @var8, i8 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -186,7 +186,7 @@ define i8 @test_atomic_load_and_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_and_i16:
+; CHECK-LABEL: test_atomic_load_and_i16:
    %old = atomicrmw and i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -206,7 +206,7 @@ define i16 @test_atomic_load_and_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_and_i32:
+; CHECK-LABEL: test_atomic_load_and_i32:
    %old = atomicrmw and i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -226,7 +226,7 @@ define i32 @test_atomic_load_and_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_and_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_and_i64:
+; CHECK-LABEL: test_atomic_load_and_i64:
    %old = atomicrmw and i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -246,7 +246,7 @@ define i64 @test_atomic_load_and_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_or_i8:
+; CHECK-LABEL: test_atomic_load_or_i8:
    %old = atomicrmw or i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -266,7 +266,7 @@ define i8 @test_atomic_load_or_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_or_i16:
+; CHECK-LABEL: test_atomic_load_or_i16:
    %old = atomicrmw or i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -286,7 +286,7 @@ define i16 @test_atomic_load_or_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_or_i32:
+; CHECK-LABEL: test_atomic_load_or_i32:
    %old = atomicrmw or i32* @var32, i32 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -306,7 +306,7 @@ define i32 @test_atomic_load_or_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_or_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_or_i64:
+; CHECK-LABEL: test_atomic_load_or_i64:
    %old = atomicrmw or i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -326,7 +326,7 @@ define i64 @test_atomic_load_or_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_xor_i8:
+; CHECK-LABEL: test_atomic_load_xor_i8:
    %old = atomicrmw xor i8* @var8, i8 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -346,7 +346,7 @@ define i8 @test_atomic_load_xor_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_xor_i16:
+; CHECK-LABEL: test_atomic_load_xor_i16:
    %old = atomicrmw xor i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -366,7 +366,7 @@ define i16 @test_atomic_load_xor_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_xor_i32:
+; CHECK-LABEL: test_atomic_load_xor_i32:
    %old = atomicrmw xor i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -386,7 +386,7 @@ define i32 @test_atomic_load_xor_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_xor_i64:
+; CHECK-LABEL: test_atomic_load_xor_i64:
    %old = atomicrmw xor i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -406,7 +406,7 @@ define i64 @test_atomic_load_xor_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_xchg_i8:
+; CHECK-LABEL: test_atomic_load_xchg_i8:
    %old = atomicrmw xchg i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -425,7 +425,7 @@ define i8 @test_atomic_load_xchg_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_xchg_i16:
+; CHECK-LABEL: test_atomic_load_xchg_i16:
    %old = atomicrmw xchg i16* @var16, i16 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -444,7 +444,7 @@ define i16 @test_atomic_load_xchg_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_xchg_i32:
+; CHECK-LABEL: test_atomic_load_xchg_i32:
    %old = atomicrmw xchg i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -463,7 +463,7 @@ define i32 @test_atomic_load_xchg_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_xchg_i64:
+; CHECK-LABEL: test_atomic_load_xchg_i64:
    %old = atomicrmw xchg i64* @var64, i64 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -483,7 +483,7 @@ define i64 @test_atomic_load_xchg_i64(i64 %offset) nounwind {
 
 
 define i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_min_i8:
+; CHECK-LABEL: test_atomic_load_min_i8:
    %old = atomicrmw min i8* @var8, i8 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -504,7 +504,7 @@ define i8 @test_atomic_load_min_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_min_i16:
+; CHECK-LABEL: test_atomic_load_min_i16:
    %old = atomicrmw min i16* @var16, i16 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -525,7 +525,7 @@ define i16 @test_atomic_load_min_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_min_i32:
+; CHECK-LABEL: test_atomic_load_min_i32:
    %old = atomicrmw min i32* @var32, i32 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -546,7 +546,7 @@ define i32 @test_atomic_load_min_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_min_i64:
+; CHECK-LABEL: test_atomic_load_min_i64:
    %old = atomicrmw min i64* @var64, i64 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -567,7 +567,7 @@ define i64 @test_atomic_load_min_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_max_i8:
+; CHECK-LABEL: test_atomic_load_max_i8:
    %old = atomicrmw max i8* @var8, i8 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -588,7 +588,7 @@ define i8 @test_atomic_load_max_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_max_i16:
+; CHECK-LABEL: test_atomic_load_max_i16:
    %old = atomicrmw max i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -609,7 +609,7 @@ define i16 @test_atomic_load_max_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_max_i32:
+; CHECK-LABEL: test_atomic_load_max_i32:
    %old = atomicrmw max i32* @var32, i32 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -630,7 +630,7 @@ define i32 @test_atomic_load_max_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_max_i64:
+; CHECK-LABEL: test_atomic_load_max_i64:
    %old = atomicrmw max i64* @var64, i64 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -651,7 +651,7 @@ define i64 @test_atomic_load_max_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_umin_i8:
+; CHECK-LABEL: test_atomic_load_umin_i8:
    %old = atomicrmw umin i8* @var8, i8 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -672,7 +672,7 @@ define i8 @test_atomic_load_umin_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_umin_i16:
+; CHECK-LABEL: test_atomic_load_umin_i16:
    %old = atomicrmw umin i16* @var16, i16 %offset acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -693,7 +693,7 @@ define i16 @test_atomic_load_umin_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_umin_i32:
+; CHECK-LABEL: test_atomic_load_umin_i32:
    %old = atomicrmw umin i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -714,7 +714,7 @@ define i32 @test_atomic_load_umin_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_umin_i64:
+; CHECK-LABEL: test_atomic_load_umin_i64:
    %old = atomicrmw umin i64* @var64, i64 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -735,7 +735,7 @@ define i64 @test_atomic_load_umin_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
-; CHECK: test_atomic_load_umax_i8:
+; CHECK-LABEL: test_atomic_load_umax_i8:
    %old = atomicrmw umax i8* @var8, i8 %offset acq_rel
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -756,7 +756,7 @@ define i8 @test_atomic_load_umax_i8(i8 %offset) nounwind {
 }
 
 define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
-; CHECK: test_atomic_load_umax_i16:
+; CHECK-LABEL: test_atomic_load_umax_i16:
    %old = atomicrmw umax i16* @var16, i16 %offset monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -777,7 +777,7 @@ define i16 @test_atomic_load_umax_i16(i16 %offset) nounwind {
 }
 
 define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
-; CHECK: test_atomic_load_umax_i32:
+; CHECK-LABEL: test_atomic_load_umax_i32:
    %old = atomicrmw umax i32* @var32, i32 %offset seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -798,7 +798,7 @@ define i32 @test_atomic_load_umax_i32(i32 %offset) nounwind {
 }
 
 define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
-; CHECK: test_atomic_load_umax_i64:
+; CHECK-LABEL: test_atomic_load_umax_i64:
    %old = atomicrmw umax i64* @var64, i64 %offset release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -819,7 +819,7 @@ define i64 @test_atomic_load_umax_i64(i64 %offset) nounwind {
 }
 
 define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
-; CHECK: test_atomic_cmpxchg_i8:
+; CHECK-LABEL: test_atomic_cmpxchg_i8:
    %old = cmpxchg i8* @var8, i8 %wanted, i8 %new acquire
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -841,7 +841,7 @@ define i8 @test_atomic_cmpxchg_i8(i8 %wanted, i8 %new) nounwind {
 }
 
 define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
-; CHECK: test_atomic_cmpxchg_i16:
+; CHECK-LABEL: test_atomic_cmpxchg_i16:
    %old = cmpxchg i16* @var16, i16 %wanted, i16 %new seq_cst
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var16
@@ -863,7 +863,7 @@ define i16 @test_atomic_cmpxchg_i16(i16 %wanted, i16 %new) nounwind {
 }
 
 define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
-; CHECK: test_atomic_cmpxchg_i32:
+; CHECK-LABEL: test_atomic_cmpxchg_i32:
    %old = cmpxchg i32* @var32, i32 %wanted, i32 %new release
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var32
@@ -885,7 +885,7 @@ define i32 @test_atomic_cmpxchg_i32(i32 %wanted, i32 %new) nounwind {
 }
 
 define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
-; CHECK: test_atomic_cmpxchg_i64:
+; CHECK-LABEL: test_atomic_cmpxchg_i64:
    %old = cmpxchg i64* @var64, i64 %wanted, i64 %new monotonic
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var64
@@ -907,7 +907,7 @@ define i64 @test_atomic_cmpxchg_i64(i64 %wanted, i64 %new) nounwind {
 }
 
 define i8 @test_atomic_load_monotonic_i8() nounwind {
-; CHECK: test_atomic_load_monotonic_i8:
+; CHECK-LABEL: test_atomic_load_monotonic_i8:
   %val = load atomic i8* @var8 monotonic, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp x[[HIADDR:[0-9]+]], var8
@@ -918,7 +918,7 @@ define i8 @test_atomic_load_monotonic_i8() nounwind {
 }
 
 define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
-; CHECK: test_atomic_load_monotonic_regoff_i8:
+; CHECK-LABEL: test_atomic_load_monotonic_regoff_i8:
   %addr_int = add i64 %base, %off
   %addr = inttoptr i64 %addr_int to i8*
 
@@ -931,7 +931,7 @@ define i8 @test_atomic_load_monotonic_regoff_i8(i64 %base, i64 %off) nounwind {
 }
 
 define i8 @test_atomic_load_acquire_i8() nounwind {
-; CHECK: test_atomic_load_acquire_i8:
+; CHECK-LABEL: test_atomic_load_acquire_i8:
   %val = load atomic i8* @var8 acquire, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[TMPADDR:x[0-9]+]], var8
@@ -944,7 +944,7 @@ define i8 @test_atomic_load_acquire_i8() nounwind {
 }
 
 define i8 @test_atomic_load_seq_cst_i8() nounwind {
-; CHECK: test_atomic_load_seq_cst_i8:
+; CHECK-LABEL: test_atomic_load_seq_cst_i8:
   %val = load atomic i8* @var8 seq_cst, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var8
@@ -957,7 +957,7 @@ define i8 @test_atomic_load_seq_cst_i8() nounwind {
 }
 
 define i16 @test_atomic_load_monotonic_i16() nounwind {
-; CHECK: test_atomic_load_monotonic_i16:
+; CHECK-LABEL: test_atomic_load_monotonic_i16:
   %val = load atomic i16* @var16 monotonic, align 2
 ; CHECK-NOT: dmb
 ; CHECK: adrp x[[HIADDR:[0-9]+]], var16
@@ -969,7 +969,7 @@ define i16 @test_atomic_load_monotonic_i16() nounwind {
 }
 
 define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind {
-; CHECK: test_atomic_load_monotonic_regoff_i32:
+; CHECK-LABEL: test_atomic_load_monotonic_regoff_i32:
   %addr_int = add i64 %base, %off
   %addr = inttoptr i64 %addr_int to i32*
 
@@ -982,7 +982,7 @@ define i32 @test_atomic_load_monotonic_regoff_i32(i64 %base, i64 %off) nounwind
 }
 
 define i64 @test_atomic_load_seq_cst_i64() nounwind {
-; CHECK: test_atomic_load_seq_cst_i64:
+; CHECK-LABEL: test_atomic_load_seq_cst_i64:
   %val = load atomic i64* @var64 seq_cst, align 8
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var64
@@ -995,7 +995,7 @@ define i64 @test_atomic_load_seq_cst_i64() nounwind {
 }
 
 define void @test_atomic_store_monotonic_i8(i8 %val) nounwind {
-; CHECK: test_atomic_store_monotonic_i8:
+; CHECK-LABEL: test_atomic_store_monotonic_i8:
   store atomic i8 %val, i8* @var8 monotonic, align 1
 ; CHECK: adrp x[[HIADDR:[0-9]+]], var8
 ; CHECK: strb w0, [x[[HIADDR]], #:lo12:var8]
@@ -1004,7 +1004,7 @@ define void @test_atomic_store_monotonic_i8(i8 %val) nounwind {
 }
 
 define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val) nounwind {
-; CHECK: test_atomic_store_monotonic_regoff_i8:
+; CHECK-LABEL: test_atomic_store_monotonic_regoff_i8:
 
   %addr_int = add i64 %base, %off
   %addr = inttoptr i64 %addr_int to i8*
@@ -1015,7 +1015,7 @@ define void @test_atomic_store_monotonic_regoff_i8(i64 %base, i64 %off, i8 %val)
   ret void
 }
 define void @test_atomic_store_release_i8(i8 %val) nounwind {
-; CHECK: test_atomic_store_release_i8:
+; CHECK-LABEL: test_atomic_store_release_i8:
   store atomic i8 %val, i8* @var8 release, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var8
@@ -1028,7 +1028,7 @@ define void @test_atomic_store_release_i8(i8 %val) nounwind {
 }
 
 define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
-; CHECK: test_atomic_store_seq_cst_i8:
+; CHECK-LABEL: test_atomic_store_seq_cst_i8:
   store atomic i8 %val, i8* @var8 seq_cst, align 1
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var8
@@ -1042,7 +1042,7 @@ define void @test_atomic_store_seq_cst_i8(i8 %val) nounwind {
 }
 
 define void @test_atomic_store_monotonic_i16(i16 %val) nounwind {
-; CHECK: test_atomic_store_monotonic_i16:
+; CHECK-LABEL: test_atomic_store_monotonic_i16:
   store atomic i16 %val, i16* @var16 monotonic, align 2
 ; CHECK-NOT: dmb
 ; CHECK: adrp x[[HIADDR:[0-9]+]], var16
@@ -1053,7 +1053,7 @@ define void @test_atomic_store_monotonic_i16(i16 %val) nounwind {
 }
 
 define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %val) nounwind {
-; CHECK: test_atomic_store_monotonic_regoff_i32:
+; CHECK-LABEL: test_atomic_store_monotonic_regoff_i32:
 
   %addr_int = add i64 %base, %off
   %addr = inttoptr i64 %addr_int to i32*
@@ -1067,7 +1067,7 @@ define void @test_atomic_store_monotonic_regoff_i32(i64 %base, i64 %off, i32 %va
 }
 
 define void @test_atomic_store_release_i64(i64 %val) nounwind {
-; CHECK: test_atomic_store_release_i64:
+; CHECK-LABEL: test_atomic_store_release_i64:
   store atomic i64 %val, i64* @var64 release, align 8
 ; CHECK-NOT: dmb
 ; CHECK: adrp [[HIADDR:x[0-9]+]], var64
diff --git a/llvm/test/CodeGen/AArch64/basic-pic.ll b/llvm/test/CodeGen/AArch64/basic-pic.ll
index 5343cc7..1f0b282 100644
--- a/llvm/test/CodeGen/AArch64/basic-pic.ll
+++ b/llvm/test/CodeGen/AArch64/basic-pic.ll
@@ -67,4 +67,4 @@ define void()* @get_func() {
   ; it can relax it because it knows where get_func is. It can't!
 ; CHECK-ELF: R_AARCH64_ADR_GOT_PAGE get_func
 ; CHECK-ELF: R_AARCH64_LD64_GOT_LO12_NC get_func
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AArch64/bitfield-insert-0.ll b/llvm/test/CodeGen/AArch64/bitfield-insert-0.ll
index d1191f6..37a18b7 100644
--- a/llvm/test/CodeGen/AArch64/bitfield-insert-0.ll
+++ b/llvm/test/CodeGen/AArch64/bitfield-insert-0.ll
@@ -16,4 +16,4 @@ define void @test_bfi0(i32* %existing, i32* %new) {
   store volatile i32 %combined, i32* %existing
 
   ret void
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AArch64/bitfield-insert.ll b/llvm/test/CodeGen/AArch64/bitfield-insert.ll
index 3e871b9..fe2aedb 100644
--- a/llvm/test/CodeGen/AArch64/bitfield-insert.ll
+++ b/llvm/test/CodeGen/AArch64/bitfield-insert.ll
@@ -25,7 +25,7 @@ entry:
 }
 
 define void @test_whole32(i32* %existing, i32* %new) {
-; CHECK: test_whole32:
+; CHECK-LABEL: test_whole32:
 ; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #26, #5
 
   %oldval = load volatile i32* %existing
@@ -42,7 +42,7 @@ define void @test_whole32(i32* %existing, i32* %new) {
 }
 
 define void @test_whole64(i64* %existing, i64* %new) {
-; CHECK: test_whole64:
+; CHECK-LABEL: test_whole64:
 ; CHECK: bfi {{x[0-9]+}}, {{x[0-9]+}}, #26, #14
 ; CHECK-NOT: and
 ; CHECK: ret
@@ -61,7 +61,7 @@ define void @test_whole64(i64* %existing, i64* %new) {
 }
 
 define void @test_whole32_from64(i64* %existing, i64* %new) {
-; CHECK: test_whole32_from64:
+; CHECK-LABEL: test_whole32_from64:
 ; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #{{0|16}}, #16
 ; CHECK-NOT: and
 ; CHECK: ret
@@ -79,7 +79,7 @@ define void @test_whole32_from64(i64* %existing, i64* %new) {
 }
 
 define void @test_32bit_masked(i32 *%existing, i32 *%new) {
-; CHECK: test_32bit_masked:
+; CHECK-LABEL: test_32bit_masked:
 ; CHECK: bfi [[INSERT:w[0-9]+]], {{w[0-9]+}}, #3, #4
 ; CHECK: and {{w[0-9]+}}, [[INSERT]], #0xff
 
@@ -97,7 +97,7 @@ define void @test_32bit_masked(i32 *%existing, i32 *%new) {
 }
 
 define void @test_64bit_masked(i64 *%existing, i64 *%new) {
-; CHECK: test_64bit_masked:
+; CHECK-LABEL: test_64bit_masked:
 ; CHECK: bfi [[INSERT:x[0-9]+]], {{x[0-9]+}}, #40, #8
 ; CHECK: and {{x[0-9]+}}, [[INSERT]], #0xffff00000000
 
@@ -116,7 +116,7 @@ define void @test_64bit_masked(i64 *%existing, i64 *%new) {
 
 ; Mask is too complicated for literal ANDwwi, make sure other avenues are tried.
 define void @test_32bit_complexmask(i32 *%existing, i32 *%new) {
-; CHECK: test_32bit_complexmask:
+; CHECK-LABEL: test_32bit_complexmask:
 ; CHECK: bfi {{w[0-9]+}}, {{w[0-9]+}}, #3, #4
 ; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
 
@@ -135,7 +135,7 @@ define void @test_32bit_complexmask(i32 *%existing, i32 *%new) {
 
 ; Neither mask is is a contiguous set of 1s. BFI can't be used
 define void @test_32bit_badmask(i32 *%existing, i32 *%new) {
-; CHECK: test_32bit_badmask:
+; CHECK-LABEL: test_32bit_badmask:
 ; CHECK-NOT: bfi
 ; CHECK: ret
 
@@ -154,7 +154,7 @@ define void @test_32bit_badmask(i32 *%existing, i32 *%new) {
 
 ; Ditto
 define void @test_64bit_badmask(i64 *%existing, i64 *%new) {
-; CHECK: test_64bit_badmask:
+; CHECK-LABEL: test_64bit_badmask:
 ; CHECK-NOT: bfi
 ; CHECK: ret
 
@@ -174,7 +174,7 @@ define void @test_64bit_badmask(i64 *%existing, i64 *%new) {
 ; Bitfield insert where there's a left-over shr needed at the beginning
 ; (e.g. result of str.bf1 = str.bf2)
 define void @test_32bit_with_shr(i32* %existing, i32* %new) {
-; CHECK: test_32bit_with_shr:
+; CHECK-LABEL: test_32bit_with_shr:
 
   %oldval = load volatile i32* %existing
   %oldval_keep = and i32 %oldval, 2214592511 ; =0x83ffffff
diff --git a/llvm/test/CodeGen/AArch64/bitfield.ll b/llvm/test/CodeGen/AArch64/bitfield.ll
index 36d337e..1c84f5d 100644
--- a/llvm/test/CodeGen/AArch64/bitfield.ll
+++ b/llvm/test/CodeGen/AArch64/bitfield.ll
@@ -5,7 +5,7 @@
 @var64 = global i64 0
 
 define void @test_extendb(i8 %var) {
-; CHECK: test_extendb:
+; CHECK-LABEL: test_extendb:
 
   %sxt32 = sext i8 %var to i32
   store volatile i32 %sxt32, i32* @var32
@@ -29,7 +29,7 @@ define void @test_extendb(i8 %var) {
 }
 
 define void @test_extendh(i16 %var) {
-; CHECK: test_extendh:
+; CHECK-LABEL: test_extendh:
 
   %sxt32 = sext i16 %var to i32
   store volatile i32 %sxt32, i32* @var32
@@ -53,7 +53,7 @@ define void @test_extendh(i16 %var) {
 }
 
 define void @test_extendw(i32 %var) {
-; CHECK: test_extendw:
+; CHECK-LABEL: test_extendw:
 
   %sxt64 = sext i32 %var to i64
   store volatile i64 %sxt64, i64* @var64
@@ -66,7 +66,7 @@ define void @test_extendw(i32 %var) {
 }
 
 define void @test_shifts(i32 %val32, i64 %val64) {
-; CHECK: test_shifts:
+; CHECK-LABEL: test_shifts:
 
   %shift1 = ashr i32 %val32, 31
   store volatile i32 %shift1, i32* @var32
@@ -114,7 +114,7 @@ define void @test_shifts(i32 %val32, i64 %val64) {
 ; LLVM can produce in-register extensions taking place entirely with
 ; 64-bit registers too.
 define void @test_sext_inreg_64(i64 %in) {
-; CHECK: test_sext_inreg_64:
+; CHECK-LABEL: test_sext_inreg_64:
 
 ; i1 doesn't have an official alias, but crops up and is handled by
 ; the bitfield ops.
@@ -143,7 +143,7 @@ define void @test_sext_inreg_64(i64 %in) {
 ; These instructions don't actually select to official bitfield
 ; operations, but it's important that we select them somehow:
 define void @test_zext_inreg_64(i64 %in) {
-; CHECK: test_zext_inreg_64:
+; CHECK-LABEL: test_zext_inreg_64:
 
   %trunc_i8 = trunc i64 %in to i8
   %zext_i8 = zext i8 %trunc_i8 to i64
@@ -164,7 +164,7 @@ define void @test_zext_inreg_64(i64 %in) {
 }
 
 define i64 @test_sext_inreg_from_32(i32 %in) {
-; CHECK: test_sext_inreg_from_32:
+; CHECK-LABEL: test_sext_inreg_from_32:
 
   %small = trunc i32 %in to i1
   %ext = sext i1 %small to i64
@@ -178,7 +178,7 @@ define i64 @test_sext_inreg_from_32(i32 %in) {
 
 
 define i32 @test_ubfx32(i32* %addr) {
-; CHECK: test_ubfx32:
+; CHECK-LABEL: test_ubfx32:
 ; CHECK: ubfx {{w[0-9]+}}, {{w[0-9]+}}, #23, #3
 
    %fields = load i32* %addr
@@ -188,7 +188,7 @@ define i32 @test_ubfx32(i32* %addr) {
 }
 
 define i64 @test_ubfx64(i64* %addr) {
-; CHECK: test_ubfx64:
+; CHECK-LABEL: test_ubfx64:
 ; CHECK: ubfx {{x[0-9]+}}, {{x[0-9]+}}, #25, #10
 
    %fields = load i64* %addr
@@ -198,7 +198,7 @@ define i64 @test_ubfx64(i64* %addr) {
 }
 
 define i32 @test_sbfx32(i32* %addr) {
-; CHECK: test_sbfx32:
+; CHECK-LABEL: test_sbfx32:
 ; CHECK: sbfx {{w[0-9]+}}, {{w[0-9]+}}, #6, #3
 
    %fields = load i32* %addr
@@ -208,7 +208,7 @@ define i32 @test_sbfx32(i32* %addr) {
 }
 
 define i64 @test_sbfx64(i64* %addr) {
-; CHECK: test_sbfx64:
+; CHECK-LABEL: test_sbfx64:
 ; CHECK: sbfx {{x[0-9]+}}, {{x[0-9]+}}, #0, #63
 
    %fields = load i64* %addr
diff --git a/llvm/test/CodeGen/AArch64/blockaddress.ll b/llvm/test/CodeGen/AArch64/blockaddress.ll
index 5e85057..8cda431 100644
--- a/llvm/test/CodeGen/AArch64/blockaddress.ll
+++ b/llvm/test/CodeGen/AArch64/blockaddress.ll
@@ -4,7 +4,7 @@
 @addr = global i8* null
 
 define void @test_blockaddress() {
-; CHECK: test_blockaddress:
+; CHECK-LABEL: test_blockaddress:
   store volatile i8* blockaddress(@test_blockaddress, %block), i8** @addr
   %val = load volatile i8** @addr
   indirectbr i8* %val, [label %block]
diff --git a/llvm/test/CodeGen/AArch64/compare-branch.ll b/llvm/test/CodeGen/AArch64/compare-branch.ll
index 4213110..62f4cd5 100644
--- a/llvm/test/CodeGen/AArch64/compare-branch.ll
+++ b/llvm/test/CodeGen/AArch64/compare-branch.ll
@@ -35,4 +35,4 @@ test5:
 
 end:
   ret void
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AArch64/cond-sel.ll b/llvm/test/CodeGen/AArch64/cond-sel.ll
index 3051cf5..48c50a1 100644
--- a/llvm/test/CodeGen/AArch64/cond-sel.ll
+++ b/llvm/test/CodeGen/AArch64/cond-sel.ll
@@ -4,7 +4,7 @@
 @var64 = global i64 0
 
 define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
-; CHECK: test_csel:
+; CHECK-LABEL: test_csel:
 
   %tst1 = icmp ugt i32 %lhs32, %rhs32
   %val1 = select i1 %tst1, i32 42, i32 52
@@ -26,7 +26,7 @@ define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
 }
 
 define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %rhs64) {
-; CHECK: test_floatcsel:
+; CHECK-LABEL: test_floatcsel:
 
   %tst1 = fcmp one float %lhs32, %rhs32
 ; CHECK: fcmp {{s[0-9]+}}, {{s[0-9]+}}
@@ -53,7 +53,7 @@ define void @test_floatcsel(float %lhs32, float %rhs32, double %lhs64, double %r
 
 
 define void @test_csinc(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
-; CHECK: test_csinc:
+; CHECK-LABEL: test_csinc:
 
 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
   %tst1 = icmp ugt i32 %lhs32, %rhs32
@@ -93,7 +93,7 @@ define void @test_csinc(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
 }
 
 define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
-; CHECK: test_csinv:
+; CHECK-LABEL: test_csinv:
 
 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
   %tst1 = icmp ugt i32 %lhs32, %rhs32
@@ -133,7 +133,7 @@ define void @test_csinv(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
 }
 
 define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
-; CHECK: test_csneg:
+; CHECK-LABEL: test_csneg:
 
 ; Note that commuting rhs and lhs in the select changes ugt to ule (i.e. hi to ls).
   %tst1 = icmp ugt i32 %lhs32, %rhs32
@@ -173,7 +173,7 @@ define void @test_csneg(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
 }
 
 define void @test_cset(i32 %lhs, i32 %rhs, i64 %lhs64) {
-; CHECK: test_cset:
+; CHECK-LABEL: test_cset:
 
 ; N.b. code is not optimal here (32-bit csinc would be better) but
 ; incoming DAG is too complex
@@ -194,7 +194,7 @@ define void @test_cset(i32 %lhs, i32 %rhs, i64 %lhs64) {
 }
 
 define void @test_csetm(i32 %lhs, i32 %rhs, i64 %lhs64) {
-; CHECK: test_csetm:
+; CHECK-LABEL: test_csetm:
 
   %tst1 = icmp eq i32 %lhs, %rhs
   %val1 = sext i1 %tst1 to i32
diff --git a/llvm/test/CodeGen/AArch64/directcond.ll b/llvm/test/CodeGen/AArch64/directcond.ll
index f5d5759..13f032d 100644
--- a/llvm/test/CodeGen/AArch64/directcond.ll
+++ b/llvm/test/CodeGen/AArch64/directcond.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
 
 define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) {
-; CHECK: test_select_i32:
+; CHECK-LABEL: test_select_i32:
   %val = select i1 %bit, i32 %a, i32 %b
 ; CHECK: movz [[ONE:w[0-9]+]], #1
 ; CHECK: tst w0, [[ONE]]
@@ -11,7 +11,7 @@ define i32 @test_select_i32(i1 %bit, i32 %a, i32 %b) {
 }
 
 define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) {
-; CHECK: test_select_i64:
+; CHECK-LABEL: test_select_i64:
   %val = select i1 %bit, i64 %a, i64 %b
 ; CHECK: movz [[ONE:w[0-9]+]], #1
 ; CHECK: tst w0, [[ONE]]
@@ -21,7 +21,7 @@ define i64 @test_select_i64(i1 %bit, i64 %a, i64 %b) {
 }
 
 define float @test_select_float(i1 %bit, float %a, float %b) {
-; CHECK: test_select_float:
+; CHECK-LABEL: test_select_float:
   %val = select i1 %bit, float %a, float %b
 ; CHECK: movz [[ONE:w[0-9]+]], #1
 ; CHECK: tst w0, [[ONE]]
@@ -31,7 +31,7 @@ define float @test_select_float(i1 %bit, float %a, float %b) {
 }
 
 define double @test_select_double(i1 %bit, double %a, double %b) {
-; CHECK: test_select_double:
+; CHECK-LABEL: test_select_double:
   %val = select i1 %bit, double %a, double %b
 ; CHECK: movz [[ONE:w[0-9]+]], #1
 ; CHECK: tst w0, [[ONE]]
@@ -41,7 +41,7 @@ define double @test_select_double(i1 %bit, double %a, double %b) {
 }
 
 define i32 @test_brcond(i1 %bit) {
-; CHECK: test_brcond:
+; CHECK-LABEL: test_brcond:
   br i1 %bit, label %true, label %false
 ; CHECK: tbz {{w[0-9]+}}, #0, .LBB
 
diff --git a/llvm/test/CodeGen/AArch64/dp-3source.ll b/llvm/test/CodeGen/AArch64/dp-3source.ll
index c40d393..81d9e15 100644
--- a/llvm/test/CodeGen/AArch64/dp-3source.ll
+++ b/llvm/test/CodeGen/AArch64/dp-3source.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
 
 define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) {
-; CHECK: test_madd32:
+; CHECK-LABEL: test_madd32:
   %mid = mul i32 %val1, %val2
   %res = add i32 %val0, %mid
 ; CHECK: madd {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
@@ -9,7 +9,7 @@ define i32 @test_madd32(i32 %val0, i32 %val1, i32 %val2) {
 }
 
 define i64 @test_madd64(i64 %val0, i64 %val1, i64 %val2) {
-; CHECK: test_madd64:
+; CHECK-LABEL: test_madd64:
   %mid = mul i64 %val1, %val2
   %res = add i64 %val0, %mid
 ; CHECK: madd {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
@@ -17,7 +17,7 @@ define i64 @test_madd64(i64 %val0, i64 %val1, i64 %val2) {
 }
 
 define i32 @test_msub32(i32 %val0, i32 %val1, i32 %val2) {
-; CHECK: test_msub32:
+; CHECK-LABEL: test_msub32:
   %mid = mul i32 %val1, %val2
   %res = sub i32 %val0, %mid
 ; CHECK: msub {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
@@ -25,7 +25,7 @@ define i32 @test_msub32(i32 %val0, i32 %val1, i32 %val2) {
 }
 
 define i64 @test_msub64(i64 %val0, i64 %val1, i64 %val2) {
-; CHECK: test_msub64:
+; CHECK-LABEL: test_msub64:
   %mid = mul i64 %val1, %val2
   %res = sub i64 %val0, %mid
 ; CHECK: msub {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
@@ -33,7 +33,7 @@ define i64 @test_msub64(i64 %val0, i64 %val1, i64 %val2) {
 }
 
 define i64 @test_smaddl(i64 %acc, i32 %val1, i32 %val2) {
-; CHECK: test_smaddl:
+; CHECK-LABEL: test_smaddl:
   %ext1 = sext i32 %val1 to i64
   %ext2 = sext i32 %val2 to i64
   %prod = mul i64 %ext1, %ext2
@@ -43,7 +43,7 @@ define i64 @test_smaddl(i64 %acc, i32 %val1, i32 %val2) {
 }
 
 define i64 @test_smsubl(i64 %acc, i32 %val1, i32 %val2) {
-; CHECK: test_smsubl:
+; CHECK-LABEL: test_smsubl:
   %ext1 = sext i32 %val1 to i64
   %ext2 = sext i32 %val2 to i64
   %prod = mul i64 %ext1, %ext2
@@ -53,7 +53,7 @@ define i64 @test_smsubl(i64 %acc, i32 %val1, i32 %val2) {
 }
 
 define i64 @test_umaddl(i64 %acc, i32 %val1, i32 %val2) {
-; CHECK: test_umaddl:
+; CHECK-LABEL: test_umaddl:
   %ext1 = zext i32 %val1 to i64
   %ext2 = zext i32 %val2 to i64
   %prod = mul i64 %ext1, %ext2
@@ -63,7 +63,7 @@ define i64 @test_umaddl(i64 %acc, i32 %val1, i32 %val2) {
 }
 
 define i64 @test_umsubl(i64 %acc, i32 %val1, i32 %val2) {
-; CHECK: test_umsubl:
+; CHECK-LABEL: test_umsubl:
   %ext1 = zext i32 %val1 to i64
   %ext2 = zext i32 %val2 to i64
   %prod = mul i64 %ext1, %ext2
@@ -73,7 +73,7 @@ define i64 @test_umsubl(i64 %acc, i32 %val1, i32 %val2) {
 }
 
 define i64 @test_smulh(i64 %lhs, i64 %rhs) {
-; CHECK: test_smulh:
+; CHECK-LABEL: test_smulh:
   %ext1 = sext i64 %lhs to i128
   %ext2 = sext i64 %rhs to i128
   %res = mul i128 %ext1, %ext2
@@ -84,7 +84,7 @@ define i64 @test_smulh(i64 %lhs, i64 %rhs) {
 }
 
 define i64 @test_umulh(i64 %lhs, i64 %rhs) {
-; CHECK: test_umulh:
+; CHECK-LABEL: test_umulh:
   %ext1 = zext i64 %lhs to i128
   %ext2 = zext i64 %rhs to i128
   %res = mul i128 %ext1, %ext2
@@ -95,21 +95,21 @@ define i64 @test_umulh(i64 %lhs, i64 %rhs) {
 }
 
 define i32 @test_mul32(i32 %lhs, i32 %rhs) {
-; CHECK: test_mul32:
+; CHECK-LABEL: test_mul32:
   %res = mul i32 %lhs, %rhs
 ; CHECK: mul {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
   ret i32 %res
 }
 
 define i64 @test_mul64(i64 %lhs, i64 %rhs) {
-; CHECK: test_mul64:
+; CHECK-LABEL: test_mul64:
   %res = mul i64 %lhs, %rhs
 ; CHECK: mul {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
   ret i64 %res
 }
 
 define i32 @test_mneg32(i32 %lhs, i32 %rhs) {
-; CHECK: test_mneg32:
+; CHECK-LABEL: test_mneg32:
   %prod = mul i32 %lhs, %rhs
   %res = sub i32 0, %prod
 ; CHECK: mneg {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}
@@ -117,7 +117,7 @@ define i32 @test_mneg32(i32 %lhs, i32 %rhs) {
 }
 
 define i64 @test_mneg64(i64 %lhs, i64 %rhs) {
-; CHECK: test_mneg64:
+; CHECK-LABEL: test_mneg64:
   %prod = mul i64 %lhs, %rhs
   %res = sub i64 0, %prod
 ; CHECK: mneg {{x[0-9]+}}, {{x[0-9]+}}, {{x[0-9]+}}
@@ -125,7 +125,7 @@ define i64 @test_mneg64(i64 %lhs, i64 %rhs) {
 }
 
 define i64 @test_smull(i32 %lhs, i32 %rhs) {
-; CHECK: test_smull:
+; CHECK-LABEL: test_smull:
   %ext1 = sext i32 %lhs to i64
   %ext2 = sext i32 %rhs to i64
   %res = mul i64 %ext1, %ext2
@@ -134,7 +134,7 @@ define i64 @test_smull(i32 %lhs, i32 %rhs) {
 }
 
 define i64 @test_umull(i32 %lhs, i32 %rhs) {
-; CHECK: test_umull:
+; CHECK-LABEL: test_umull:
   %ext1 = zext i32 %lhs to i64
   %ext2 = zext i32 %rhs to i64
   %res = mul i64 %ext1, %ext2
@@ -143,7 +143,7 @@ define i64 @test_umull(i32 %lhs, i32 %rhs) {
 }
 
 define i64 @test_smnegl(i32 %lhs, i32 %rhs) {
-; CHECK: test_smnegl:
+; CHECK-LABEL: test_smnegl:
   %ext1 = sext i32 %lhs to i64
   %ext2 = sext i32 %rhs to i64
   %prod = mul i64 %ext1, %ext2
@@ -153,7 +153,7 @@ define i64 @test_smnegl(i32 %lhs, i32 %rhs) {
 }
 
 define i64 @test_umnegl(i32 %lhs, i32 %rhs) {
-; CHECK: test_umnegl:
+; CHECK-LABEL: test_umnegl:
   %ext1 = zext i32 %lhs to i64
   %ext2 = zext i32 %rhs to i64
   %prod = mul i64 %ext1, %ext2
diff --git a/llvm/test/CodeGen/AArch64/dp2.ll b/llvm/test/CodeGen/AArch64/dp2.ll
index 4c740f6..a5ebc2f 100644
--- a/llvm/test/CodeGen/AArch64/dp2.ll
+++ b/llvm/test/CodeGen/AArch64/dp2.ll
@@ -139,7 +139,7 @@ define void @udiv_i32() {
 ; The point of this test is that we may not actually see (shl GPR32:$Val, (zext GPR32:$Val2))
 ; in the DAG (the RHS may be natively 64-bit), but we should still use the lsl instructions.
 define i32 @test_lsl32() {
-; CHECK: test_lsl32:
+; CHECK-LABEL: test_lsl32:
 
   %val = load i32* @var32_0
   %ret = shl i32 1, %val
@@ -149,7 +149,7 @@ define i32 @test_lsl32() {
 }
 
 define i32 @test_lsr32() {
-; CHECK: test_lsr32:
+; CHECK-LABEL: test_lsr32:
 
   %val = load i32* @var32_0
   %ret = lshr i32 1, %val
@@ -159,7 +159,7 @@ define i32 @test_lsr32() {
 }
 
 define i32 @test_asr32(i32 %in) {
-; CHECK: test_asr32:
+; CHECK-LABEL: test_asr32:
 
   %val = load i32* @var32_0
   %ret = ashr i32 %in, %val
diff --git a/llvm/test/CodeGen/AArch64/extern-weak.ll b/llvm/test/CodeGen/AArch64/extern-weak.ll
index bc0acc2..322b3f4 100644
--- a/llvm/test/CodeGen/AArch64/extern-weak.ll
+++ b/llvm/test/CodeGen/AArch64/extern-weak.ll
@@ -51,4 +51,4 @@ define i32* @wibble() {
 ; CHECK-LARGE: movk x0, #:abs_g2_nc:defined_weak_var
 ; CHECK-LARGE: movk x0, #:abs_g1_nc:defined_weak_var
 ; CHECK-LARGE: movk x0, #:abs_g0_nc:defined_weak_var
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AArch64/fcmp.ll b/llvm/test/CodeGen/AArch64/fcmp.ll
index ad4a903..a9518ea 100644
--- a/llvm/test/CodeGen/AArch64/fcmp.ll
+++ b/llvm/test/CodeGen/AArch64/fcmp.ll
@@ -3,7 +3,7 @@
 declare void @bar(i32)
 
 define void @test_float(float %a, float %b) {
-; CHECK: test_float:
+; CHECK-LABEL: test_float:
 
   %tst1 = fcmp oeq float %a, %b
   br i1 %tst1, label %end, label %t2
@@ -42,7 +42,7 @@ end:
 }
 
 define void @test_double(double %a, double %b) {
-; CHECK: test_double:
+; CHECK-LABEL: test_double:
 
   %tst1 = fcmp oeq double %a, %b
   br i1 %tst1, label %end, label %t2
diff --git a/llvm/test/CodeGen/AArch64/fcvt-fixed.ll b/llvm/test/CodeGen/AArch64/fcvt-fixed.ll
index 0f7b95b..9d66da4 100644
--- a/llvm/test/CodeGen/AArch64/fcvt-fixed.ll
+++ b/llvm/test/CodeGen/AArch64/fcvt-fixed.ll
@@ -4,7 +4,7 @@
 @var64 = global i64 0
 
 define void @test_fcvtzs(float %flt, double %dbl) {
-; CHECK: test_fcvtzs:
+; CHECK-LABEL: test_fcvtzs:
 
   %fix1 = fmul float %flt, 128.0
   %cvt1 = fptosi float %fix1 to i32
@@ -50,7 +50,7 @@ define void @test_fcvtzs(float %flt, double %dbl) {
 }
 
 define void @test_fcvtzu(float %flt, double %dbl) {
-; CHECK: test_fcvtzu:
+; CHECK-LABEL: test_fcvtzu:
 
   %fix1 = fmul float %flt, 128.0
   %cvt1 = fptoui float %fix1 to i32
@@ -99,7 +99,7 @@ define void @test_fcvtzu(float %flt, double %dbl) {
 @vardouble = global double 0.0
 
 define void @test_scvtf(i32 %int, i64 %long) {
-; CHECK: test_scvtf:
+; CHECK-LABEL: test_scvtf:
 
   %cvt1 = sitofp i32 %int to float
   %fix1 = fdiv float %cvt1, 128.0
@@ -145,7 +145,7 @@ define void @test_scvtf(i32 %int, i64 %long) {
 }
 
 define void @test_ucvtf(i32 %int, i64 %long) {
-; CHECK: test_ucvtf:
+; CHECK-LABEL: test_ucvtf:
 
   %cvt1 = uitofp i32 %int to float
   %fix1 = fdiv float %cvt1, 128.0
diff --git a/llvm/test/CodeGen/AArch64/fcvt-int.ll b/llvm/test/CodeGen/AArch64/fcvt-int.ll
index c771d68..9afcfc4 100644
--- a/llvm/test/CodeGen/AArch64/fcvt-int.ll
+++ b/llvm/test/CodeGen/AArch64/fcvt-int.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
 
 define i32 @test_floattoi32(float %in) {
-; CHECK: test_floattoi32:
+; CHECK-LABEL: test_floattoi32:
 
   %signed = fptosi float %in to i32
   %unsigned = fptoui float %in to i32
@@ -16,7 +16,7 @@ define i32 @test_floattoi32(float %in) {
 }
 
 define i32 @test_doubletoi32(double %in) {
-; CHECK: test_doubletoi32:
+; CHECK-LABEL: test_doubletoi32:
 
   %signed = fptosi double %in to i32
   %unsigned = fptoui double %in to i32
@@ -31,7 +31,7 @@ define i32 @test_doubletoi32(double %in) {
 }
 
 define i64 @test_floattoi64(float %in) {
-; CHECK: test_floattoi64:
+; CHECK-LABEL: test_floattoi64:
 
   %signed = fptosi float %in to i64
   %unsigned = fptoui float %in to i64
@@ -46,7 +46,7 @@ define i64 @test_floattoi64(float %in) {
 }
 
 define i64 @test_doubletoi64(double %in) {
-; CHECK: test_doubletoi64:
+; CHECK-LABEL: test_doubletoi64:
 
   %signed = fptosi double %in to i64
   %unsigned = fptoui double %in to i64
@@ -61,7 +61,7 @@ define i64 @test_doubletoi64(double %in) {
 }
 
 define float @test_i32tofloat(i32 %in) {
-; CHECK: test_i32tofloat:
+; CHECK-LABEL: test_i32tofloat:
 
   %signed = sitofp i32 %in to float
   %unsigned = uitofp i32 %in to float
@@ -75,7 +75,7 @@ define float @test_i32tofloat(i32 %in) {
 }
 
 define double @test_i32todouble(i32 %in) {
-; CHECK: test_i32todouble:
+; CHECK-LABEL: test_i32todouble:
 
   %signed = sitofp i32 %in to double
   %unsigned = uitofp i32 %in to double
@@ -89,7 +89,7 @@ define double @test_i32todouble(i32 %in) {
 }
 
 define float @test_i64tofloat(i64 %in) {
-; CHECK: test_i64tofloat:
+; CHECK-LABEL: test_i64tofloat:
 
   %signed = sitofp i64 %in to float
   %unsigned = uitofp i64 %in to float
@@ -103,7 +103,7 @@ define float @test_i64tofloat(i64 %in) {
 }
 
 define double @test_i64todouble(i64 %in) {
-; CHECK: test_i64todouble:
+; CHECK-LABEL: test_i64todouble:
 
   %signed = sitofp i64 %in to double
   %unsigned = uitofp i64 %in to double
@@ -117,7 +117,7 @@ define double @test_i64todouble(i64 %in) {
 }
 
 define i32 @test_bitcastfloattoi32(float %in) {
-; CHECK: test_bitcastfloattoi32:
+; CHECK-LABEL: test_bitcastfloattoi32:
 
    %res = bitcast float %in to i32
 ; CHECK: fmov {{w[0-9]+}}, {{s[0-9]+}}
@@ -125,7 +125,7 @@ define i32 @test_bitcastfloattoi32(float %in) {
 }
 
 define i64 @test_bitcastdoubletoi64(double %in) {
-; CHECK: test_bitcastdoubletoi64:
+; CHECK-LABEL: test_bitcastdoubletoi64:
 
    %res = bitcast double %in to i64
 ; CHECK: fmov {{x[0-9]+}}, {{d[0-9]+}}
@@ -133,7 +133,7 @@ define i64 @test_bitcastdoubletoi64(double %in) {
 }
 
 define float @test_bitcasti32tofloat(i32 %in) {
-; CHECK: test_bitcasti32tofloat:
+; CHECK-LABEL: test_bitcasti32tofloat:
 
    %res = bitcast i32 %in to float
 ; CHECK: fmov {{s[0-9]+}}, {{w[0-9]+}}
@@ -142,7 +142,7 @@ define float @test_bitcasti32tofloat(i32 %in) {
 }
 
 define double @test_bitcasti64todouble(i64 %in) {
-; CHECK: test_bitcasti64todouble:
+; CHECK-LABEL: test_bitcasti64todouble:
 
    %res = bitcast i64 %in to double
 ; CHECK: fmov {{d[0-9]+}}, {{x[0-9]+}}
diff --git a/llvm/test/CodeGen/AArch64/flags-multiuse.ll b/llvm/test/CodeGen/AArch64/flags-multiuse.ll
index 940c146..e99c728 100644
--- a/llvm/test/CodeGen/AArch64/flags-multiuse.ll
+++ b/llvm/test/CodeGen/AArch64/flags-multiuse.ll
@@ -9,7 +9,7 @@ declare void @bar()
 @var = global i32 0
 
 define i32 @test_multiflag(i32 %n, i32 %m, i32 %o) {
-; CHECK: test_multiflag:
+; CHECK-LABEL: test_multiflag:
 
   %test = icmp ne i32 %n, %m
 ; CHECK: cmp [[LHS:w[0-9]+]], [[RHS:w[0-9]+]]
diff --git a/llvm/test/CodeGen/AArch64/floatdp_2source.ll b/llvm/test/CodeGen/AArch64/floatdp_2source.ll
index b2256b3..bb65528 100644
--- a/llvm/test/CodeGen/AArch64/floatdp_2source.ll
+++ b/llvm/test/CodeGen/AArch64/floatdp_2source.ll
@@ -4,7 +4,7 @@
 @vardouble = global double 0.0
 
 define void @testfloat() {
-; CHECK: testfloat:
+; CHECK-LABEL: testfloat:
   %val1 = load float* @varfloat
 
   %val2 = fadd float %val1, %val1
@@ -32,7 +32,7 @@ define void @testfloat() {
 }
 
 define void @testdouble() {
-; CHECK: testdouble:
+; CHECK-LABEL: testdouble:
   %val1 = load double* @vardouble
 
   %val2 = fadd double %val1, %val1
diff --git a/llvm/test/CodeGen/AArch64/fp-cond-sel.ll b/llvm/test/CodeGen/AArch64/fp-cond-sel.ll
index 56e8f16..572f42e 100644
--- a/llvm/test/CodeGen/AArch64/fp-cond-sel.ll
+++ b/llvm/test/CodeGen/AArch64/fp-cond-sel.ll
@@ -4,7 +4,7 @@
 @vardouble = global double 0.0
 
 define void @test_csel(i32 %lhs32, i32 %rhs32, i64 %lhs64) {
-; CHECK: test_csel:
+; CHECK-LABEL: test_csel:
 
   %tst1 = icmp ugt i32 %lhs32, %rhs32
   %val1 = select i1 %tst1, float 0.0, float 1.0
diff --git a/llvm/test/CodeGen/AArch64/fp-dp3.ll b/llvm/test/CodeGen/AArch64/fp-dp3.ll
index f4c00a7..09d9072 100644
--- a/llvm/test/CodeGen/AArch64/fp-dp3.ll
+++ b/llvm/test/CodeGen/AArch64/fp-dp3.ll
@@ -45,7 +45,7 @@ define float @test_fnmsub(float %a, float %b, float %c) {
 }
 
 define double @testd_fmadd(double %a, double %b, double %c) {
-; CHECK: testd_fmadd:
+; CHECK-LABEL: testd_fmadd:
 ; CHECK-NOFAST: testd_fmadd:
   %val = call double @llvm.fma.f64(double %a, double %b, double %c)
 ; CHECK: fmadd {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}, {{d[0-9]+}}
@@ -54,7 +54,7 @@ define double @testd_fmadd(double %a, double %b, double %c) {
 }
 
 define double @testd_fmsub(double %a, double %b, double %c) {
-; CHECK: testd_fmsub:
+; CHECK-LABEL: testd_fmsub:
 ; CHECK-NOFAST: testd_fmsub:
   %nega = fsub double -0.0, %a
   %val = call double @llvm.fma.f64(double %nega, double %b, double %c)
@@ -64,7 +64,7 @@ define double @testd_fmsub(double %a, double %b, double %c) {
 }
 
 define double @testd_fnmadd(double %a, double %b, double %c) {
-; CHECK: testd_fnmadd:
+; CHECK-LABEL: testd_fnmadd:
 ; CHECK-NOFAST: testd_fnmadd:
   %negc = fsub double -0.0, %c
   %val = call double @llvm.fma.f64(double %a, double %b, double %negc)
@@ -74,7 +74,7 @@ define double @testd_fnmadd(double %a, double %b, double %c) {
 }
 
 define double @testd_fnmsub(double %a, double %b, double %c) {
-; CHECK: testd_fnmsub:
+; CHECK-LABEL: testd_fnmsub:
 ; CHECK-NOFAST: testd_fnmsub:
   %nega = fsub double -0.0, %a
   %negc = fsub double -0.0, %c
diff --git a/llvm/test/CodeGen/AArch64/fp128-folding.ll b/llvm/test/CodeGen/AArch64/fp128-folding.ll
index b5bdcf4..b1c560d2 100644
--- a/llvm/test/CodeGen/AArch64/fp128-folding.ll
+++ b/llvm/test/CodeGen/AArch64/fp128-folding.ll
@@ -5,7 +5,7 @@ declare void @bar(i8*, i8*, i32*)
 ; which is not supported.
 
 define fp128 @test_folding() {
-; CHECK: test_folding:
+; CHECK-LABEL: test_folding:
   %l = alloca i32
   store i32 42, i32* %l
   %val = load i32* %l
@@ -14,4 +14,4 @@ define fp128 @test_folding() {
   ; successfully.
 ; CHECK: ldr {{q[0-9]+}}, [{{x[0-9]+}}, #:lo12:.LCPI
   ret fp128 %fpval
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AArch64/fp128.ll b/llvm/test/CodeGen/AArch64/fp128.ll
index 258d34b..853c03d 100644
--- a/llvm/test/CodeGen/AArch64/fp128.ll
+++ b/llvm/test/CodeGen/AArch64/fp128.ll
@@ -4,7 +4,7 @@
 @rhs = global fp128 zeroinitializer
 
 define fp128 @test_add() {
-; CHECK: test_add:
+; CHECK-LABEL: test_add:
 
   %lhs = load fp128* @lhs
   %rhs = load fp128* @rhs
@@ -17,7 +17,7 @@ define fp128 @test_add() {
 }
 
 define fp128 @test_sub() {
-; CHECK: test_sub:
+; CHECK-LABEL: test_sub:
 
   %lhs = load fp128* @lhs
   %rhs = load fp128* @rhs
@@ -30,7 +30,7 @@ define fp128 @test_sub() {
 }
 
 define fp128 @test_mul() {
-; CHECK: test_mul:
+; CHECK-LABEL: test_mul:
 
   %lhs = load fp128* @lhs
   %rhs = load fp128* @rhs
@@ -43,7 +43,7 @@ define fp128 @test_mul() {
 }
 
 define fp128 @test_div() {
-; CHECK: test_div:
+; CHECK-LABEL: test_div:
 
   %lhs = load fp128* @lhs
   %rhs = load fp128* @rhs
@@ -59,7 +59,7 @@ define fp128 @test_div() {
 @var64 = global i64 0
 
 define void @test_fptosi() {
-; CHECK: test_fptosi:
+; CHECK-LABEL: test_fptosi:
   %val = load fp128* @lhs
 
   %val32 = fptosi fp128 %val to i32
@@ -74,7 +74,7 @@ define void @test_fptosi() {
 }
 
 define void @test_fptoui() {
-; CHECK: test_fptoui:
+; CHECK-LABEL: test_fptoui:
   %val = load fp128* @lhs
 
   %val32 = fptoui fp128 %val to i32
@@ -89,7 +89,7 @@ define void @test_fptoui() {
 }
 
 define void @test_sitofp() {
-; CHECK: test_sitofp:
+; CHECK-LABEL: test_sitofp:
 
   %src32 = load i32* @var32
   %val32 = sitofp i32 %src32 to fp128
@@ -105,7 +105,7 @@ define void @test_sitofp() {
 }
 
 define void @test_uitofp() {
-; CHECK: test_uitofp:
+; CHECK-LABEL: test_uitofp:
 
   %src32 = load i32* @var32
   %val32 = uitofp i32 %src32 to fp128
@@ -121,7 +121,7 @@ define void @test_uitofp() {
 }
 
 define i1 @test_setcc1() {
-; CHECK: test_setcc1:
+; CHECK-LABEL: test_setcc1:
 
   %lhs = load fp128* @lhs
   %rhs = load fp128* @rhs
@@ -140,7 +140,7 @@ define i1 @test_setcc1() {
 }
 
 define i1 @test_setcc2() {
-; CHECK: test_setcc2:
+; CHECK-LABEL: test_setcc2:
 
   %lhs = load fp128* @lhs
   %rhs = load fp128* @rhs
@@ -165,7 +165,7 @@ define i1 @test_setcc2() {
 }
 
 define i32 @test_br_cc() {
-; CHECK: test_br_cc:
+; CHECK-LABEL: test_br_cc:
 
   %lhs = load fp128* @lhs
   %rhs = load fp128* @rhs
@@ -202,7 +202,7 @@ iffalse:
 }
 
 define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
-; CHECK: test_select:
+; CHECK-LABEL: test_select:
 
   %val = select i1 %cond, fp128 %lhs, fp128 %rhs
   store fp128 %val, fp128* @lhs
@@ -222,7 +222,7 @@ define void @test_select(i1 %cond, fp128 %lhs, fp128 %rhs) {
 @vardouble = global double 0.0
 
 define void @test_round() {
-; CHECK: test_round:
+; CHECK-LABEL: test_round:
 
   %val = load fp128* @lhs
 
@@ -240,7 +240,7 @@ define void @test_round() {
 }
 
 define void @test_extend() {
-; CHECK: test_extend:
+; CHECK-LABEL: test_extend:
 
   %val = load fp128* @lhs
 
@@ -265,7 +265,7 @@ define fp128 @test_neg(fp128 %in) {
 ; Make sure the weird hex constant below *is* -0.0
 ; CHECK-NEXT: fp128 -0
 
-; CHECK: test_neg:
+; CHECK-LABEL: test_neg:
 
   ; Could in principle be optimized to fneg which we can't select, this makes
   ; sure that doesn't happen.
diff --git a/llvm/test/CodeGen/AArch64/func-argpassing.ll b/llvm/test/CodeGen/AArch64/func-argpassing.ll
index 78fde6a..7367107 100644
--- a/llvm/test/CodeGen/AArch64/func-argpassing.ll
+++ b/llvm/test/CodeGen/AArch64/func-argpassing.ll
@@ -186,7 +186,7 @@ define void @check_i128_stackalign(i32 %val0, i32 %val1, i32 %val2, i32 %val3,
 declare void @llvm.memcpy.p0i8.p0i8.i32(i8*, i8*, i32, i32, i1)
 
 define i32 @test_extern() {
-; CHECK: test_extern:
+; CHECK-LABEL: test_extern:
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* undef, i8* undef, i32 undef, i32 4, i1 0)
 ; CHECK: bl memcpy
   ret i32 0
diff --git a/llvm/test/CodeGen/AArch64/global-alignment.ll b/llvm/test/CodeGen/AArch64/global-alignment.ll
index 8ed6e55..56e5cba 100644
--- a/llvm/test/CodeGen/AArch64/global-alignment.ll
+++ b/llvm/test/CodeGen/AArch64/global-alignment.ll
@@ -5,7 +5,7 @@
 @var32_align64 = global [3 x i32] zeroinitializer, align 8
 
 define i64 @test_align32() {
-; CHECK: test_align32:
+; CHECK-LABEL: test_align32:
   %addr = bitcast [3 x i32]* @var32 to i64*
 
   ; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to
@@ -19,7 +19,7 @@ define i64 @test_align32() {
 }
 
 define i64 @test_align64() {
-; CHECK: test_align64:
+; CHECK-LABEL: test_align64:
   %addr = bitcast [3 x i64]* @var64 to i64*
 
   ; However, var64 *is* properly aligned and emitting an adrp/add/ldr would be
@@ -33,7 +33,7 @@ define i64 @test_align64() {
 }
 
 define i64 @test_var32_align64() {
-; CHECK: test_var32_align64:
+; CHECK-LABEL: test_var32_align64:
   %addr = bitcast [3 x i32]* @var32_align64 to i64*
 
   ; Since @var32 is only guaranteed to be aligned to 32-bits, it's invalid to
@@ -49,7 +49,7 @@ define i64 @test_var32_align64() {
 @yet_another_var = external global {i32, i32}
 
 define i64 @test_yet_another_var() {
-; CHECK: test_yet_another_var:
+; CHECK-LABEL: test_yet_another_var:
 
   ; @yet_another_var has a preferred alignment of 8, but that's not enough if
   ; we're going to be linking against other things. Its ABI alignment is only 4
@@ -62,7 +62,7 @@ define i64 @test_yet_another_var() {
 }
 
 define i64()* @test_functions() {
-; CHECK: test_functions:
+; CHECK-LABEL: test_functions:
   ret i64()* @test_yet_another_var
 ; CHECK: adrp [[HIBITS:x[0-9]+]], test_yet_another_var
 ; CHECK: add x0, [[HIBITS]], #:lo12:test_yet_another_var
diff --git a/llvm/test/CodeGen/AArch64/i128-align.ll b/llvm/test/CodeGen/AArch64/i128-align.ll
index f019ea0..8eeaa2f 100644
--- a/llvm/test/CodeGen/AArch64/i128-align.ll
+++ b/llvm/test/CodeGen/AArch64/i128-align.ll
@@ -26,4 +26,4 @@ define i64 @check_field() {
   %diff = sub i64 %endi, %starti
   ret i64 %diff
 ; CHECK: movz x0, #16
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AArch64/init-array.ll b/llvm/test/CodeGen/AArch64/init-array.ll
index d80be8f..3ff1c1a 100644
--- a/llvm/test/CodeGen/AArch64/init-array.ll
+++ b/llvm/test/CodeGen/AArch64/init-array.ll
@@ -6,4 +6,4 @@ define internal void @_GLOBAL__I_a() section ".text.startup" {
 
 @llvm.global_ctors = appending global [1 x { i32, void ()* }] [{ i32, void ()* } { i32 65535, void ()* @_GLOBAL__I_a }]
 
-; CHECK: .section .init_array
\ No newline at end of file
+; CHECK: .section .init_array
diff --git a/llvm/test/CodeGen/AArch64/inline-asm-constraints-badI.ll b/llvm/test/CodeGen/AArch64/inline-asm-constraints-badI.ll
index c39c57f..61bbfc2 100644
--- a/llvm/test/CodeGen/AArch64/inline-asm-constraints-badI.ll
+++ b/llvm/test/CodeGen/AArch64/inline-asm-constraints-badI.ll
@@ -4,4 +4,4 @@ define void @foo() {
   ; Out of range immediate for I.
   call void asm sideeffect "add x0, x0, $0", "I"(i32 4096)
   ret void
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AArch64/inline-asm-constraints-badK.ll b/llvm/test/CodeGen/AArch64/inline-asm-constraints-badK.ll
index 47c5f98..40746e1 100644
--- a/llvm/test/CodeGen/AArch64/inline-asm-constraints-badK.ll
+++ b/llvm/test/CodeGen/AArch64/inline-asm-constraints-badK.ll
@@ -4,4 +4,4 @@ define void @foo() {
   ; 32-bit bitpattern ending in 1101 can't be produced.
   call void asm sideeffect "and w0, w0, $0", "K"(i32 13)
   ret void
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll b/llvm/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll
index 7a5b99e..2c53381 100644
--- a/llvm/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll
+++ b/llvm/test/CodeGen/AArch64/inline-asm-constraints-badK2.ll
@@ -4,4 +4,4 @@ define void @foo() {
   ; 32-bit bitpattern ending in 1101 can't be produced.
   call void asm sideeffect "and w0, w0, $0", "K"(i64 4294967296)
   ret void
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AArch64/inline-asm-constraints-badL.ll b/llvm/test/CodeGen/AArch64/inline-asm-constraints-badL.ll
index 4f00398..d82d5a2 100644
--- a/llvm/test/CodeGen/AArch64/inline-asm-constraints-badL.ll
+++ b/llvm/test/CodeGen/AArch64/inline-asm-constraints-badL.ll
@@ -4,4 +4,4 @@ define void @foo() {
   ; 32-bit bitpattern ending in 1101 can't be produced.
   call void asm sideeffect "and x0, x0, $0", "L"(i32 13)
   ret void
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AArch64/inline-asm-constraints.ll b/llvm/test/CodeGen/AArch64/inline-asm-constraints.ll
index c232f32..cfa06a4 100644
--- a/llvm/test/CodeGen/AArch64/inline-asm-constraints.ll
+++ b/llvm/test/CodeGen/AArch64/inline-asm-constraints.ll
@@ -1,21 +1,21 @@
 ; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
 
 define i64 @test_inline_constraint_r(i64 %base, i32 %offset) {
-; CHECK: test_inline_constraint_r:
+; CHECK-LABEL: test_inline_constraint_r:
   %val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 %base, i32 %offset)
 ; CHECK: add {{x[0-9]+}}, {{x[0-9]+}}, {{w[0-9]+}}, sxtw
   ret i64 %val
 }
 
 define i16 @test_small_reg(i16 %lhs, i16 %rhs) {
-; CHECK: test_small_reg:
+; CHECK-LABEL: test_small_reg:
   %val = call i16 asm sideeffect "add $0, $1, $2, sxth", "=r,r,r"(i16 %lhs, i16 %rhs)
 ; CHECK: add {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}}, sxth
   ret i16 %val
 }
 
 define i64 @test_inline_constraint_r_imm(i64 %base, i32 %offset) {
-; CHECK: test_inline_constraint_r_imm:
+; CHECK-LABEL: test_inline_constraint_r_imm:
   %val = call i64 asm "add $0, $1, $2, sxtw", "=r,r,r"(i64 4, i32 12)
 ; CHECK: movz [[FOUR:x[0-9]+]], #4
 ; CHECK: movz [[TWELVE:w[0-9]+]], #12
@@ -26,7 +26,7 @@ define i64 @test_inline_constraint_r_imm(i64 %base, i32 %offset) {
 ; m is permitted to have a base/offset form. We don't do that
 ; currently though.
 define i32 @test_inline_constraint_m(i32 *%ptr) {
-; CHECK: test_inline_constraint_m:
+; CHECK-LABEL: test_inline_constraint_m:
   %val = call i32 asm "ldr $0, $1", "=r,m"(i32 *%ptr)
 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
   ret i32 %val
@@ -36,7 +36,7 @@ define i32 @test_inline_constraint_m(i32 *%ptr) {
 
 ; Q should *never* have base/offset form even if given the chance.
 define i32 @test_inline_constraint_Q(i32 *%ptr) {
-; CHECK: test_inline_constraint_Q:
+; CHECK-LABEL: test_inline_constraint_Q:
   %val = call i32 asm "ldr $0, $1", "=r,Q"(i32* getelementptr([8 x i32]* @arr, i32 0, i32 1))
 ; CHECK: ldr {{w[0-9]+}}, [{{x[0-9]+}}]
   ret i32 %val
@@ -45,7 +45,7 @@ define i32 @test_inline_constraint_Q(i32 *%ptr) {
 @dump = global fp128 zeroinitializer
 
 define void @test_inline_constraint_I() {
-; CHECK: test_inline_constraint_I:
+; CHECK-LABEL: test_inline_constraint_I:
   call void asm sideeffect "add x0, x0, $0", "I"(i32 0)
   call void asm sideeffect "add x0, x0, $0", "I"(i64 4095)
 ; CHECK: add x0, x0, #0
@@ -57,7 +57,7 @@ define void @test_inline_constraint_I() {
 ; Skip J because it's useless
 
 define void @test_inline_constraint_K() {
-; CHECK: test_inline_constraint_K:
+; CHECK-LABEL: test_inline_constraint_K:
   call void asm sideeffect "and w0, w0, $0", "K"(i32 2863311530) ; = 0xaaaaaaaa
   call void asm sideeffect "and w0, w0, $0", "K"(i32 65535)
 ; CHECK: and w0, w0, #-1431655766
@@ -67,7 +67,7 @@ define void @test_inline_constraint_K() {
 }
 
 define void @test_inline_constraint_L() {
-; CHECK: test_inline_constraint_L:
+; CHECK-LABEL: test_inline_constraint_L:
   call void asm sideeffect "and x0, x0, $0", "L"(i64 4294967296) ; = 0xaaaaaaaa
   call void asm sideeffect "and x0, x0, $0", "L"(i64 65535)
 ; CHECK: and x0, x0, #4294967296
@@ -81,7 +81,7 @@ define void @test_inline_constraint_L() {
 @var = global i32 0
 
 define void @test_inline_constraint_S() {
-; CHECK: test_inline_constraint_S:
+; CHECK-LABEL: test_inline_constraint_S:
   call void asm sideeffect "adrp x0, $0", "S"(i32* @var)
   call void asm sideeffect "adrp x0, ${0:A}", "S"(i32* @var)
   call void asm sideeffect "add x0, x0, ${0:L}", "S"(i32* @var)
@@ -92,7 +92,7 @@ define void @test_inline_constraint_S() {
 }
 
 define i32 @test_inline_constraint_S_label(i1 %in) {
-; CHECK: test_inline_constraint_S_label:
+; CHECK-LABEL: test_inline_constraint_S_label:
   call void asm sideeffect "adr x0, $0", "S"(i8* blockaddress(@test_inline_constraint_S_label, %loc))
 ; CHECK: adr x0, .Ltmp{{[0-9]+}}
   br i1 %in, label %loc, label %loc2
@@ -103,15 +103,15 @@ loc2:
 }
 
 define void @test_inline_constraint_Y() {
-; CHECK: test_inline_constraint_Y:
+; CHECK-LABEL: test_inline_constraint_Y:
   call void asm sideeffect "fcmp s0, $0", "Y"(float 0.0)
 ; CHECK: fcmp s0, #0.0
   ret void
 }
 
 define void @test_inline_constraint_Z() {
-; CHECK: test_inline_constraint_Z:
+; CHECK-LABEL: test_inline_constraint_Z:
   call void asm sideeffect "cmp w0, $0", "Z"(i32 0)
 ; CHECK: cmp w0, #0
   ret void
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AArch64/inline-asm-modifiers.ll b/llvm/test/CodeGen/AArch64/inline-asm-modifiers.ll
index 3b55945..d1b21f8 100644
--- a/llvm/test/CodeGen/AArch64/inline-asm-modifiers.ll
+++ b/llvm/test/CodeGen/AArch64/inline-asm-modifiers.ll
@@ -9,7 +9,7 @@
 @var_tlsle = thread_local(localexec) global i32 0
 
 define void @test_inline_modifier_L() nounwind {
-; CHECK: test_inline_modifier_L:
+; CHECK-LABEL: test_inline_modifier_L:
   call void asm sideeffect "add x0, x0, ${0:L}", "S,~{x0}"(i32* @var_simple)
   call void asm sideeffect "ldr x0, [x0, ${0:L}]", "S,~{x0}"(i32* @var_got)
   call void asm sideeffect "add x0, x0, ${0:L}", "S,~{x0}"(i32* @var_tlsgd)
@@ -34,7 +34,7 @@ define void @test_inline_modifier_L() nounwind {
 }
 
 define void @test_inline_modifier_G() nounwind {
-; CHECK: test_inline_modifier_G:
+; CHECK-LABEL: test_inline_modifier_G:
   call void asm sideeffect "add x0, x0, ${0:G}, lsl #12", "S,~{x0}"(i32* @var_tlsld)
   call void asm sideeffect "add x0, x0, ${0:G}, lsl #12", "S,~{x0}"(i32* @var_tlsle)
 ; CHECK: add x0, x0, #:dtprel_hi12:var_tlsld, lsl #12
@@ -47,7 +47,7 @@ define void @test_inline_modifier_G() nounwind {
 }
 
 define void @test_inline_modifier_A() nounwind {
-; CHECK: test_inline_modifier_A:
+; CHECK-LABEL: test_inline_modifier_A:
   call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_simple)
   call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_got)
   call void asm sideeffect "adrp x0, ${0:A}", "S,~{x0}"(i32* @var_tlsgd)
@@ -67,7 +67,7 @@ define void @test_inline_modifier_A() nounwind {
 }
 
 define void @test_inline_modifier_wx(i32 %small, i64 %big) nounwind {
-; CHECK: test_inline_modifier_wx:
+; CHECK-LABEL: test_inline_modifier_wx:
   call i32 asm sideeffect "add $0, $0, $0", "=r,0"(i32 %small)
   call i32 asm sideeffect "add ${0:w}, ${0:w}, ${0:w}", "=r,0"(i32 %small)
   call i32 asm sideeffect "add ${0:x}, ${0:x}, ${0:x}", "=r,0"(i32 %small)
@@ -91,7 +91,7 @@ define void @test_inline_modifier_wx(i32 %small, i64 %big) nounwind {
 }
 
 define void @test_inline_modifier_bhsdq() nounwind {
-; CHECK: test_inline_modifier_bhsdq:
+; CHECK-LABEL: test_inline_modifier_bhsdq:
   call float asm sideeffect "ldr ${0:b}, [sp]", "=w"()
   call float asm sideeffect "ldr ${0:h}, [sp]", "=w"()
   call float asm sideeffect "ldr ${0:s}, [sp]", "=w"()
@@ -117,9 +117,9 @@ define void @test_inline_modifier_bhsdq() nounwind {
 }
 
 define void @test_inline_modifier_c() nounwind {
-; CHECK: test_inline_modifier_c:
+; CHECK-LABEL: test_inline_modifier_c:
   call void asm sideeffect "adr x0, ${0:c}", "i"(i32 3)
 ; CHECK: adr x0, 3
 
   ret void
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AArch64/large-frame.ll b/llvm/test/CodeGen/AArch64/large-frame.ll
index 690b21d..fde3036 100644
--- a/llvm/test/CodeGen/AArch64/large-frame.ll
+++ b/llvm/test/CodeGen/AArch64/large-frame.ll
@@ -4,7 +4,7 @@ declare void @use_addr(i8*)
 @addr = global i8* null
 
 define void @test_bigframe() {
-; CHECK: test_bigframe:
+; CHECK-LABEL: test_bigframe:
 ; CHECK: .cfi_startproc
 
   %var1 = alloca i8, i32 20000000
@@ -50,7 +50,7 @@ define void @test_bigframe() {
 }
 
 define void @test_mediumframe() {
-; CHECK: test_mediumframe:
+; CHECK-LABEL: test_mediumframe:
   %var1 = alloca i8, i32 1000000
   %var2 = alloca i8, i32 16
   %var3 = alloca i8, i32 1000000
@@ -93,7 +93,7 @@ define void @test_mediumframe() {
 ; If temporary registers are allocated for adjustment, they should *not* clobber
 ; argument registers.
 define void @test_tempallocation([8 x i64] %val) nounwind {
-; CHECK: test_tempallocation:
+; CHECK-LABEL: test_tempallocation:
   %var = alloca i8, i32 1000000
 ; CHECK: sub sp, sp,
 
diff --git a/llvm/test/CodeGen/AArch64/logical-imm.ll b/llvm/test/CodeGen/AArch64/logical-imm.ll
index 5f3f4da..e04bb51 100644
--- a/llvm/test/CodeGen/AArch64/logical-imm.ll
+++ b/llvm/test/CodeGen/AArch64/logical-imm.ll
@@ -4,7 +4,7 @@
 @var64 = global i64 0
 
 define void @test_and(i32 %in32, i64 %in64) {
-; CHECK: test_and:
+; CHECK-LABEL: test_and:
 
   %val0 = and i32 %in32, 2863311530
   store volatile i32 %val0, i32* @var32
@@ -26,7 +26,7 @@ define void @test_and(i32 %in32, i64 %in64) {
 }
 
 define void @test_orr(i32 %in32, i64 %in64) {
-; CHECK: test_orr:
+; CHECK-LABEL: test_orr:
 
   %val0 = or i32 %in32, 2863311530
   store volatile i32 %val0, i32* @var32
@@ -48,7 +48,7 @@ define void @test_orr(i32 %in32, i64 %in64) {
 }
 
 define void @test_eor(i32 %in32, i64 %in64) {
-; CHECK: test_eor:
+; CHECK-LABEL: test_eor:
 
   %val0 = xor i32 %in32, 2863311530
   store volatile i32 %val0, i32* @var32
@@ -70,7 +70,7 @@ define void @test_eor(i32 %in32, i64 %in64) {
 }
 
 define void @test_mov(i32 %in32, i64 %in64) {
-; CHECK: test_mov:
+; CHECK-LABEL: test_mov:
   %val0 = add i32 %in32, 2863311530
   store i32 %val0, i32* @var32
 ; CHECK: orr {{w[0-9]+}}, wzr, #0xaaaaaaaa
diff --git a/llvm/test/CodeGen/AArch64/movw-consts.ll b/llvm/test/CodeGen/AArch64/movw-consts.ll
index b8a5fb9..38e37db 100644
--- a/llvm/test/CodeGen/AArch64/movw-consts.ll
+++ b/llvm/test/CodeGen/AArch64/movw-consts.ll
@@ -1,50 +1,50 @@
 ; RUN: llc -verify-machineinstrs -O0 < %s -mtriple=aarch64-none-linux-gnu | FileCheck %s
 
 define i64 @test0() {
-; CHECK: test0:
+; CHECK-LABEL: test0:
 ; Not produced by move wide instructions, but good to make sure we can return 0 anyway:
 ; CHECK: mov x0, xzr
   ret i64 0
 }
 
 define i64 @test1() {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: movz x0, #1
   ret i64 1
 }
 
 define i64 @test2() {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movz x0, #65535
   ret i64 65535
 }
 
 define i64 @test3() {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: movz x0, #1, lsl #16
   ret i64 65536
 }
 
 define i64 @test4() {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: movz x0, #65535, lsl #16
   ret i64 4294901760
 }
 
 define i64 @test5() {
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: movz x0, #1, lsl #32
   ret i64 4294967296
 }
 
 define i64 @test6() {
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: movz x0, #65535, lsl #32
   ret i64 281470681743360
 }
 
 define i64 @test7() {
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: movz x0, #1, lsl #48
   ret i64 281474976710656
 }
@@ -52,19 +52,19 @@ define i64 @test7() {
 ; A 32-bit MOVN can generate some 64-bit patterns that a 64-bit one
 ; couldn't. Useful even for i64
 define i64 @test8() {
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: movn w0, #60875
   ret i64 4294906420
 }
 
 define i64 @test9() {
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: movn x0, #0
   ret i64 -1
 }
 
 define i64 @test10() {
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: movn x0, #60875, lsl #16
   ret i64 18446744069720047615
 }
@@ -74,49 +74,49 @@ define i64 @test10() {
 @var32 = global i32 0
 
 define void @test11() {
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK: mov {{w[0-9]+}}, wzr
   store i32 0, i32* @var32
   ret void
 }
 
 define void @test12() {
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK: movz {{w[0-9]+}}, #1
   store i32 1, i32* @var32
   ret void
 }
 
 define void @test13() {
-; CHECK: test13:
+; CHECK-LABEL: test13:
 ; CHECK: movz {{w[0-9]+}}, #65535
   store i32 65535, i32* @var32
   ret void
 }
 
 define void @test14() {
-; CHECK: test14:
+; CHECK-LABEL: test14:
 ; CHECK: movz {{w[0-9]+}}, #1, lsl #16
   store i32 65536, i32* @var32
   ret void
 }
 
 define void @test15() {
-; CHECK: test15:
+; CHECK-LABEL: test15:
 ; CHECK: movz {{w[0-9]+}}, #65535, lsl #16
   store i32 4294901760, i32* @var32
   ret void
 }
 
 define void @test16() {
-; CHECK: test16:
+; CHECK-LABEL: test16:
 ; CHECK: movn {{w[0-9]+}}, #0
   store i32 -1, i32* @var32
   ret void
 }
 
 define i64 @test17() {
-; CHECK: test17:
+; CHECK-LABEL: test17:
 
   ; Mustn't MOVN w0 here.
 ; CHECK: movn x0, #2
diff --git a/llvm/test/CodeGen/AArch64/pic-eh-stubs.ll b/llvm/test/CodeGen/AArch64/pic-eh-stubs.ll
index 77bf691..6ec4b19 100644
--- a/llvm/test/CodeGen/AArch64/pic-eh-stubs.ll
+++ b/llvm/test/CodeGen/AArch64/pic-eh-stubs.ll
@@ -57,4 +57,4 @@ declare i32 @llvm.eh.typeid.for(i8*) nounwind readnone
 
 declare i8* @__cxa_begin_catch(i8*)
 
-declare void @__cxa_end_catch()
\ No newline at end of file
+declare void @__cxa_end_catch()
diff --git a/llvm/test/CodeGen/AArch64/regress-bitcast-formals.ll b/llvm/test/CodeGen/AArch64/regress-bitcast-formals.ll
index 28dc9a7..9655f90 100644
--- a/llvm/test/CodeGen/AArch64/regress-bitcast-formals.ll
+++ b/llvm/test/CodeGen/AArch64/regress-bitcast-formals.ll
@@ -4,7 +4,7 @@
 ; actually capable of that (the test was omitted from LowerFormalArguments).
 
 define void @test_bitcast_lower(<2 x i32> %a) {
-; CHECK: test_bitcast_lower:
+; CHECK-LABEL: test_bitcast_lower:
 
   ret void
 ; CHECK: ret
diff --git a/llvm/test/CodeGen/AArch64/regress-tail-livereg.ll b/llvm/test/CodeGen/AArch64/regress-tail-livereg.ll
index 8d5485c..3216775 100644
--- a/llvm/test/CodeGen/AArch64/regress-tail-livereg.ll
+++ b/llvm/test/CodeGen/AArch64/regress-tail-livereg.ll
@@ -16,4 +16,4 @@ define void @foo() {
        tail call void %func()
 ; CHECK: br {{x([0-79]|1[0-8])}}
        ret void
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll b/llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll
index e54552f..ff77fb4 100644
--- a/llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll
+++ b/llvm/test/CodeGen/AArch64/regress-tblgen-chains.ll
@@ -12,7 +12,7 @@
 declare void @bar(i8*)
 
 define i64 @test_chains() {
-; CHECK: test_chains:
+; CHECK-LABEL: test_chains:
 
   %locvar = alloca i8
 
diff --git a/llvm/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll b/llvm/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
index 9176651..0ef9818 100644
--- a/llvm/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
+++ b/llvm/test/CodeGen/AArch64/regress-w29-reserved-with-fp.ll
@@ -4,7 +4,7 @@
 declare void @bar()
 
 define void @test_w29_reserved() {
-; CHECK: test_w29_reserved:
+; CHECK-LABEL: test_w29_reserved:
 ; CHECK: .cfi_startproc
 ; CHECK: .cfi_def_cfa sp, 96
 ; CHECK: add x29, sp, #{{[0-9]+}}
diff --git a/llvm/test/CodeGen/AArch64/setcc-takes-i32.ll b/llvm/test/CodeGen/AArch64/setcc-takes-i32.ll
index d2eb77a..bd79685 100644
--- a/llvm/test/CodeGen/AArch64/setcc-takes-i32.ll
+++ b/llvm/test/CodeGen/AArch64/setcc-takes-i32.ll
@@ -12,11 +12,11 @@
 declare {i64, i1} @llvm.umul.with.overflow.i64(i64, i64)
 
 define i64 @test_select(i64 %lhs, i64 %rhs) {
-; CHECK: test_select:
+; CHECK-LABEL: test_select:
 
   %res = call {i64, i1} @llvm.umul.with.overflow.i64(i64 %lhs, i64 %rhs)
   %flag = extractvalue {i64, i1} %res, 1
   %retval = select i1 %flag, i64 %lhs, i64 %rhs
   ret i64 %retval
 ; CHECK: ret
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/AArch64/sincos-expansion.ll b/llvm/test/CodeGen/AArch64/sincos-expansion.ll
index f1b7441..4cd4449 100644
--- a/llvm/test/CodeGen/AArch64/sincos-expansion.ll
+++ b/llvm/test/CodeGen/AArch64/sincos-expansion.ll
@@ -32,4 +32,4 @@ declare double @sin(double) readonly
 declare fp128 @sinl(fp128) readonly
 declare float @cosf(float) readonly
 declare double @cos(double) readonly
-declare fp128 @cosl(fp128) readonly
\ No newline at end of file
+declare fp128 @cosl(fp128) readonly
diff --git a/llvm/test/CodeGen/AArch64/tls-dynamic-together.ll b/llvm/test/CodeGen/AArch64/tls-dynamic-together.ll
index bad2298..b5d7d89 100644
--- a/llvm/test/CodeGen/AArch64/tls-dynamic-together.ll
+++ b/llvm/test/CodeGen/AArch64/tls-dynamic-together.ll
@@ -8,7 +8,7 @@
 @general_dynamic_var = external thread_local global i32
 
 define i32 @test_generaldynamic() {
-; CHECK: test_generaldynamic:
+; CHECK-LABEL: test_generaldynamic:
 
   %val = load i32* @general_dynamic_var
   ret i32 %val
diff --git a/llvm/test/CodeGen/AArch64/tls-dynamics.ll b/llvm/test/CodeGen/AArch64/tls-dynamics.ll
index cdfd117..887d2f8 100644
--- a/llvm/test/CodeGen/AArch64/tls-dynamics.ll
+++ b/llvm/test/CodeGen/AArch64/tls-dynamics.ll
@@ -4,7 +4,7 @@
 @general_dynamic_var = external thread_local global i32
 
 define i32 @test_generaldynamic() {
-; CHECK: test_generaldynamic:
+; CHECK-LABEL: test_generaldynamic:
 
   %val = load i32* @general_dynamic_var
   ret i32 %val
@@ -26,7 +26,7 @@ define i32 @test_generaldynamic() {
 }
 
 define i32* @test_generaldynamic_addr() {
-; CHECK: test_generaldynamic_addr:
+; CHECK-LABEL: test_generaldynamic_addr:
 
   ret i32* @general_dynamic_var
 
@@ -49,7 +49,7 @@ define i32* @test_generaldynamic_addr() {
 @local_dynamic_var = external thread_local(localdynamic) global i32
 
 define i32 @test_localdynamic() {
-; CHECK: test_localdynamic:
+; CHECK-LABEL: test_localdynamic:
 
   %val = load i32* @local_dynamic_var
   ret i32 %val
@@ -73,7 +73,7 @@ define i32 @test_localdynamic() {
 }
 
 define i32* @test_localdynamic_addr() {
-; CHECK: test_localdynamic_addr:
+; CHECK-LABEL: test_localdynamic_addr:
 
   ret i32* @local_dynamic_var
 
@@ -101,7 +101,7 @@ define i32* @test_localdynamic_addr() {
 @local_dynamic_var2 = external thread_local(localdynamic) global i32
 
 define i32 @test_localdynamic_deduplicate() {
-; CHECK: test_localdynamic_deduplicate:
+; CHECK-LABEL: test_localdynamic_deduplicate:
 
   %val = load i32* @local_dynamic_var
   %val2 = load i32* @local_dynamic_var2
diff --git a/llvm/test/CodeGen/AArch64/tls-execs.ll b/llvm/test/CodeGen/AArch64/tls-execs.ll
index a665884..5bb9e32 100644
--- a/llvm/test/CodeGen/AArch64/tls-execs.ll
+++ b/llvm/test/CodeGen/AArch64/tls-execs.ll
@@ -4,7 +4,7 @@
 @initial_exec_var = external thread_local(initialexec) global i32
 
 define i32 @test_initial_exec() {
-; CHECK: test_initial_exec:
+; CHECK-LABEL: test_initial_exec:
   %val = load i32* @initial_exec_var
 
 ; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var
@@ -19,7 +19,7 @@ define i32 @test_initial_exec() {
 }
 
 define i32* @test_initial_exec_addr() {
-; CHECK: test_initial_exec_addr:
+; CHECK-LABEL: test_initial_exec_addr:
   ret i32* @initial_exec_var
 
 ; CHECK: adrp x[[GOTADDR:[0-9]+]], :gottprel:initial_exec_var
@@ -35,7 +35,7 @@ define i32* @test_initial_exec_addr() {
 @local_exec_var = thread_local(initialexec) global i32 0
 
 define i32 @test_local_exec() {
-; CHECK: test_local_exec:
+; CHECK-LABEL: test_local_exec:
   %val = load i32* @local_exec_var
 
 ; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var
@@ -50,7 +50,7 @@ define i32 @test_local_exec() {
 }
 
 define i32* @test_local_exec_addr() {
-; CHECK: test_local_exec_addr:
+; CHECK-LABEL: test_local_exec_addr:
   ret i32* @local_exec_var
 
 ; CHECK: movz [[TP_OFFSET:x[0-9]+]], #:tprel_g1:local_exec_var
diff --git a/llvm/test/CodeGen/AArch64/tst-br.ll b/llvm/test/CodeGen/AArch64/tst-br.ll
index 65c1fda..154bc08 100644
--- a/llvm/test/CodeGen/AArch64/tst-br.ll
+++ b/llvm/test/CodeGen/AArch64/tst-br.ll
@@ -7,7 +7,7 @@
 @var64 = global i64 0
 
 define i32 @test_tbz() {
-; CHECK: test_tbz:
+; CHECK-LABEL: test_tbz:
 
   %val = load i32* @var32
   %val64 = load i64* @var64
diff --git a/llvm/test/CodeGen/AArch64/variadic.ll b/llvm/test/CodeGen/AArch64/variadic.ll
index c5d319e..1c7e3bf 100644
--- a/llvm/test/CodeGen/AArch64/variadic.ll
+++ b/llvm/test/CodeGen/AArch64/variadic.ll
@@ -7,7 +7,7 @@
 declare void @llvm.va_start(i8*)
 
 define void @test_simple(i32 %n, ...) {
-; CHECK: test_simple:
+; CHECK-LABEL: test_simple:
 ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
 ; CHECK: mov x[[FPRBASE:[0-9]+]], sp
 ; CHECK: str q7, [x[[FPRBASE]], #112]
@@ -37,7 +37,7 @@ define void @test_simple(i32 %n, ...) {
 }
 
 define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
-; CHECK: test_fewargs:
+; CHECK-LABEL: test_fewargs:
 ; CHECK: sub sp, sp, #[[STACKSIZE:[0-9]+]]
 ; CHECK: mov x[[FPRBASE:[0-9]+]], sp
 ; CHECK: str q7, [x[[FPRBASE]], #96]
@@ -67,7 +67,7 @@ define void @test_fewargs(i32 %n, i32 %n1, i32 %n2, float %m, ...) {
 }
 
 define void @test_nospare([8 x i64], [8 x float], ...) {
-; CHECK: test_nospare:
+; CHECK-LABEL: test_nospare:
 
   %addr = bitcast %va_list* @var to i8*
   call void @llvm.va_start(i8* %addr)
@@ -81,7 +81,7 @@ define void @test_nospare([8 x i64], [8 x float], ...) {
 ; If there are non-variadic arguments on the stack (here two i64s) then the
 ; __stack field should point just past them.
 define void @test_offsetstack([10 x i64], [3 x float], ...) {
-; CHECK: test_offsetstack:
+; CHECK-LABEL: test_offsetstack:
 ; CHECK: sub sp, sp, #80
 ; CHECK: mov x[[FPRBASE:[0-9]+]], sp
 ; CHECK: str q7, [x[[FPRBASE]], #64]
@@ -108,7 +108,7 @@ define void @test_offsetstack([10 x i64], [3 x float], ...) {
 declare void @llvm.va_end(i8*)
 
 define void @test_va_end() nounwind {
-; CHECK: test_va_end:
+; CHECK-LABEL: test_va_end:
 ; CHECK-NEXT: BB#0
 
   %addr = bitcast %va_list* @var to i8*
@@ -123,7 +123,7 @@ declare void @llvm.va_copy(i8* %dest, i8* %src)
 @second_list = global %va_list zeroinitializer
 
 define void @test_va_copy() {
-; CHECK: test_va_copy:
+; CHECK-LABEL: test_va_copy:
   %srcaddr = bitcast %va_list* @var to i8*
   %dstaddr = bitcast %va_list* @second_list to i8*
   call void @llvm.va_copy(i8* %dstaddr, i8* %srcaddr)
diff --git a/llvm/test/CodeGen/AArch64/zero-reg.ll b/llvm/test/CodeGen/AArch64/zero-reg.ll
index fef0437..9b1e527 100644
--- a/llvm/test/CodeGen/AArch64/zero-reg.ll
+++ b/llvm/test/CodeGen/AArch64/zero-reg.ll
@@ -4,7 +4,7 @@
 @var64 = global i64 0
 
 define void @test_zr() {
-; CHECK: test_zr:
+; CHECK-LABEL: test_zr:
 
   store i32 0, i32* @var32
 ; CHECK: str wzr, [{{x[0-9]+}}, #:lo12:var32]
@@ -16,7 +16,7 @@ define void @test_zr() {
 }
 
 define void @test_sp(i32 %val) {
-; CHECK: test_sp:
+; CHECK-LABEL: test_sp:
 
 ; Important correctness point here is that LLVM doesn't try to use xzr
 ; as an addressing register: "str w0, [xzr]" is not a valid A64
@@ -28,4 +28,4 @@ define void @test_sp(i32 %val) {
 
   ret void
 ; CHECK: ret
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll b/llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll
index ed7dd03..057c199 100644
--- a/llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll
+++ b/llvm/test/CodeGen/ARM/2011-04-26-SchedTweak.ll
@@ -15,7 +15,7 @@
 
 define i32 @test() nounwind optsize ssp {
 entry:
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: push
 ; CHECK-NOT: push
   %block_size = alloca i32, align 4
diff --git a/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll b/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
index 113cbfe..8a65f2e 100644
--- a/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
+++ b/llvm/test/CodeGen/ARM/2011-11-07-PromoteVectorLoadStore.ll
@@ -6,7 +6,7 @@
 @i8_src2 = global <2 x i8> <i8 2, i8 1>
 
 define void @test_neon_vector_add_2xi8() nounwind {
-; CHECK: test_neon_vector_add_2xi8:
+; CHECK-LABEL: test_neon_vector_add_2xi8:
   %1 = load <2 x i8>* @i8_src1
   %2 = load <2 x i8>* @i8_src2
   %3 = add <2 x i8> %1, %2
@@ -15,7 +15,7 @@ define void @test_neon_vector_add_2xi8() nounwind {
 }
 
 define void @test_neon_ld_st_volatile_with_ashr_2xi8() {
-; CHECK: test_neon_ld_st_volatile_with_ashr_2xi8:
+; CHECK-LABEL: test_neon_ld_st_volatile_with_ashr_2xi8:
   %1 = load volatile <2 x i8>* @i8_src1
   %2 = load volatile <2 x i8>* @i8_src2
   %3 = ashr <2 x i8> %1, %2
diff --git a/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll b/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll
index 2ab6a4f..42eb32d 100644
--- a/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll
+++ b/llvm/test/CodeGen/ARM/2011-11-09-BitcastVectorDouble.ll
@@ -7,7 +7,7 @@
 declare <2 x i16> @foo_v2i16(<2 x i16>) nounwind
 
 define void @test_neon_call_return_v2i16() {
-; CHECK: test_neon_call_return_v2i16:
+; CHECK-LABEL: test_neon_call_return_v2i16:
   %1 = load <2 x i16>* @src1_v2i16
   %2 = call <2 x i16> @foo_v2i16(<2 x i16> %1) nounwind
   store <2 x i16> %2, <2 x i16>* @res_v2i16
diff --git a/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll b/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
index 0d0d03b..a263c9c 100644
--- a/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
+++ b/llvm/test/CodeGen/ARM/2011-11-29-128bitArithmetics.ll
@@ -4,7 +4,7 @@
 
 define void @test_sqrt(<4 x float>* %X) nounwind {
 
-; CHECK: test_sqrt:
+; CHECK-LABEL: test_sqrt:
 
 ; CHECK:      movw    r1, :lower16:{{.*}}
 ; CHECK:      movt    r1, :upper16:{{.*}}
@@ -27,7 +27,7 @@ declare <4 x float> @llvm.sqrt.v4f32(<4 x float>) nounwind readonly
 
 define void @test_cos(<4 x float>* %X) nounwind {
 
-; CHECK: test_cos:
+; CHECK-LABEL: test_cos:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
@@ -58,7 +58,7 @@ declare <4 x float> @llvm.cos.v4f32(<4 x float>) nounwind readonly
 
 define void @test_exp(<4 x float>* %X) nounwind {
 
-; CHECK: test_exp:
+; CHECK-LABEL: test_exp:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
@@ -89,7 +89,7 @@ declare <4 x float> @llvm.exp.v4f32(<4 x float>) nounwind readonly
 
 define void @test_exp2(<4 x float>* %X) nounwind {
 
-; CHECK: test_exp2:
+; CHECK-LABEL: test_exp2:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
@@ -120,7 +120,7 @@ declare <4 x float> @llvm.exp2.v4f32(<4 x float>) nounwind readonly
 
 define void @test_log10(<4 x float>* %X) nounwind {
 
-; CHECK: test_log10:
+; CHECK-LABEL: test_log10:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
@@ -151,7 +151,7 @@ declare <4 x float> @llvm.log10.v4f32(<4 x float>) nounwind readonly
 
 define void @test_log(<4 x float>* %X) nounwind {
 
-; CHECK: test_log:
+; CHECK-LABEL: test_log:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
@@ -182,7 +182,7 @@ declare <4 x float> @llvm.log.v4f32(<4 x float>) nounwind readonly
 
 define void @test_log2(<4 x float>* %X) nounwind {
 
-; CHECK: test_log2:
+; CHECK-LABEL: test_log2:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
@@ -214,7 +214,7 @@ declare <4 x float> @llvm.log2.v4f32(<4 x float>) nounwind readonly
 
 define void @test_pow(<4 x float>* %X) nounwind {
 
-; CHECK: test_pow:
+; CHECK-LABEL: test_pow:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
@@ -248,7 +248,7 @@ declare <4 x float> @llvm.pow.v4f32(<4 x float>, <4 x float>) nounwind readonly
 
 define void @test_powi(<4 x float>* %X) nounwind {
 
-; CHECK: test_powi:
+; CHECK-LABEL: test_powi:
 
 ; CHECK:       movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:       movt  [[reg0]], :upper16:{{.*}}
@@ -271,7 +271,7 @@ declare <4 x float> @llvm.powi.v4f32(<4 x float>, i32) nounwind readonly
 
 define void @test_sin(<4 x float>* %X) nounwind {
 
-; CHECK: test_sin:
+; CHECK-LABEL: test_sin:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
@@ -302,7 +302,7 @@ declare <4 x float> @llvm.sin.v4f32(<4 x float>) nounwind readonly
 
 define void @test_floor(<4 x float>* %X) nounwind {
 
-; CHECK: test_floor:
+; CHECK-LABEL: test_floor:
 
 ; CHECK:      movw  [[reg0:r[0-9]+]], :lower16:{{.*}}
 ; CHECK:      movt  [[reg0]], :upper16:{{.*}}
diff --git a/llvm/test/CodeGen/ARM/2012-08-09-neon-extload.ll b/llvm/test/CodeGen/ARM/2012-08-09-neon-extload.ll
index 764c58f..a710825 100644
--- a/llvm/test/CodeGen/ARM/2012-08-09-neon-extload.ll
+++ b/llvm/test/CodeGen/ARM/2012-08-09-neon-extload.ll
@@ -12,7 +12,7 @@
 @var_v2i64 = global <2 x i64> zeroinitializer
 
 define void @test_v2i8tov2i32() {
-; CHECK: test_v2i8tov2i32:
+; CHECK-LABEL: test_v2i8tov2i32:
 
   %i8val = load <2 x i8>* @var_v2i8
 
@@ -26,7 +26,7 @@ define void @test_v2i8tov2i32() {
 }
 
 define void @test_v2i8tov2i64() {
-; CHECK: test_v2i8tov2i64:
+; CHECK-LABEL: test_v2i8tov2i64:
 
   %i8val = load <2 x i8>* @var_v2i8
 
@@ -44,7 +44,7 @@ define void @test_v2i8tov2i64() {
 }
 
 define void @test_v4i8tov4i16() {
-; CHECK: test_v4i8tov4i16:
+; CHECK-LABEL: test_v4i8tov4i16:
 
   %i8val = load <4 x i8>* @var_v4i8
 
@@ -59,7 +59,7 @@ define void @test_v4i8tov4i16() {
 }
 
 define void @test_v4i8tov4i32() {
-; CHECK: test_v4i8tov4i32:
+; CHECK-LABEL: test_v4i8tov4i32:
 
   %i8val = load <4 x i8>* @var_v4i8
 
@@ -73,7 +73,7 @@ define void @test_v4i8tov4i32() {
 }
 
 define void @test_v2i16tov2i32() {
-; CHECK: test_v2i16tov2i32:
+; CHECK-LABEL: test_v2i16tov2i32:
 
   %i16val = load <2 x i16>* @var_v2i16
 
@@ -88,7 +88,7 @@ define void @test_v2i16tov2i32() {
 }
 
 define void @test_v2i16tov2i64() {
-; CHECK: test_v2i16tov2i64:
+; CHECK-LABEL: test_v2i16tov2i64:
 
   %i16val = load <2 x i16>* @var_v2i16
 
diff --git a/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll b/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
index e599f43..645e68b 100644
--- a/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
+++ b/llvm/test/CodeGen/ARM/2012-10-04-AAPCS-byval-align8.ll
@@ -7,7 +7,7 @@
 declare void @llvm.va_start(i8*) nounwind
 declare void @llvm.va_end(i8*) nounwind
 
-; CHECK: test_byval_8_bytes_alignment:
+; CHECK-LABEL: test_byval_8_bytes_alignment:
 define void @test_byval_8_bytes_alignment(i32 %i, ...) {
 entry:
 ; CHECK: stm     r0, {r1, r2, r3}
@@ -40,7 +40,7 @@ entry:
 
 declare void @f(double);
 
-; CHECK:     test_byval_8_bytes_alignment_fixed_arg:
+; CHECK-LABEL:     test_byval_8_bytes_alignment_fixed_arg:
 ; CHECK-NOT:   str     r1
 ; CHECK:       str     r3, [sp, #12]
 ; CHECK:       str     r2, [sp, #8]
diff --git a/llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll b/llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
index 478048d..c9ccc10 100644
--- a/llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
+++ b/llvm/test/CodeGen/ARM/2012-10-04-FixedFrame-vs-byval.ll
@@ -6,7 +6,7 @@
 
 declare i32 @printf(i8*, ...)
 
-; CHECK:     test_byval_usage_scheduling:
+; CHECK-LABEL:     test_byval_usage_scheduling:
 ; CHECK:       str     r3, [sp, #12]
 ; CHECK:       str     r2, [sp, #8]
 ; CHECK:       vldr    d16, [sp, #8]
diff --git a/llvm/test/CodeGen/ARM/atomic-64bit.ll b/llvm/test/CodeGen/ARM/atomic-64bit.ll
index 669c563..93664e3 100644
--- a/llvm/test/CodeGen/ARM/atomic-64bit.ll
+++ b/llvm/test/CodeGen/ARM/atomic-64bit.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -mtriple=thumbv7-none-linux-gnueabihf | FileCheck %s --check-prefix=CHECK-THUMB
 
 define i64 @test1(i64* %ptr, i64 %val) {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: adds [[REG3:(r[0-9]?[02468])]], [[REG1]]
@@ -27,7 +27,7 @@ define i64 @test1(i64* %ptr, i64 %val) {
 }
 
 define i64 @test2(i64* %ptr, i64 %val) {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: subs [[REG3:(r[0-9]?[02468])]], [[REG1]]
@@ -52,7 +52,7 @@ define i64 @test2(i64* %ptr, i64 %val) {
 }
 
 define i64 @test3(i64* %ptr, i64 %val) {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: and [[REG3:(r[0-9]?[02468])]], [[REG1]]
@@ -77,7 +77,7 @@ define i64 @test3(i64* %ptr, i64 %val) {
 }
 
 define i64 @test4(i64* %ptr, i64 %val) {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: orr [[REG3:(r[0-9]?[02468])]], [[REG1]]
@@ -102,7 +102,7 @@ define i64 @test4(i64* %ptr, i64 %val) {
 }
 
 define i64 @test5(i64* %ptr, i64 %val) {
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: eor [[REG3:(r[0-9]?[02468])]], [[REG1]]
@@ -127,7 +127,7 @@ define i64 @test5(i64* %ptr, i64 %val) {
 }
 
 define i64 @test6(i64* %ptr, i64 %val) {
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
@@ -148,7 +148,7 @@ define i64 @test6(i64* %ptr, i64 %val) {
 }
 
 define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: cmp [[REG1]]
@@ -178,7 +178,7 @@ define i64 @test7(i64* %ptr, i64 %val1, i64 %val2) {
 ; Compiles down to cmpxchg
 ; FIXME: Should compile to a single ldrexd
 define i64 @test8(i64* %ptr) {
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: cmp [[REG1]]
 ; CHECK: cmpeq [[REG2]]
@@ -206,7 +206,7 @@ define i64 @test8(i64* %ptr) {
 ; Compiles down to atomicrmw xchg; there really isn't any more efficient
 ; way to write it.
 define void @test9(i64* %ptr, i64 %val) {
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: strexd {{[a-z0-9]+}}, {{r[0-9]?[02468]}}, {{r[0-9]?[13579]}}
@@ -227,7 +227,7 @@ define void @test9(i64* %ptr, i64 %val) {
 }
 
 define i64 @test10(i64* %ptr, i64 %val) {
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
@@ -254,7 +254,7 @@ define i64 @test10(i64* %ptr, i64 %val) {
 }
 
 define i64 @test11(i64* %ptr, i64 %val) {
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
@@ -282,7 +282,7 @@ define i64 @test11(i64* %ptr, i64 %val) {
 }
 
 define i64 @test12(i64* %ptr, i64 %val) {
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
@@ -309,7 +309,7 @@ define i64 @test12(i64* %ptr, i64 %val) {
 }
 
 define i64 @test13(i64* %ptr, i64 %val) {
-; CHECK: test13:
+; CHECK-LABEL: test13:
 ; CHECK: dmb {{ish$}}
 ; CHECK: ldrexd [[REG1:(r[0-9]?[02468])]], [[REG2:(r[0-9]?[13579])]]
 ; CHECK: subs {{[a-z0-9]+}}, [[REG1]], [[REG3:(r[0-9]?[02468])]]
diff --git a/llvm/test/CodeGen/ARM/crash-shufflevector.ll b/llvm/test/CodeGen/ARM/crash-shufflevector.ll
index bdc0e0e..0ae8668 100644
--- a/llvm/test/CodeGen/ARM/crash-shufflevector.ll
+++ b/llvm/test/CodeGen/ARM/crash-shufflevector.ll
@@ -7,4 +7,4 @@ define void @f(<4 x i8> %param1, <4 x i8> %param2) {
    %z = shufflevector <16 x i8> %y1, <16 x i8> %y2, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 16, i32 17, i32 18, i32 19>
    call void @g(<16 x i8> %z)
    ret void
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/ARM/dagcombine-concatvector.ll b/llvm/test/CodeGen/ARM/dagcombine-concatvector.ll
index e9e0fe3..d8c6c64 100644
--- a/llvm/test/CodeGen/ARM/dagcombine-concatvector.ll
+++ b/llvm/test/CodeGen/ARM/dagcombine-concatvector.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=thumbv7s-apple-ios3.0.0 | FileCheck %s
 
 ; PR15525
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: ldr.w	[[REG:r[0-9]+]], [sp]
 ; CHECK-NEXT: vmov	{{d[0-9]+}}, r1, r2
 ; CHECK-NEXT: vmov	{{d[0-9]+}}, r3, [[REG]]
diff --git a/llvm/test/CodeGen/ARM/domain-conv-vmovs.ll b/llvm/test/CodeGen/ARM/domain-conv-vmovs.ll
index b5586cc..d6528db 100644
--- a/llvm/test/CodeGen/ARM/domain-conv-vmovs.ll
+++ b/llvm/test/CodeGen/ARM/domain-conv-vmovs.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -verify-machineinstrs -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a9 -mattr=+neon,+neonfp -float-abi=hard < %s | FileCheck %s
 
 define <2 x float> @test_vmovs_via_vext_lane0to0(float %arg, <2 x float> %in) {
-; CHECK: test_vmovs_via_vext_lane0to0:
+; CHECK-LABEL: test_vmovs_via_vext_lane0to0:
   %vec = insertelement <2 x float> %in, float %arg, i32 0
   %res = fadd <2 x float> %vec, %vec
 
@@ -13,7 +13,7 @@ define <2 x float> @test_vmovs_via_vext_lane0to0(float %arg, <2 x float> %in) {
 }
 
 define <2 x float> @test_vmovs_via_vext_lane0to1(float %arg, <2 x float> %in) {
-; CHECK: test_vmovs_via_vext_lane0to1:
+; CHECK-LABEL: test_vmovs_via_vext_lane0to1:
   %vec = insertelement <2 x float> %in, float %arg, i32 1
   %res = fadd <2 x float> %vec, %vec
 
@@ -25,7 +25,7 @@ define <2 x float> @test_vmovs_via_vext_lane0to1(float %arg, <2 x float> %in) {
 }
 
 define <2 x float> @test_vmovs_via_vext_lane1to0(float, float %arg, <2 x float> %in) {
-; CHECK: test_vmovs_via_vext_lane1to0:
+; CHECK-LABEL: test_vmovs_via_vext_lane1to0:
   %vec = insertelement <2 x float> %in, float %arg, i32 0
   %res = fadd <2 x float> %vec, %vec
 
@@ -37,7 +37,7 @@ define <2 x float> @test_vmovs_via_vext_lane1to0(float, float %arg, <2 x float>
 }
 
 define <2 x float> @test_vmovs_via_vext_lane1to1(float, float %arg, <2 x float> %in) {
-; CHECK: test_vmovs_via_vext_lane1to1:
+; CHECK-LABEL: test_vmovs_via_vext_lane1to1:
   %vec = insertelement <2 x float> %in, float %arg, i32 1
   %res = fadd <2 x float> %vec, %vec
 
@@ -50,7 +50,7 @@ define <2 x float> @test_vmovs_via_vext_lane1to1(float, float %arg, <2 x float>
 
 
 define float @test_vmovs_via_vdup(float, float %ret, float %lhs, float %rhs) {
-; CHECK: test_vmovs_via_vdup:
+; CHECK-LABEL: test_vmovs_via_vdup:
 
   ; Do an operation (which will end up NEON because of +neonfp) to convince the
   ; execution-domain pass that NEON is a good thing to use.
@@ -68,7 +68,7 @@ declare void @bar()
 
 ; This is a comp
 define float @test_ineligible(float, float %in) {
-; CHECK: test_ineligible:
+; CHECK-LABEL: test_ineligible:
 
   %sqrt = call float @llvm.sqrt.f32(float %in)
   %val = fadd float %sqrt, %sqrt
@@ -85,7 +85,7 @@ define float @test_ineligible(float, float %in) {
 }
 
 define i32 @test_vmovs_no_sreg(i32 %in) {
-; CHECK: test_vmovs_no_sreg:
+; CHECK-LABEL: test_vmovs_no_sreg:
 
   ; Check that the movement to and from GPRs takes place in the NEON domain.
 ; CHECK: vmov.32 d
diff --git a/llvm/test/CodeGen/ARM/fabs-neon.ll b/llvm/test/CodeGen/ARM/fabs-neon.ll
index 614117f..e3094aa 100644
--- a/llvm/test/CodeGen/ARM/fabs-neon.ll
+++ b/llvm/test/CodeGen/ARM/fabs-neon.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -mtriple=armv7-eabi -float-abi=hard -mcpu=cortex-a8 | FileCheck %s
 
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK:         vabs.f32        q0, q0
 define <4 x float> @test(<4 x float> %a) {
   %foo = call <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
@@ -8,7 +8,7 @@ define <4 x float> @test(<4 x float> %a) {
 }
 declare <4 x float> @llvm.fabs.v4f32(<4 x float> %a)
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK:        vabs.f32        d0, d0
 define <2 x float> @test2(<2 x float> %a) {
   %foo = call <2 x float> @llvm.fabs.v2f32(<2 x float> %a)
diff --git a/llvm/test/CodeGen/ARM/fabss.ll b/llvm/test/CodeGen/ARM/fabss.ll
index c3e00ce..77c21c5 100644
--- a/llvm/test/CodeGen/ARM/fabss.ll
+++ b/llvm/test/CodeGen/ARM/fabss.ll
@@ -13,17 +13,17 @@ entry:
 
 declare float @fabsf(float)
 
-; VFP2: test:
+; VFP2-LABEL: test:
 ; VFP2: 	vabs.f32	s
 
-; NFP1: test:
+; NFP1-LABEL: test:
 ; NFP1: 	vabs.f32	d
-; NFP0: test:
+; NFP0-LABEL: test:
 ; NFP0: 	vabs.f32	s
 
-; CORTEXA8: test:
+; CORTEXA8-LABEL: test:
 ; CORTEXA8:     vadd.f32        [[D1:d[0-9]+]]
 ; CORTEXA8: 	vabs.f32	{{d[0-9]+}}, [[D1]]
 
-; CORTEXA9: test:
+; CORTEXA9-LABEL: test:
 ; CORTEXA9: 	vabs.f32	s{{.}}, s{{.}}
diff --git a/llvm/test/CodeGen/ARM/fadds.ll b/llvm/test/CodeGen/ARM/fadds.ll
index c7e2f5d..21219ce 100644
--- a/llvm/test/CodeGen/ARM/fadds.ll
+++ b/llvm/test/CodeGen/ARM/fadds.ll
@@ -11,17 +11,17 @@ entry:
 	ret float %0
 }
 
-; VFP2: test:
+; VFP2-LABEL: test:
 ; VFP2: 	vadd.f32	s
 
-; NFP1: test:
+; NFP1-LABEL: test:
 ; NFP1: 	vadd.f32	d
-; NFP0: test:
+; NFP0-LABEL: test:
 ; NFP0: 	vadd.f32	s
 
-; CORTEXA8: test:
+; CORTEXA8-LABEL: test:
 ; CORTEXA8: 	vadd.f32	s
-; CORTEXA8U: test:
+; CORTEXA8U-LABEL: test:
 ; CORTEXA8U: 	vadd.f32	d
-; CORTEXA9: test:
+; CORTEXA9-LABEL: test:
 ; CORTEXA9: 	vadd.f32	s
diff --git a/llvm/test/CodeGen/ARM/fast-isel.ll b/llvm/test/CodeGen/ARM/fast-isel.ll
index fd846bd..682fa35 100644
--- a/llvm/test/CodeGen/ARM/fast-isel.ll
+++ b/llvm/test/CodeGen/ARM/fast-isel.ll
@@ -27,16 +27,16 @@ br label %if.end
 
 if.end:                                           ; preds = %if.then, %entry
 ret void
-; ARM: test1:
+; ARM-LABEL: test1:
 ; ARM: tst r0, #1
-; THUMB: test1:
+; THUMB-LABEL: test1:
 ; THUMB: tst.w r0, #1
 }
 
 ; Check some simple operations with immediates
 define void @test2(i32 %tmp, i32* %ptr) nounwind {
-; THUMB: test2:
-; ARM: test2:
+; THUMB-LABEL: test2:
+; ARM-LABEL: test2:
 
 b1:
   %a = add i32 %tmp, 4096
@@ -64,8 +64,8 @@ b3:
 }
 
 define void @test3(i32 %tmp, i32* %ptr1, i16* %ptr2, i8* %ptr3) nounwind {
-; THUMB: test3:
-; ARM: test3:
+; THUMB-LABEL: test3:
+; ARM-LABEL: test3:
 
 bb1:
   %a1 = trunc i32 %tmp to i16
diff --git a/llvm/test/CodeGen/ARM/fcopysign.ll b/llvm/test/CodeGen/ARM/fcopysign.ll
index 5511d24..1de05720 100644
--- a/llvm/test/CodeGen/ARM/fcopysign.ll
+++ b/llvm/test/CodeGen/ARM/fcopysign.ll
@@ -4,11 +4,11 @@
 ; rdar://8984306
 define float @test1(float %x, float %y) nounwind {
 entry:
-; SOFT: test1:
+; SOFT-LABEL: test1:
 ; SOFT: lsr r1, r1, #31
 ; SOFT: bfi r0, r1, #31, #1
 
-; HARD: test1:
+; HARD-LABEL: test1:
 ; HARD: vmov.i32 [[REG1:(d[0-9]+)]], #0x80000000
 ; HARD: vbsl [[REG1]], d
   %0 = tail call float @copysignf(float %x, float %y) nounwind readnone
@@ -17,11 +17,11 @@ entry:
 
 define double @test2(double %x, double %y) nounwind {
 entry:
-; SOFT: test2:
+; SOFT-LABEL: test2:
 ; SOFT: lsr r2, r3, #31
 ; SOFT: bfi r1, r2, #31, #1
 
-; HARD: test2:
+; HARD-LABEL: test2:
 ; HARD: vmov.i32 [[REG2:(d[0-9]+)]], #0x80000000
 ; HARD: vshl.i64 [[REG2]], [[REG2]], #32
 ; HARD: vbsl [[REG2]], d1, d0
@@ -31,7 +31,7 @@ entry:
 
 define double @test3(double %x, double %y, double %z) nounwind {
 entry:
-; SOFT: test3:
+; SOFT-LABEL: test3:
 ; SOFT: vmov.i32 [[REG3:(d[0-9]+)]], #0x80000000
 ; SOFT: vshl.i64 [[REG3]], [[REG3]], #32
 ; SOFT: vbsl [[REG3]],
@@ -43,7 +43,7 @@ entry:
 ; rdar://9287902
 define float @test4() nounwind {
 entry:
-; SOFT: test4:
+; SOFT-LABEL: test4:
 ; SOFT: vmov [[REG7:(d[0-9]+)]], r0, r1
 ; SOFT: vmov.i32 [[REG6:(d[0-9]+)]], #0x80000000
 ; SOFT: vshr.u64 [[REG7]], [[REG7]], #32
diff --git a/llvm/test/CodeGen/ARM/fdivs.ll b/llvm/test/CodeGen/ARM/fdivs.ll
index 8f13f39..a4fecfe 100644
--- a/llvm/test/CodeGen/ARM/fdivs.ll
+++ b/llvm/test/CodeGen/ARM/fdivs.ll
@@ -9,15 +9,15 @@ entry:
 	ret float %0
 }
 
-; VFP2: test:
+; VFP2-LABEL: test:
 ; VFP2: 	vdiv.f32	s{{.}}, s{{.}}, s{{.}}
 
-; NFP1: test:
+; NFP1-LABEL: test:
 ; NFP1: 	vdiv.f32	s{{.}}, s{{.}}, s{{.}}
-; NFP0: test:
+; NFP0-LABEL: test:
 ; NFP0: 	vdiv.f32	s{{.}}, s{{.}}, s{{.}}
 
-; CORTEXA8: test:
+; CORTEXA8-LABEL: test:
 ; CORTEXA8: 	vdiv.f32	s{{.}}, s{{.}}, s{{.}}
-; CORTEXA9: test:
+; CORTEXA9-LABEL: test:
 ; CORTEXA9: 	vdiv.f32	s{{.}}, s{{.}}, s{{.}}
diff --git a/llvm/test/CodeGen/ARM/fmuls.ll b/llvm/test/CodeGen/ARM/fmuls.ll
index f5245c9..d11f6bd 100644
--- a/llvm/test/CodeGen/ARM/fmuls.ll
+++ b/llvm/test/CodeGen/ARM/fmuls.ll
@@ -11,19 +11,19 @@ entry:
 	ret float %0
 }
 
-; VFP2: test:
+; VFP2-LABEL: test:
 ; VFP2: 	vmul.f32	s
 
-; NFP1: test:
+; NFP1-LABEL: test:
 ; NFP1: 	vmul.f32	d
-; NFP0: test:
+; NFP0-LABEL: test:
 ; NFP0: 	vmul.f32	s
 
-; CORTEXA8: test:
+; CORTEXA8-LABEL: test:
 ; CORTEXA8: 	vmul.f32	s
-; CORTEXA8U: test:
+; CORTEXA8U-LABEL: test:
 ; CORTEXA8U: 	vmul.f32	d
-; CORTEXA9: test:
+; CORTEXA9-LABEL: test:
 ; CORTEXA9: 	vmul.f32	s
 
 ; VFP2: test2
diff --git a/llvm/test/CodeGen/ARM/fnegs.ll b/llvm/test/CodeGen/ARM/fnegs.ll
index d84690b..dc4c2e3 100644
--- a/llvm/test/CodeGen/ARM/fnegs.ll
+++ b/llvm/test/CodeGen/ARM/fnegs.ll
@@ -14,22 +14,22 @@ entry:
 	%retval = select i1 %3, float %1, float %0		; <float> [#uses=1]
 	ret float %retval
 }
-; VFP2: test1:
+; VFP2-LABEL: test1:
 ; VFP2: 	vneg.f32	s{{.*}}, s{{.*}}
 
-; NFP1: test1:
+; NFP1-LABEL: test1:
 ; NFP1: 	vneg.f32	d{{.*}}, d{{.*}}
 
-; NFP0: test1:
+; NFP0-LABEL: test1:
 ; NFP0: 	vneg.f32	s{{.*}}, s{{.*}}
 
-; CORTEXA8: test1:
+; CORTEXA8-LABEL: test1:
 ; CORTEXA8: 	vneg.f32	s{{.*}}, s{{.*}}
 
-; CORTEXA8U: test1:
+; CORTEXA8U-LABEL: test1:
 ; CORTEXA8U: 	vneg.f32	d{{.*}}, d{{.*}}
 
-; CORTEXA9: test1:
+; CORTEXA9-LABEL: test1:
 ; CORTEXA9: 	vneg.f32	s{{.*}}, s{{.*}}
 
 define float @test2(float* %a) {
@@ -41,21 +41,21 @@ entry:
 	%retval = select i1 %3, float %1, float %0		; <float> [#uses=1]
 	ret float %retval
 }
-; VFP2: test2:
+; VFP2-LABEL: test2:
 ; VFP2: 	vneg.f32	s{{.*}}, s{{.*}}
 
-; NFP1: test2:
+; NFP1-LABEL: test2:
 ; NFP1: 	vneg.f32	d{{.*}}, d{{.*}}
 
-; NFP0: test2:
+; NFP0-LABEL: test2:
 ; NFP0: 	vneg.f32	s{{.*}}, s{{.*}}
 
-; CORTEXA8: test2:
+; CORTEXA8-LABEL: test2:
 ; CORTEXA8: 	vneg.f32	s{{.*}}, s{{.*}}
 
-; CORTEXA8U: test2:
+; CORTEXA8U-LABEL: test2:
 ; CORTEXA8U: 	vneg.f32	d{{.*}}, d{{.*}}
 
-; CORTEXA9: test2:
+; CORTEXA9-LABEL: test2:
 ; CORTEXA9: 	vneg.f32	s{{.*}}, s{{.*}}
 
diff --git a/llvm/test/CodeGen/ARM/fp_convert.ll b/llvm/test/CodeGen/ARM/fp_convert.ll
index 3c47eb5..f0d9100 100644
--- a/llvm/test/CodeGen/ARM/fp_convert.ll
+++ b/llvm/test/CodeGen/ARM/fp_convert.ll
@@ -6,9 +6,9 @@
 ; RUN: llc < %s -march=arm -mcpu=cortex-a9 | FileCheck %s -check-prefix=VFP2
 
 define i32 @test1(float %a, float %b) {
-; VFP2: test1:
+; VFP2-LABEL: test1:
 ; VFP2: vcvt.s32.f32 s{{.}}, s{{.}}
-; NEON: test1:
+; NEON-LABEL: test1:
 ; NEON: vadd.f32 [[D0:d[0-9]+]]
 ; NEON: vcvt.s32.f32 d0, [[D0]]
 entry:
@@ -18,9 +18,9 @@ entry:
 }
 
 define i32 @test2(float %a, float %b) {
-; VFP2: test2:
+; VFP2-LABEL: test2:
 ; VFP2: vcvt.u32.f32 s{{.}}, s{{.}}
-; NEON: test2:
+; NEON-LABEL: test2:
 ; NEON: vadd.f32 [[D0:d[0-9]+]]
 ; NEON: vcvt.u32.f32 d0, [[D0]]
 entry:
@@ -30,9 +30,9 @@ entry:
 }
 
 define float @test3(i32 %a, i32 %b) {
-; VFP2: test3:
+; VFP2-LABEL: test3:
 ; VFP2: vcvt.f32.u32 s{{.}}, s{{.}}
-; NEON: test3:
+; NEON-LABEL: test3:
 ; NEON: vcvt.f32.u32 d
 entry:
         %0 = add i32 %a, %b
@@ -41,9 +41,9 @@ entry:
 }
 
 define float @test4(i32 %a, i32 %b) {
-; VFP2: test4:
+; VFP2-LABEL: test4:
 ; VFP2: vcvt.f32.s32 s{{.}}, s{{.}}
-; NEON: test4:
+; NEON-LABEL: test4:
 ; NEON: vcvt.f32.s32 d
 entry:
         %0 = add i32 %a, %b
diff --git a/llvm/test/CodeGen/ARM/ldr_post.ll b/llvm/test/CodeGen/ARM/ldr_post.ll
index a6ca434..f5ff7dd 100644
--- a/llvm/test/CodeGen/ARM/ldr_post.ll
+++ b/llvm/test/CodeGen/ARM/ldr_post.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
 ; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: ldr {{.*, \[.*]}}, -r2
 ; CHECK-NOT: ldr
 define i32 @test1(i32 %a, i32 %b, i32 %c) {
@@ -13,7 +13,7 @@ define i32 @test1(i32 %a, i32 %b, i32 %c) {
         ret i32 %tmp5
 }
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: ldr {{.*, \[.*\]}}, #-16
 ; CHECK-NOT: ldr
 define i32 @test2(i32 %a, i32 %b) {
diff --git a/llvm/test/CodeGen/ARM/ldr_pre.ll b/llvm/test/CodeGen/ARM/ldr_pre.ll
index 6c40ad7..8281827 100644
--- a/llvm/test/CodeGen/ARM/ldr_pre.ll
+++ b/llvm/test/CodeGen/ARM/ldr_pre.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
 ; RUN: llc < %s -march=arm -mcpu=swift | FileCheck %s
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: ldr {{.*!}}
 ; CHECK-NOT: ldr
 define i32* @test1(i32* %X, i32* %dest) {
@@ -11,7 +11,7 @@ define i32* @test1(i32* %X, i32* %dest) {
         ret i32* %Y
 }
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: ldr {{.*!}}
 ; CHECK-NOT: ldr
 define i32 @test2(i32 %a, i32 %b, i32 %c) {
diff --git a/llvm/test/CodeGen/ARM/neon_vabs.ll b/llvm/test/CodeGen/ARM/neon_vabs.ll
index bf2770b..76b6044 100644
--- a/llvm/test/CodeGen/ARM/neon_vabs.ll
+++ b/llvm/test/CodeGen/ARM/neon_vabs.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <4 x i32> @test1(<4 x i32> %a) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: vabs.s32 q
         %tmp1neg = sub <4 x i32> zeroinitializer, %a
         %b = icmp sgt <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1>
@@ -10,7 +10,7 @@ define <4 x i32> @test1(<4 x i32> %a) nounwind {
 }
 
 define <4 x i32> @test2(<4 x i32> %a) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: vabs.s32 q
         %tmp1neg = sub <4 x i32> zeroinitializer, %a
         %b = icmp sge <4 x i32> %a, zeroinitializer
@@ -19,7 +19,7 @@ define <4 x i32> @test2(<4 x i32> %a) nounwind {
 }
 
 define <8 x i16> @test3(<8 x i16> %a) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: vabs.s16 q
         %tmp1neg = sub <8 x i16> zeroinitializer, %a
         %b = icmp sgt <8 x i16> %a, zeroinitializer
@@ -28,7 +28,7 @@ define <8 x i16> @test3(<8 x i16> %a) nounwind {
 }
 
 define <16 x i8> @test4(<16 x i8> %a) nounwind {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: vabs.s8 q
         %tmp1neg = sub <16 x i8> zeroinitializer, %a
         %b = icmp slt <16 x i8> %a, zeroinitializer
@@ -37,7 +37,7 @@ define <16 x i8> @test4(<16 x i8> %a) nounwind {
 }
 
 define <4 x i32> @test5(<4 x i32> %a) nounwind {
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: vabs.s32 q
         %tmp1neg = sub <4 x i32> zeroinitializer, %a
         %b = icmp sle <4 x i32> %a, zeroinitializer
@@ -46,7 +46,7 @@ define <4 x i32> @test5(<4 x i32> %a) nounwind {
 }
 
 define <2 x i32> @test6(<2 x i32> %a) nounwind {
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: vabs.s32 d
         %tmp1neg = sub <2 x i32> zeroinitializer, %a
         %b = icmp sgt <2 x i32> %a, <i32 -1, i32 -1>
@@ -55,7 +55,7 @@ define <2 x i32> @test6(<2 x i32> %a) nounwind {
 }
 
 define <2 x i32> @test7(<2 x i32> %a) nounwind {
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: vabs.s32 d
         %tmp1neg = sub <2 x i32> zeroinitializer, %a
         %b = icmp sge <2 x i32> %a, zeroinitializer
@@ -64,7 +64,7 @@ define <2 x i32> @test7(<2 x i32> %a) nounwind {
 }
 
 define <4 x i16> @test8(<4 x i16> %a) nounwind {
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: vabs.s16 d
         %tmp1neg = sub <4 x i16> zeroinitializer, %a
         %b = icmp sgt <4 x i16> %a, zeroinitializer
@@ -73,7 +73,7 @@ define <4 x i16> @test8(<4 x i16> %a) nounwind {
 }
 
 define <8 x i8> @test9(<8 x i8> %a) nounwind {
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: vabs.s8 d
         %tmp1neg = sub <8 x i8> zeroinitializer, %a
         %b = icmp slt <8 x i8> %a, zeroinitializer
@@ -82,7 +82,7 @@ define <8 x i8> @test9(<8 x i8> %a) nounwind {
 }
 
 define <2 x i32> @test10(<2 x i32> %a) nounwind {
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: vabs.s32 d
         %tmp1neg = sub <2 x i32> zeroinitializer, %a
         %b = icmp sle <2 x i32> %a, zeroinitializer
diff --git a/llvm/test/CodeGen/ARM/pack.ll b/llvm/test/CodeGen/ARM/pack.ll
index f6cc75e..fbc1155 100644
--- a/llvm/test/CodeGen/ARM/pack.ll
+++ b/llvm/test/CodeGen/ARM/pack.ll
@@ -90,7 +90,7 @@ define i32 @test8(i32 %X, i32 %Y) {
 	ret i32 %tmp57
 }
 
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: pkhtb r0, r0, r1, asr #16
 define i32 @test9(i32 %src1, i32 %src2) {
 entry:
@@ -100,7 +100,7 @@ entry:
     ret i32 %tmp3
 }
 
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: pkhtb r0, r0, r1, asr #17
 define i32 @test10(i32 %src1, i32 %src2) {
 entry:
diff --git a/llvm/test/CodeGen/ARM/rev.ll b/llvm/test/CodeGen/ARM/rev.ll
index 6bb6743..6c380ae 100644
--- a/llvm/test/CodeGen/ARM/rev.ll
+++ b/llvm/test/CodeGen/ARM/rev.ll
@@ -32,7 +32,7 @@ define i32 @test2(i32 %X) nounwind {
 ; rdar://9147637
 define i32 @test3(i16 zeroext %a) nounwind {
 entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: revsh r0, r0
   %0 = tail call i16 @llvm.bswap.i16(i16 %a)
   %1 = sext i16 %0 to i32
@@ -43,7 +43,7 @@ declare i16 @llvm.bswap.i16(i16) nounwind readnone
 
 define i32 @test4(i16 zeroext %a) nounwind {
 entry:
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: revsh r0, r0
   %conv = zext i16 %a to i32
   %shr9 = lshr i16 %a, 8
diff --git a/llvm/test/CodeGen/ARM/shifter_operand.ll b/llvm/test/CodeGen/ARM/shifter_operand.ll
index eb971ff..f14adca 100644
--- a/llvm/test/CodeGen/ARM/shifter_operand.ll
+++ b/llvm/test/CodeGen/ARM/shifter_operand.ll
@@ -4,10 +4,10 @@
 
 
 define i32 @test1(i32 %X, i32 %Y, i8 %sh) {
-; A8: test1:
+; A8-LABEL: test1:
 ; A8: add r0, r0, r1, lsl r2
 
-; A9: test1:
+; A9-LABEL: test1:
 ; A9: add r0, r0, r1, lsl r2
         %shift.upgrd.1 = zext i8 %sh to i32
         %A = shl i32 %Y, %shift.upgrd.1
@@ -16,10 +16,10 @@ define i32 @test1(i32 %X, i32 %Y, i8 %sh) {
 }
 
 define i32 @test2(i32 %X, i32 %Y, i8 %sh) {
-; A8: test2:
+; A8-LABEL: test2:
 ; A8: bic r0, r0, r1, asr r2
 
-; A9: test2:
+; A9-LABEL: test2:
 ; A9: bic r0, r0, r1, asr r2
         %shift.upgrd.2 = zext i8 %sh to i32
         %A = ashr i32 %Y, %shift.upgrd.2
@@ -30,12 +30,12 @@ define i32 @test2(i32 %X, i32 %Y, i8 %sh) {
 
 define i32 @test3(i32 %base, i32 %base2, i32 %offset) {
 entry:
-; A8: test3:
+; A8-LABEL: test3:
 ; A8: ldr r0, [r0, r2, lsl #2]
 ; A8: ldr r1, [r1, r2, lsl #2]
 
 ; lsl #2 is free
-; A9: test3:
+; A9-LABEL: test3:
 ; A9: ldr r0, [r0, r2, lsl #2]
 ; A9: ldr r1, [r1, r2, lsl #2]
         %tmp1 = shl i32 %offset, 2
@@ -53,13 +53,13 @@ declare i8* @malloc(...)
 
 define fastcc void @test4(i16 %addr) nounwind {
 entry:
-; A8: test4:
+; A8-LABEL: test4:
 ; A8: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
 ; A8-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
 ; A8: str [[REG]], [r0, r1, lsl #2]
 ; A8-NOT: str [[REG]], [r0]
 
-; A9: test4:
+; A9-LABEL: test4:
 ; A9: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]
 ; A9-NOT: ldr [[REG:r[0-9]+]], [r0, r1, lsl #2]!
 ; A9: str [[REG]], [r0, r1, lsl #2]
diff --git a/llvm/test/CodeGen/ARM/str_post.ll b/llvm/test/CodeGen/ARM/str_post.ll
index 97916f1..32e3b85 100644
--- a/llvm/test/CodeGen/ARM/str_post.ll
+++ b/llvm/test/CodeGen/ARM/str_post.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm | FileCheck %s
 
 define i16 @test1(i32* %X, i16* %A) {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: strh {{.*}}[{{.*}}], #-4
         %Y = load i32* %X               ; <i32> [#uses=1]
         %tmp1 = trunc i32 %Y to i16             ; <i16> [#uses=1]
@@ -12,7 +12,7 @@ define i16 @test1(i32* %X, i16* %A) {
 }
 
 define i32 @test2(i32* %X, i32* %A) {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: str {{.*}}[{{.*}}],
         %Y = load i32* %X               ; <i32> [#uses=1]
         store i32 %Y, i32* %A
diff --git a/llvm/test/CodeGen/ARM/swift-atomics.ll b/llvm/test/CodeGen/ARM/swift-atomics.ll
index 9711a9f..1d71815 100644
--- a/llvm/test/CodeGen/ARM/swift-atomics.ll
+++ b/llvm/test/CodeGen/ARM/swift-atomics.ll
@@ -4,7 +4,7 @@
 ; Release operations only need the store barrier provided by a "dmb ishst",
 
 define void @test_store_release(i32* %p, i32 %v) {
-; CHECK: test_store_release:
+; CHECK-LABEL: test_store_release:
 ; CHECK: dmb ishst
 ; CHECK: str
 
@@ -17,7 +17,7 @@ define void @test_store_release(i32* %p, i32 %v) {
 ; followed by an acquire does not get reordered. In that case a "dmb ishst" is
 ; not adequate.
 define i32 @test_seq_cst(i32* %p, i32 %v) {
-; CHECK: test_seq_cst:
+; CHECK-LABEL: test_seq_cst:
 ; CHECK: dmb ishst
 ; CHECK: str
 ; CHECK: dmb {{ish$}}
@@ -35,7 +35,7 @@ define i32 @test_seq_cst(i32* %p, i32 %v) {
 ; Also, pure acquire operations should definitely not have an ishst barrier.
 
 define i32 @test_acq(i32* %addr) {
-; CHECK: test_acq:
+; CHECK-LABEL: test_acq:
 ; CHECK: ldr
 ; CHECK: dmb {{ish$}}
 
diff --git a/llvm/test/CodeGen/ARM/thumb1-varalloc.ll b/llvm/test/CodeGen/ARM/thumb1-varalloc.ll
index aa88ae0..e07e8aa 100644
--- a/llvm/test/CodeGen/ARM/thumb1-varalloc.ll
+++ b/llvm/test/CodeGen/ARM/thumb1-varalloc.ll
@@ -39,4 +39,4 @@ bb3:
 }
 
 declare noalias i8* @strdup(i8* nocapture) nounwind
-declare i32 @_called_func(i8*, i32*) nounwind
\ No newline at end of file
+declare i32 @_called_func(i8*, i32*) nounwind
diff --git a/llvm/test/CodeGen/ARM/va_arg.ll b/llvm/test/CodeGen/ARM/va_arg.ll
index af477b4..f18b498 100644
--- a/llvm/test/CodeGen/ARM/va_arg.ll
+++ b/llvm/test/CodeGen/ARM/va_arg.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -pre-RA-sched=source | FileCheck %s
 ; Test that we correctly align elements when using va_arg
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NOT: bfc
 ; CHECK: add	[[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
 ; CHECK: bfc	[[REG]], #0, #3
@@ -17,7 +17,7 @@ entry:
   ret i64 %0
 }
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK-NOT: bfc
 ; CHECK: add	[[REG:(r[0-9]+)|(lr)]], {{(r[0-9]+)|(lr)}}, #7
 ; CHECK: bfc	[[REG]], #0, #3
diff --git a/llvm/test/CodeGen/ARM/vbsl.ll b/llvm/test/CodeGen/ARM/vbsl.ll
index 750fb0d..56e40eb 100644
--- a/llvm/test/CodeGen/ARM/vbsl.ll
+++ b/llvm/test/CodeGen/ARM/vbsl.ll
@@ -163,28 +163,28 @@ define <4 x float> @g4(<4 x float> %a, <4 x float> %b, <4 x float> %c) nounwind
 }
 
 define <1 x i64> @test_vbsl_s64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {
-; CHECK: test_vbsl_s64:
+; CHECK-LABEL: test_vbsl_s64:
 ; CHECK: vbsl d
   %vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind
   ret <1 x i64> %vbsl3.i
 }
 
 define <1 x i64> @test_vbsl_u64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind readnone optsize ssp {
-; CHECK: test_vbsl_u64:
+; CHECK-LABEL: test_vbsl_u64:
 ; CHECK: vbsl d
   %vbsl3.i = tail call <1 x i64> @llvm.arm.neon.vbsl.v1i64(<1 x i64> %a, <1 x i64> %b, <1 x i64> %c) nounwind
   ret <1 x i64> %vbsl3.i
 }
 
 define <2 x i64> @test_vbslq_s64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
-; CHECK: test_vbslq_s64:
+; CHECK-LABEL: test_vbslq_s64:
 ; CHECK: vbsl q
   %vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind
   ret <2 x i64> %vbsl3.i
 }
 
 define <2 x i64> @test_vbslq_u64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind readnone optsize ssp {
-; CHECK: test_vbslq_u64:
+; CHECK-LABEL: test_vbslq_u64:
 ; CHECK: vbsl q
   %vbsl3.i = tail call <2 x i64> @llvm.arm.neon.vbsl.v2i64(<2 x i64> %a, <2 x i64> %b, <2 x i64> %c) nounwind
   ret <2 x i64> %vbsl3.i
diff --git a/llvm/test/CodeGen/ARM/vext.ll b/llvm/test/CodeGen/ARM/vext.ll
index ef22a3b..5555a47 100644
--- a/llvm/test/CodeGen/ARM/vext.ll
+++ b/llvm/test/CodeGen/ARM/vext.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: test_vextd:
+;CHECK-LABEL: test_vextd:
 ;CHECK: vext
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -10,7 +10,7 @@ define <8 x i8> @test_vextd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: test_vextRd:
+;CHECK-LABEL: test_vextRd:
 ;CHECK: vext
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -19,7 +19,7 @@ define <8 x i8> @test_vextRd(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: test_vextq:
+;CHECK-LABEL: test_vextq:
 ;CHECK: vext
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -28,7 +28,7 @@ define <16 x i8> @test_vextq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: test_vextRq:
+;CHECK-LABEL: test_vextRq:
 ;CHECK: vext
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -37,7 +37,7 @@ define <16 x i8> @test_vextRq(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
-;CHECK: test_vextd16:
+;CHECK-LABEL: test_vextd16:
 ;CHECK: vext
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = load <4 x i16>* %B
@@ -46,7 +46,7 @@ define <4 x i16> @test_vextd16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
 }
 
 define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
-;CHECK: test_vextq32:
+;CHECK-LABEL: test_vextq32:
 ;CHECK: vext
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = load <4 x i32>* %B
@@ -57,7 +57,7 @@ define <4 x i32> @test_vextq32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
 ; Undef shuffle indices should not prevent matching to VEXT:
 
 define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
-;CHECK: test_vextd_undef:
+;CHECK-LABEL: test_vextd_undef:
 ;CHECK: vext
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = load <8 x i8>* %B
@@ -66,7 +66,7 @@ define <8 x i8> @test_vextd_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
 }
 
 define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
-;CHECK: test_vextRq_undef:
+;CHECK-LABEL: test_vextRq_undef:
 ;CHECK: vext
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = load <16 x i8>* %B
@@ -75,7 +75,7 @@ define <16 x i8> @test_vextRq_undef(<16 x i8>* %A, <16 x i8>* %B) nounwind {
 }
 
 define <16 x i8> @test_vextq_undef_op2(<16 x i8> %a) nounwind {
-;CHECK: test_vextq_undef_op2:
+;CHECK-LABEL: test_vextq_undef_op2:
 ;CHECK: vext
 entry:
   %tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>
@@ -83,7 +83,7 @@ entry:
 }
 
 define <8 x i8> @test_vextd_undef_op2(<8 x i8> %a) nounwind {
-;CHECK: test_vextd_undef_op2:
+;CHECK-LABEL: test_vextd_undef_op2:
 ;CHECK: vext
 entry:
   %tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0, i32 1>
@@ -92,7 +92,7 @@ entry:
 
 
 define <16 x i8> @test_vextq_undef_op2_undef(<16 x i8> %a) nounwind {
-;CHECK: test_vextq_undef_op2_undef:
+;CHECK-LABEL: test_vextq_undef_op2_undef:
 ;CHECK: vext
 entry:
   %tmp1 = shufflevector <16 x i8> %a, <16 x i8> undef, <16 x i32> <i32 2, i32 3, i32 4, i32 undef, i32 undef, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 0, i32 1>
@@ -100,7 +100,7 @@ entry:
 }
 
 define <8 x i8> @test_vextd_undef_op2_undef(<8 x i8> %a) nounwind {
-;CHECK: test_vextd_undef_op2_undef:
+;CHECK-LABEL: test_vextd_undef_op2_undef:
 ;CHECK: vext
 entry:
   %tmp1 = shufflevector <8 x i8> %a, <8 x i8> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 6, i32 7, i32 undef, i32 1>
@@ -114,7 +114,7 @@ entry:
 ; Also checks interleaving of sources is handled correctly.
 ; Essence: a vext is used on %A and something saner than stack load/store for final result.
 define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: test_interleaved:
+;CHECK-LABEL: test_interleaved:
 ;CHECK: vext.16
 ;CHECK-NOT: vext.16
 ;CHECK: vzip.16
@@ -126,7 +126,7 @@ define <4 x i16> @test_interleaved(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 
 ; An undef in the shuffle list should still be optimizable
 define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: test_undef:
+;CHECK-LABEL: test_undef:
 ;CHECK: vzip.16
         %tmp1 = load <8 x i16>* %A
         %tmp2 = load <8 x i16>* %B
@@ -138,7 +138,7 @@ define <4 x i16> @test_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ; Use illegal <32 x i16> type to produce such a shuffle after legalizing types.
 ; Try to look for fallback to by-element inserts.
 define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind {
-;CHECK: test_multisource:
+;CHECK-LABEL: test_multisource:
 ;CHECK: vmov.16 [[REG:d[0-9]+]][0]
 ;CHECK: vmov.16 [[REG]][1]
 ;CHECK: vmov.16 [[REG]][2]
@@ -151,7 +151,7 @@ define <4 x i16> @test_multisource(<32 x i16>* %B) nounwind {
 ; We don't handle shuffles using more than half of a 128-bit vector.
 ; Again, test for fallback to by-element inserts.
 define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
-;CHECK: test_largespan:
+;CHECK-LABEL: test_largespan:
 ;CHECK: vmov.16 [[REG:d[0-9]+]][0]
 ;CHECK: vmov.16 [[REG]][1]
 ;CHECK: vmov.16 [[REG]][2]
@@ -165,7 +165,7 @@ define <4 x i16> @test_largespan(<8 x i16>* %B) nounwind {
 ; this rather than blindly emitting a VECTOR_SHUFFLE (infinite
 ; lowering loop can result otherwise).
 define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
-;CHECK: test_illegal:
+;CHECK-LABEL: test_illegal:
 ;CHECK: vmov.16 [[REG:d[0-9]+]][0]
 ;CHECK: vmov.16 [[REG]][1]
 ;CHECK: vmov.16 [[REG]][2]
@@ -183,7 +183,7 @@ define <8 x i16> @test_illegal(<8 x i16>* %A, <8 x i16>* %B) nounwind {
 ; PR11129
 ; Make sure this doesn't crash
 define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind {
-; CHECK: test_elem_mismatch:
+; CHECK-LABEL: test_elem_mismatch:
 ; CHECK: vstr
   %tmp0 = load <2 x i64>* %src, align 16
   %tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32>
diff --git a/llvm/test/CodeGen/ARM/vfp.ll b/llvm/test/CodeGen/ARM/vfp.ll
index 7a4b34f..5d2943c 100644
--- a/llvm/test/CodeGen/ARM/vfp.ll
+++ b/llvm/test/CodeGen/ARM/vfp.ll
@@ -14,7 +14,7 @@ declare float @fabsf(float)
 declare double @fabs(double)
 
 define void @test_abs(float* %P, double* %D) {
-;CHECK: test_abs:
+;CHECK-LABEL: test_abs:
 	%a = load float* %P		; <float> [#uses=1]
 ;CHECK: vabs.f32
 	%b = call float @fabsf( float %a ) readnone	; <float> [#uses=1]
@@ -27,7 +27,7 @@ define void @test_abs(float* %P, double* %D) {
 }
 
 define void @test_add(float* %P, double* %D) {
-;CHECK: test_add:
+;CHECK-LABEL: test_add:
 	%a = load float* %P		; <float> [#uses=2]
 	%b = fadd float %a, %a		; <float> [#uses=1]
 	store float %b, float* %P
@@ -38,7 +38,7 @@ define void @test_add(float* %P, double* %D) {
 }
 
 define void @test_ext_round(float* %P, double* %D) {
-;CHECK: test_ext_round:
+;CHECK-LABEL: test_ext_round:
 	%a = load float* %P		; <float> [#uses=1]
 ;CHECK: vcvt.f64.f32
 ;CHECK: vcvt.f32.f64
@@ -51,7 +51,7 @@ define void @test_ext_round(float* %P, double* %D) {
 }
 
 define void @test_fma(float* %P1, float* %P2, float* %P3) {
-;CHECK: test_fma:
+;CHECK-LABEL: test_fma:
 	%a1 = load float* %P1		; <float> [#uses=1]
 	%a2 = load float* %P2		; <float> [#uses=1]
 	%a3 = load float* %P3		; <float> [#uses=1]
@@ -63,7 +63,7 @@ define void @test_fma(float* %P1, float* %P2, float* %P3) {
 }
 
 define i32 @test_ftoi(float* %P1) {
-;CHECK: test_ftoi:
+;CHECK-LABEL: test_ftoi:
 	%a1 = load float* %P1		; <float> [#uses=1]
 ;CHECK: vcvt.s32.f32
 	%b1 = fptosi float %a1 to i32		; <i32> [#uses=1]
@@ -71,7 +71,7 @@ define i32 @test_ftoi(float* %P1) {
 }
 
 define i32 @test_ftou(float* %P1) {
-;CHECK: test_ftou:
+;CHECK-LABEL: test_ftou:
 	%a1 = load float* %P1		; <float> [#uses=1]
 ;CHECK: vcvt.u32.f32
 	%b1 = fptoui float %a1 to i32		; <i32> [#uses=1]
@@ -79,7 +79,7 @@ define i32 @test_ftou(float* %P1) {
 }
 
 define i32 @test_dtoi(double* %P1) {
-;CHECK: test_dtoi:
+;CHECK-LABEL: test_dtoi:
 	%a1 = load double* %P1		; <double> [#uses=1]
 ;CHECK: vcvt.s32.f64
 	%b1 = fptosi double %a1 to i32		; <i32> [#uses=1]
@@ -87,7 +87,7 @@ define i32 @test_dtoi(double* %P1) {
 }
 
 define i32 @test_dtou(double* %P1) {
-;CHECK: test_dtou:
+;CHECK-LABEL: test_dtou:
 	%a1 = load double* %P1		; <double> [#uses=1]
 ;CHECK: vcvt.u32.f64
 	%b1 = fptoui double %a1 to i32		; <i32> [#uses=1]
@@ -95,7 +95,7 @@ define i32 @test_dtou(double* %P1) {
 }
 
 define void @test_utod(double* %P1, i32 %X) {
-;CHECK: test_utod:
+;CHECK-LABEL: test_utod:
 ;CHECK: vcvt.f64.u32
 	%b1 = uitofp i32 %X to double		; <double> [#uses=1]
 	store double %b1, double* %P1
@@ -103,7 +103,7 @@ define void @test_utod(double* %P1, i32 %X) {
 }
 
 define void @test_utod2(double* %P1, i8 %X) {
-;CHECK: test_utod2:
+;CHECK-LABEL: test_utod2:
 ;CHECK: vcvt.f64.u32
 	%b1 = uitofp i8 %X to double		; <double> [#uses=1]
 	store double %b1, double* %P1
@@ -111,7 +111,7 @@ define void @test_utod2(double* %P1, i8 %X) {
 }
 
 define void @test_cmp(float* %glob, i32 %X) {
-;CHECK: test_cmp:
+;CHECK-LABEL: test_cmp:
 entry:
 	%tmp = load float* %glob		; <float> [#uses=2]
 	%tmp3 = getelementptr float* %glob, i32 2		; <float*> [#uses=1]
@@ -139,7 +139,7 @@ declare i32 @bar(...)
 declare i32 @baz(...)
 
 define void @test_cmpfp0(float* %glob, i32 %X) {
-;CHECK: test_cmpfp0:
+;CHECK-LABEL: test_cmpfp0:
 entry:
 	%tmp = load float* %glob		; <float> [#uses=1]
 ;CHECK: vcmpe.f32
diff --git a/llvm/test/CodeGen/ARM/vget_lane.ll b/llvm/test/CodeGen/ARM/vget_lane.ll
index c9ce3b7..806ec95 100644
--- a/llvm/test/CodeGen/ARM/vget_lane.ll
+++ b/llvm/test/CodeGen/ARM/vget_lane.ll
@@ -207,7 +207,7 @@ define <4 x i32> @vsetQ_lane32(<4 x i32>* %A, i32 %B) nounwind {
 }
 
 define arm_aapcs_vfpcc <2 x float> @test_vset_lanef32(float %arg0_float32_t, <2 x float> %arg1_float32x2_t) nounwind {
-;CHECK: test_vset_lanef32:
+;CHECK-LABEL: test_vset_lanef32:
 ;CHECK: vmov.f32 s3, s0
 ;CHECK: vmov.f64 d0, d1
 entry:
diff --git a/llvm/test/CodeGen/ARM/vmul.ll b/llvm/test/CodeGen/ARM/vmul.ll
index eb5ad8f..aa3cda0 100644
--- a/llvm/test/CodeGen/ARM/vmul.ll
+++ b/llvm/test/CodeGen/ARM/vmul.ll
@@ -95,7 +95,7 @@ declare <16 x i8>  @llvm.arm.neon.vmulp.v16i8(<16 x i8>, <16 x i8>) nounwind rea
 
 define arm_aapcs_vfpcc <2 x float> @test_vmul_lanef32(<2 x float> %arg0_float32x2_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
 entry:
-; CHECK: test_vmul_lanef32:
+; CHECK-LABEL: test_vmul_lanef32:
 ; CHECK: vmul.f32 d0, d0, d1[0]
   %0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <2 x i32> zeroinitializer ; <<2 x float>> [#uses=1]
   %1 = fmul <2 x float> %0, %arg0_float32x2_t     ; <<2 x float>> [#uses=1]
@@ -104,7 +104,7 @@ entry:
 
 define arm_aapcs_vfpcc <4 x i16> @test_vmul_lanes16(<4 x i16> %arg0_int16x4_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
 entry:
-; CHECK: test_vmul_lanes16:
+; CHECK-LABEL: test_vmul_lanes16:
 ; CHECK: vmul.i16 d0, d0, d1[1]
   %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i16>> [#uses$
   %1 = mul <4 x i16> %0, %arg0_int16x4_t          ; <<4 x i16>> [#uses=1]
@@ -113,7 +113,7 @@ entry:
 
 define arm_aapcs_vfpcc <2 x i32> @test_vmul_lanes32(<2 x i32> %arg0_int32x2_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
 entry:
-; CHECK: test_vmul_lanes32:
+; CHECK-LABEL: test_vmul_lanes32:
 ; CHECK: vmul.i32 d0, d0, d1[1]
   %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <2 x i32> <i32 1, i32 1> ; <<2 x i32>> [#uses=1]
   %1 = mul <2 x i32> %0, %arg0_int32x2_t          ; <<2 x i32>> [#uses=1]
@@ -122,7 +122,7 @@ entry:
 
 define arm_aapcs_vfpcc <4 x float> @test_vmulQ_lanef32(<4 x float> %arg0_float32x4_t, <2 x float> %arg1_float32x2_t) nounwind readnone {
 entry:
-; CHECK: test_vmulQ_lanef32:
+; CHECK-LABEL: test_vmulQ_lanef32:
 ; CHECK: vmul.f32 q0, q0, d2[1]
   %0 = shufflevector <2 x float> %arg1_float32x2_t, <2 x float> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x float>$
   %1 = fmul <4 x float> %0, %arg0_float32x4_t     ; <<4 x float>> [#uses=1]
@@ -131,7 +131,7 @@ entry:
 
 define arm_aapcs_vfpcc <8 x i16> @test_vmulQ_lanes16(<8 x i16> %arg0_int16x8_t, <4 x i16> %arg1_int16x4_t) nounwind readnone {
 entry:
-; CHECK: test_vmulQ_lanes16:
+; CHECK-LABEL: test_vmulQ_lanes16:
 ; CHECK: vmul.i16 q0, q0, d2[1]
   %0 = shufflevector <4 x i16> %arg1_int16x4_t, <4 x i16> undef, <8 x i32> <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
   %1 = mul <8 x i16> %0, %arg0_int16x8_t          ; <<8 x i16>> [#uses=1]
@@ -140,7 +140,7 @@ entry:
 
 define arm_aapcs_vfpcc <4 x i32> @test_vmulQ_lanes32(<4 x i32> %arg0_int32x4_t, <2 x i32> %arg1_int32x2_t) nounwind readnone {
 entry:
-; CHECK: test_vmulQ_lanes32:
+; CHECK-LABEL: test_vmulQ_lanes32:
 ; CHECK: vmul.i32 q0, q0, d2[1]
   %0 = shufflevector <2 x i32> %arg1_int32x2_t, <2 x i32> undef, <4 x i32> <i32 1, i32 1, i32 1, i32 1> ; <<4 x i32>> [#uses$
   %1 = mul <4 x i32> %0, %arg0_int32x4_t          ; <<4 x i32>> [#uses=1]
diff --git a/llvm/test/CodeGen/ARM/vrev.ll b/llvm/test/CodeGen/ARM/vrev.ll
index 122ec03..b6da694 100644
--- a/llvm/test/CodeGen/ARM/vrev.ll
+++ b/llvm/test/CodeGen/ARM/vrev.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=arm -mattr=+neon | FileCheck %s
 
 define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
-;CHECK: test_vrev64D8:
+;CHECK-LABEL: test_vrev64D8:
 ;CHECK: vrev64.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
@@ -9,7 +9,7 @@ define <8 x i8> @test_vrev64D8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
-;CHECK: test_vrev64D16:
+;CHECK-LABEL: test_vrev64D16:
 ;CHECK: vrev64.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
@@ -17,7 +17,7 @@ define <4 x i16> @test_vrev64D16(<4 x i16>* %A) nounwind {
 }
 
 define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
-;CHECK: test_vrev64D32:
+;CHECK-LABEL: test_vrev64D32:
 ;CHECK: vrev64.32
 	%tmp1 = load <2 x i32>* %A
 	%tmp2 = shufflevector <2 x i32> %tmp1, <2 x i32> undef, <2 x i32> <i32 1, i32 0>
@@ -25,7 +25,7 @@ define <2 x i32> @test_vrev64D32(<2 x i32>* %A) nounwind {
 }
 
 define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
-;CHECK: test_vrev64Df:
+;CHECK-LABEL: test_vrev64Df:
 ;CHECK: vrev64.32
 	%tmp1 = load <2 x float>* %A
 	%tmp2 = shufflevector <2 x float> %tmp1, <2 x float> undef, <2 x i32> <i32 1, i32 0>
@@ -33,7 +33,7 @@ define <2 x float> @test_vrev64Df(<2 x float>* %A) nounwind {
 }
 
 define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
-;CHECK: test_vrev64Q8:
+;CHECK-LABEL: test_vrev64Q8:
 ;CHECK: vrev64.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0, i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8>
@@ -41,7 +41,7 @@ define <16 x i8> @test_vrev64Q8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
-;CHECK: test_vrev64Q16:
+;CHECK-LABEL: test_vrev64Q16:
 ;CHECK: vrev64.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
@@ -49,7 +49,7 @@ define <8 x i16> @test_vrev64Q16(<8 x i16>* %A) nounwind {
 }
 
 define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
-;CHECK: test_vrev64Q32:
+;CHECK-LABEL: test_vrev64Q32:
 ;CHECK: vrev64.32
 	%tmp1 = load <4 x i32>* %A
 	%tmp2 = shufflevector <4 x i32> %tmp1, <4 x i32> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
@@ -57,7 +57,7 @@ define <4 x i32> @test_vrev64Q32(<4 x i32>* %A) nounwind {
 }
 
 define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
-;CHECK: test_vrev64Qf:
+;CHECK-LABEL: test_vrev64Qf:
 ;CHECK: vrev64.32
 	%tmp1 = load <4 x float>* %A
 	%tmp2 = shufflevector <4 x float> %tmp1, <4 x float> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
@@ -65,7 +65,7 @@ define <4 x float> @test_vrev64Qf(<4 x float>* %A) nounwind {
 }
 
 define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
-;CHECK: test_vrev32D8:
+;CHECK-LABEL: test_vrev32D8:
 ;CHECK: vrev32.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4>
@@ -73,7 +73,7 @@ define <8 x i8> @test_vrev32D8(<8 x i8>* %A) nounwind {
 }
 
 define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
-;CHECK: test_vrev32D16:
+;CHECK-LABEL: test_vrev32D16:
 ;CHECK: vrev32.16
 	%tmp1 = load <4 x i16>* %A
 	%tmp2 = shufflevector <4 x i16> %tmp1, <4 x i16> undef, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
@@ -81,7 +81,7 @@ define <4 x i16> @test_vrev32D16(<4 x i16>* %A) nounwind {
 }
 
 define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
-;CHECK: test_vrev32Q8:
+;CHECK-LABEL: test_vrev32Q8:
 ;CHECK: vrev32.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 3, i32 2, i32 1, i32 0, i32 7, i32 6, i32 5, i32 4, i32 11, i32 10, i32 9, i32 8, i32 15, i32 14, i32 13, i32 12>
@@ -89,7 +89,7 @@ define <16 x i8> @test_vrev32Q8(<16 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
-;CHECK: test_vrev32Q16:
+;CHECK-LABEL: test_vrev32Q16:
 ;CHECK: vrev32.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
@@ -97,7 +97,7 @@ define <8 x i16> @test_vrev32Q16(<8 x i16>* %A) nounwind {
 }
 
 define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
-;CHECK: test_vrev16D8:
+;CHECK-LABEL: test_vrev16D8:
 ;CHECK: vrev16.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6>
@@ -105,7 +105,7 @@ define <8 x i8> @test_vrev16D8(<8 x i8>* %A) nounwind {
 }
 
 define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
-;CHECK: test_vrev16Q8:
+;CHECK-LABEL: test_vrev16Q8:
 ;CHECK: vrev16.8
 	%tmp1 = load <16 x i8>* %A
 	%tmp2 = shufflevector <16 x i8> %tmp1, <16 x i8> undef, <16 x i32> <i32 1, i32 0, i32 3, i32 2, i32 5, i32 4, i32 7, i32 6, i32 9, i32 8, i32 11, i32 10, i32 13, i32 12, i32 15, i32 14>
@@ -115,7 +115,7 @@ define <16 x i8> @test_vrev16Q8(<16 x i8>* %A) nounwind {
 ; Undef shuffle indices should not prevent matching to VREV:
 
 define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
-;CHECK: test_vrev64D8_undef:
+;CHECK-LABEL: test_vrev64D8_undef:
 ;CHECK: vrev64.8
 	%tmp1 = load <8 x i8>* %A
 	%tmp2 = shufflevector <8 x i8> %tmp1, <8 x i8> undef, <8 x i32> <i32 7, i32 undef, i32 undef, i32 4, i32 3, i32 2, i32 1, i32 0>
@@ -123,7 +123,7 @@ define <8 x i8> @test_vrev64D8_undef(<8 x i8>* %A) nounwind {
 }
 
 define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
-;CHECK: test_vrev32Q16_undef:
+;CHECK-LABEL: test_vrev32Q16_undef:
 ;CHECK: vrev32.16
 	%tmp1 = load <8 x i16>* %A
 	%tmp2 = shufflevector <8 x i16> %tmp1, <8 x i16> undef, <8 x i32> <i32 undef, i32 0, i32 undef, i32 2, i32 5, i32 4, i32 7, i32 undef>
@@ -133,7 +133,7 @@ define <8 x i16> @test_vrev32Q16_undef(<8 x i16>* %A) nounwind {
 ; A vcombine feeding a VREV should not obscure things.  Radar 8597007.
 
 define void @test_with_vcombine(<4 x float>* %v) nounwind {
-;CHECK: test_with_vcombine:
+;CHECK-LABEL: test_with_vcombine:
 ;CHECK-NOT: vext
 ;CHECK: vrev64.32
   %tmp1 = load <4 x float>* %v, align 16
@@ -151,7 +151,7 @@ define void @test_with_vcombine(<4 x float>* %v) nounwind {
 ; The type <2 x i16> is legalized to <2 x i32> and need to be trunc-stored
 ; to <2 x i16> when stored to memory.
 define void @test_vrev64(<4 x i16>* nocapture %source, <2 x i16>* nocapture %dst) nounwind ssp {
-; CHECK: test_vrev64:
+; CHECK-LABEL: test_vrev64:
 ; CHECK: vst1.32
 entry:
   %0 = bitcast <4 x i16>* %source to <8 x i16>*
diff --git a/llvm/test/CodeGen/Hexagon/adde.ll b/llvm/test/CodeGen/Hexagon/adde.ll
index 9cee3e2..6d060c1 100644
--- a/llvm/test/CodeGen/Hexagon/adde.ll
+++ b/llvm/test/CodeGen/Hexagon/adde.ll
@@ -31,4 +31,4 @@ entry:
         %tmp2122 = trunc i128 %tmp21 to i64
         store i64 %tmp2122, i64* %RH
         ret void
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/Hexagon/i16_VarArg.ll b/llvm/test/CodeGen/Hexagon/i16_VarArg.ll
index eb44c29..c5d05a5 100644
--- a/llvm/test/CodeGen/Hexagon/i16_VarArg.ll
+++ b/llvm/test/CodeGen/Hexagon/i16_VarArg.ll
@@ -37,4 +37,4 @@ define i32 @main() {
         %ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0
         call i32 (i8*, ...)* @printf( i8* %lt_s, i16 %val1 )
         ret i32 0
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/Hexagon/i1_VarArg.ll b/llvm/test/CodeGen/Hexagon/i1_VarArg.ll
index 7dbfb25..37f2778 100644
--- a/llvm/test/CodeGen/Hexagon/i1_VarArg.ll
+++ b/llvm/test/CodeGen/Hexagon/i1_VarArg.ll
@@ -41,4 +41,4 @@ define i32 @main() {
         call i32 (i8*, ...)* @printf( i8* %eq_s, i1 %eq_r )
         call i32 (i8*, ...)* @printf( i8* %ne_s, i1 %ne_r )
         ret i32 0
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/Hexagon/i8_VarArg.ll b/llvm/test/CodeGen/Hexagon/i8_VarArg.ll
index 687b178..6f056ff 100644
--- a/llvm/test/CodeGen/Hexagon/i8_VarArg.ll
+++ b/llvm/test/CodeGen/Hexagon/i8_VarArg.ll
@@ -37,4 +37,4 @@ define i32 @main() {
         %ne_s = getelementptr [13 x i8]* @ne_str, i64 0, i64 0
         call i32 (i8*, ...)* @printf( i8* %lt_s, i8 %val1 )
         ret i32 0
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/Hexagon/indirect-br.ll b/llvm/test/CodeGen/Hexagon/indirect-br.ll
index 919e501..188eebf 100644
--- a/llvm/test/CodeGen/Hexagon/indirect-br.ll
+++ b/llvm/test/CodeGen/Hexagon/indirect-br.ll
@@ -11,4 +11,4 @@ test_label:
 
 ret:
         ret i32 -1
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/Hexagon/sube.ll b/llvm/test/CodeGen/Hexagon/sube.ll
index 84172e9..735ac9e 100644
--- a/llvm/test/CodeGen/Hexagon/sube.ll
+++ b/llvm/test/CodeGen/Hexagon/sube.ll
@@ -26,4 +26,4 @@ entry:
         %tmp2122 = trunc i128 %tmp21 to i64
         store i64 %tmp2122, i64* %RH
         ret void
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/Hexagon/zextloadi1.ll b/llvm/test/CodeGen/Hexagon/zextloadi1.ll
index cb6e6fd..b58d933 100644
--- a/llvm/test/CodeGen/Hexagon/zextloadi1.ll
+++ b/llvm/test/CodeGen/Hexagon/zextloadi1.ll
@@ -22,4 +22,4 @@ define void @i65_ls() nounwind  {
         %tmp = load i65* @i65_l
         store i65 %tmp, i65* @i65_s
         ret void
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/MSP430/jumptable.ll b/llvm/test/CodeGen/MSP430/jumptable.ll
index cfd64e0..23619e7 100644
--- a/llvm/test/CodeGen/MSP430/jumptable.ll
+++ b/llvm/test/CodeGen/MSP430/jumptable.ll
@@ -6,7 +6,7 @@ target triple = "msp430---elf"
 ; Function Attrs: nounwind
 define i16 @test(i16 %i) #0 {
 entry:
-; CHECK: test:
+; CHECK-LABEL: test:
   %retval = alloca i16, align 2
   %i.addr = alloca i16, align 2
   store i16 %i, i16* %i.addr, align 2
diff --git a/llvm/test/CodeGen/Mips/align16.ll b/llvm/test/CodeGen/Mips/align16.ll
index 99139ab..815c84d 100644
--- a/llvm/test/CodeGen/Mips/align16.ll
+++ b/llvm/test/CodeGen/Mips/align16.ll
@@ -28,4 +28,4 @@ entry:
 ; 16:	save	$ra, $s0, $s1, 2040
 ; 16:	addiu	$sp, -48 # 16 bit inst
 ; 16:	addiu	$sp, 48 # 16 bit inst
-; 16:	restore	$ra,  $s0, $s1, 2040
\ No newline at end of file
+; 16:	restore	$ra,  $s0, $s1, 2040
diff --git a/llvm/test/CodeGen/Mips/blez_bgez.ll b/llvm/test/CodeGen/Mips/blez_bgez.ll
index 52765af..f6a5e4f 100644
--- a/llvm/test/CodeGen/Mips/blez_bgez.ll
+++ b/llvm/test/CodeGen/Mips/blez_bgez.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -march=mipsel < %s | FileCheck %s
 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
 
-; CHECK: test_blez:
+; CHECK-LABEL: test_blez:
 ; CHECK: blez ${{[0-9]+}}, $BB
 
 define void @test_blez(i32 %a) {
@@ -19,7 +19,7 @@ if.end:
 
 declare void @foo1()
 
-; CHECK: test_bgez:
+; CHECK-LABEL: test_bgez:
 ; CHECK: bgez ${{[0-9]+}}, $BB
 
 define void @test_bgez(i32 %a) {
diff --git a/llvm/test/CodeGen/Mips/dsp-patterns.ll b/llvm/test/CodeGen/Mips/dsp-patterns.ll
index eeb7140..ae0167b 100644
--- a/llvm/test/CodeGen/Mips/dsp-patterns.ll
+++ b/llvm/test/CodeGen/Mips/dsp-patterns.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -march=mips -mattr=dsp < %s | FileCheck %s -check-prefix=R1
 ; RUN: llc -march=mips -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2
 
-; R1: test_lbux:
+; R1-LABEL: test_lbux:
 ; R1: lbux ${{[0-9]+}}
 
 define zeroext i8 @test_lbux(i8* nocapture %b, i32 %i) {
@@ -11,7 +11,7 @@ entry:
   ret i8 %0
 }
 
-; R1: test_lhx:
+; R1-LABEL: test_lhx:
 ; R1: lhx ${{[0-9]+}}
 
 define signext i16 @test_lhx(i16* nocapture %b, i32 %i) {
@@ -21,7 +21,7 @@ entry:
   ret i16 %0
 }
 
-; R1: test_lwx:
+; R1-LABEL: test_lwx:
 ; R1: lwx ${{[0-9]+}}
 
 define i32 @test_lwx(i32* nocapture %b, i32 %i) {
@@ -31,7 +31,7 @@ entry:
   ret i32 %0
 }
 
-; R1: test_add_v2q15_:
+; R1-LABEL: test_add_v2q15_:
 ; R1: addq.ph ${{[0-9]+}}
 
 define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) {
@@ -44,7 +44,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: test_sub_v2q15_:
+; R1-LABEL: test_sub_v2q15_:
 ; R1: subq.ph ${{[0-9]+}}
 
 define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) {
@@ -57,11 +57,11 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R2: test_mul_v2q15_:
+; R2-LABEL: test_mul_v2q15_:
 ; R2: mul.ph ${{[0-9]+}}
 
 ; mul.ph is an R2 instruction. Check that multiply node gets expanded.
-; R1: test_mul_v2q15_:
+; R1-LABEL: test_mul_v2q15_:
 ; R1: mul ${{[0-9]+}}
 ; R1: mul ${{[0-9]+}}
 
@@ -75,7 +75,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: test_add_v4i8_:
+; R1-LABEL: test_add_v4i8_:
 ; R1: addu.qb ${{[0-9]+}}
 
 define { i32 } @test_add_v4i8_(i32 %a.coerce, i32 %b.coerce) {
@@ -88,7 +88,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: test_sub_v4i8_:
+; R1-LABEL: test_sub_v4i8_:
 ; R1: subu.qb ${{[0-9]+}}
 
 define { i32 } @test_sub_v4i8_(i32 %a.coerce, i32 %b.coerce) {
@@ -102,7 +102,7 @@ entry:
 }
 
 ; DSP-ASE doesn't have a v4i8 multiply instruction. Check that multiply node gets expanded.
-; R2: test_mul_v4i8_:
+; R2-LABEL: test_mul_v4i8_:
 ; R2: mul ${{[0-9]+}}
 ; R2: mul ${{[0-9]+}}
 ; R2: mul ${{[0-9]+}}
@@ -118,7 +118,7 @@ entry:
   ret { i32 } %.fca.0.insert
 }
 
-; R1: test_addsc:
+; R1-LABEL: test_addsc:
 ; R1: addsc ${{[0-9]+}}
 ; R1: addwc ${{[0-9]+}}
 
@@ -206,7 +206,7 @@ entry:
 
 ; Check that shift node is expanded if splat element size is not 16-bit.
 ;
-; R1: test_vector_splat_imm_v2q15:
+; R1-LABEL: test_vector_splat_imm_v2q15:
 ; R1-NOT: shll.ph
 
 define { i32 } @test_vector_splat_imm_v2q15(i32 %a.coerce) {
@@ -220,7 +220,7 @@ entry:
 
 ; Check that shift node is expanded if splat element size is not 8-bit.
 ;
-; R1: test_vector_splat_imm_v4i8:
+; R1-LABEL: test_vector_splat_imm_v4i8:
 ; R1-NOT: shll.qb
 
 define { i32 } @test_vector_splat_imm_v4i8(i32 %a.coerce) {
@@ -234,7 +234,7 @@ entry:
 
 ; Check that shift node is expanded if shift amount doesn't fit in 4-bit sa field.
 ;
-; R1: test_shift_amount_v2q15:
+; R1-LABEL: test_shift_amount_v2q15:
 ; R1-NOT: shll.ph
 
 define { i32 } @test_shift_amount_v2q15(i32 %a.coerce) {
@@ -248,7 +248,7 @@ entry:
 
 ; Check that shift node is expanded if shift amount doesn't fit in 3-bit sa field.
 ;
-; R1: test_shift_amount_v4i8:
+; R1-LABEL: test_shift_amount_v4i8:
 ; R1-NOT: shll.qb
 
 define { i32 } @test_shift_amount_v4i8(i32 %a.coerce) {
diff --git a/llvm/test/CodeGen/Mips/int-to-float-conversion.ll b/llvm/test/CodeGen/Mips/int-to-float-conversion.ll
index 2a7dfdd..c2baf44 100644
--- a/llvm/test/CodeGen/Mips/int-to-float-conversion.ll
+++ b/llvm/test/CodeGen/Mips/int-to-float-conversion.ll
@@ -4,7 +4,7 @@
 @i1 = global [3 x i32] [i32 1, i32 2, i32 3], align 4
 @i3 = common global i32* null, align 4
 
-; 32: test_float_int_:
+; 32-LABEL: test_float_int_:
 ; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
 ; 32: cvt.s.w $f{{[0-9]+}}, $f[[R0]]
 
@@ -14,10 +14,10 @@ entry:
   ret float %conv
 }
 
-; 32: test_double_int_:
+; 32-LABEL: test_double_int_:
 ; 32: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
 ; 32: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
-; 64: test_double_int_:
+; 64-LABEL: test_double_int_:
 ; 64: mtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
 ; 64: cvt.d.w $f{{[0-9]+}}, $f[[R0]]
 
@@ -27,7 +27,7 @@ entry:
   ret double %conv
 }
 
-; 64: test_float_LL_:
+; 64-LABEL: test_float_LL_:
 ; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
 ; 64: cvt.s.l $f{{[0-9]+}}, $f[[R0]]
 
@@ -37,7 +37,7 @@ entry:
   ret float %conv
 }
 
-; 64: test_double_LL_:
+; 64-LABEL: test_double_LL_:
 ; 64: dmtc1 ${{[0-9]+}}, $f[[R0:[0-9]+]]
 ; 64: cvt.d.l $f{{[0-9]+}}, $f[[R0]]
 
diff --git a/llvm/test/CodeGen/Mips/optimize-fp-math.ll b/llvm/test/CodeGen/Mips/optimize-fp-math.ll
index 9348d3c..8b71dc4 100644
--- a/llvm/test/CodeGen/Mips/optimize-fp-math.ll
+++ b/llvm/test/CodeGen/Mips/optimize-fp-math.ll
@@ -1,10 +1,10 @@
 ; RUN: llc -march=mipsel < %s | FileCheck %s -check-prefix=32
 ; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s -check-prefix=64
 
-; 32: test_sqrtf_float_:
+; 32-LABEL: test_sqrtf_float_:
 ; 32: sqrt.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 32: c.un.s $f[[R0]], $f[[R0]]
-; 64: test_sqrtf_float_:
+; 64-LABEL: test_sqrtf_float_:
 ; 64: sqrt.s $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 64: c.un.s $f[[R0]], $f[[R0]]
 
@@ -16,10 +16,10 @@ entry:
 
 declare float @sqrtf(float)
 
-; 32: test_sqrt_double_:
+; 32-LABEL: test_sqrt_double_:
 ; 32: sqrt.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 32: c.un.d $f[[R0]], $f[[R0]]
-; 64: test_sqrt_double_:
+; 64-LABEL: test_sqrt_double_:
 ; 64: sqrt.d $f[[R0:[0-9]+]], $f{{[0-9]+}}
 ; 64: c.un.d $f[[R0]], $f[[R0]]
 
diff --git a/llvm/test/CodeGen/Mips/selnek.ll b/llvm/test/CodeGen/Mips/selnek.ll
index 2601552..64834b2 100644
--- a/llvm/test/CodeGen/Mips/selnek.ll
+++ b/llvm/test/CodeGen/Mips/selnek.ll
@@ -104,4 +104,4 @@ attributes #1 = { "target-cpu"="mips16" "target-features"="+mips16,+o32" }
 ; 16:	bteqz	$BB{{[0-9]+}}_{{[0-9]}}
 
 ; 16:	cmpi	${{[0-9]+}}, 1000
-; 16:	bteqz	$BB{{[0-9]+}}_{{[0-9]}}
\ No newline at end of file
+; 16:	bteqz	$BB{{[0-9]+}}_{{[0-9]}}
diff --git a/llvm/test/CodeGen/NVPTX/ctpop.ll b/llvm/test/CodeGen/NVPTX/ctpop.ll
index 89477ac..b961d4d 100644
--- a/llvm/test/CodeGen/NVPTX/ctpop.ll
+++ b/llvm/test/CodeGen/NVPTX/ctpop.ll
@@ -22,4 +22,4 @@ define i64 @myctpop64(i64 %a) {
 
 declare i16 @llvm.ctpop.i16(i16)
 declare i32 @llvm.ctpop.i32(i32)
-declare i64 @llvm.ctpop.i64(i64)
\ No newline at end of file
+declare i64 @llvm.ctpop.i64(i64)
diff --git a/llvm/test/CodeGen/NVPTX/i8-param.ll b/llvm/test/CodeGen/NVPTX/i8-param.ll
index 9a253ff..84daa9f 100644
--- a/llvm/test/CodeGen/NVPTX/i8-param.ll
+++ b/llvm/test/CodeGen/NVPTX/i8-param.ll
@@ -20,4 +20,4 @@ define void @caller(i8* %a) {
   ret void
 }
 
-  
\ No newline at end of file
+  
diff --git a/llvm/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll b/llvm/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll
index 242e5b8..26cadc4 100644
--- a/llvm/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll
+++ b/llvm/test/CodeGen/NVPTX/ldu-reg-plus-offset.ll
@@ -18,4 +18,4 @@ define void @reg_plus_offset(i32* %a) {
 !1 = metadata !{ i32 4 }
 
 declare i32 @llvm.nvvm.ldu.global.i.i32(i32*)
-declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
\ No newline at end of file
+declare i32 @llvm.nvvm.read.ptx.sreg.tid.x()
diff --git a/llvm/test/CodeGen/NVPTX/rsqrt.ll b/llvm/test/CodeGen/NVPTX/rsqrt.ll
index d49eebe..3a52a49 100644
--- a/llvm/test/CodeGen/NVPTX/rsqrt.ll
+++ b/llvm/test/CodeGen/NVPTX/rsqrt.ll
@@ -10,4 +10,4 @@ define float @foo(float %a) {
   %ret = fdiv float 1.0, %val
   ret float %ret
 }
-  
\ No newline at end of file
+  
diff --git a/llvm/test/CodeGen/NVPTX/sext-in-reg.ll b/llvm/test/CodeGen/NVPTX/sext-in-reg.ll
index 4761fb5..b516dfa 100644
--- a/llvm/test/CodeGen/NVPTX/sext-in-reg.ll
+++ b/llvm/test/CodeGen/NVPTX/sext-in-reg.ll
@@ -108,4 +108,4 @@ entry:
   %add17 = add nsw i16 %shr9, %shr
   store i16 %add17, i16* %p2, align 4
   ret void
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll b/llvm/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll
index a18829e..b1cbb36 100644
--- a/llvm/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll
+++ b/llvm/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll
@@ -9,7 +9,7 @@ entry:
   store i64 %z2, i64* %xx, align 4
   ret void
 
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: sldi {{.*}}, {{.*}}, 32
 ; Note: it's okay if someday CodeGen gets smart enough to optimize out
 ; the shift.
diff --git a/llvm/test/CodeGen/PowerPC/fma.ll b/llvm/test/CodeGen/PowerPC/fma.ll
index a173c91..db19761 100644
--- a/llvm/test/CodeGen/PowerPC/fma.ll
+++ b/llvm/test/CodeGen/PowerPC/fma.ll
@@ -4,7 +4,7 @@ define double @test_FMADD1(double %A, double %B, double %C) {
 	%D = fmul double %A, %B		; <double> [#uses=1]
 	%E = fadd double %D, %C		; <double> [#uses=1]
 	ret double %E
-; CHECK: test_FMADD1:
+; CHECK-LABEL: test_FMADD1:
 ; CHECK: fmadd
 ; CHECK-NEXT: blr
 }
@@ -13,7 +13,7 @@ define double @test_FMADD2(double %A, double %B, double %C) {
 	%D = fmul double %A, %B		; <double> [#uses=1]
 	%E = fadd double %D, %C		; <double> [#uses=1]
 	ret double %E
-; CHECK: test_FMADD2:
+; CHECK-LABEL: test_FMADD2:
 ; CHECK: fmadd
 ; CHECK-NEXT: blr
 }
@@ -22,7 +22,7 @@ define double @test_FMSUB(double %A, double %B, double %C) {
 	%D = fmul double %A, %B		; <double> [#uses=1]
 	%E = fsub double %D, %C		; <double> [#uses=1]
 	ret double %E
-; CHECK: test_FMSUB:
+; CHECK-LABEL: test_FMSUB:
 ; CHECK: fmsub
 ; CHECK-NEXT: blr
 }
@@ -32,7 +32,7 @@ define double @test_FNMADD1(double %A, double %B, double %C) {
 	%E = fadd double %D, %C		; <double> [#uses=1]
 	%F = fsub double -0.000000e+00, %E		; <double> [#uses=1]
 	ret double %F
-; CHECK: test_FNMADD1:
+; CHECK-LABEL: test_FNMADD1:
 ; CHECK: fnmadd
 ; CHECK-NEXT: blr
 }
@@ -42,7 +42,7 @@ define double @test_FNMADD2(double %A, double %B, double %C) {
 	%E = fadd double %C, %D		; <double> [#uses=1]
 	%F = fsub double -0.000000e+00, %E		; <double> [#uses=1]
 	ret double %F
-; CHECK: test_FNMADD2:
+; CHECK-LABEL: test_FNMADD2:
 ; CHECK: fnmadd
 ; CHECK-NEXT: blr
 }
@@ -51,7 +51,7 @@ define double @test_FNMSUB1(double %A, double %B, double %C) {
 	%D = fmul double %A, %B		; <double> [#uses=1]
 	%E = fsub double %C, %D		; <double> [#uses=1]
 	ret double %E
-; CHECK: test_FNMSUB1:
+; CHECK-LABEL: test_FNMSUB1:
 ; CHECK: fnmsub
 ; CHECK-NEXT: blr
 }
@@ -61,7 +61,7 @@ define double @test_FNMSUB2(double %A, double %B, double %C) {
 	%E = fsub double %D, %C		; <double> [#uses=1]
 	%F = fsub double -0.000000e+00, %E		; <double> [#uses=1]
 	ret double %F
-; CHECK: test_FNMSUB2:
+; CHECK-LABEL: test_FNMSUB2:
 ; CHECK: fnmsub
 ; CHECK-NEXT: blr
 }
@@ -71,7 +71,7 @@ define float @test_FNMSUBS(float %A, float %B, float %C) {
 	%E = fsub float %D, %C		; <float> [#uses=1]
 	%F = fsub float -0.000000e+00, %E		; <float> [#uses=1]
 	ret float %F
-; CHECK: test_FNMSUBS:
+; CHECK-LABEL: test_FNMSUBS:
 ; CHECK: fnmsubs
 ; CHECK-NEXT: blr
 }
diff --git a/llvm/test/CodeGen/PowerPC/mcm-1.ll b/llvm/test/CodeGen/PowerPC/mcm-1.ll
index a57fb9d..4e31550 100644
--- a/llvm/test/CodeGen/PowerPC/mcm-1.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-1.ll
@@ -17,7 +17,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_external:
+; CHECK-LABEL: test_external:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/llvm/test/CodeGen/PowerPC/mcm-10.ll b/llvm/test/CodeGen/PowerPC/mcm-10.ll
index 4bec3e1..b479559 100644
--- a/llvm/test/CodeGen/PowerPC/mcm-10.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-10.ll
@@ -16,7 +16,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_fn_static:
+; CHECK-LABEL: test_fn_static:
 ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; CHECK: lwz {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
 ; CHECK: stw {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
diff --git a/llvm/test/CodeGen/PowerPC/mcm-11.ll b/llvm/test/CodeGen/PowerPC/mcm-11.ll
index f2bc4c9..c49e865 100644
--- a/llvm/test/CodeGen/PowerPC/mcm-11.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-11.ll
@@ -16,7 +16,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_file_static:
+; CHECK-LABEL: test_file_static:
 ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; CHECK: lwz {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
 ; CHECK: stw {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
diff --git a/llvm/test/CodeGen/PowerPC/mcm-12.ll b/llvm/test/CodeGen/PowerPC/mcm-12.ll
index 911305d..b31b605 100644
--- a/llvm/test/CodeGen/PowerPC/mcm-12.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-12.ll
@@ -13,6 +13,6 @@ entry:
 
 ; CHECK: [[VAR:[a-z0-9A-Z_.]+]]:
 ; CHECK: .quad 4562098671269285104
-; CHECK: test_double_const:
+; CHECK-LABEL: test_double_const:
 ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
diff --git a/llvm/test/CodeGen/PowerPC/mcm-2.ll b/llvm/test/CodeGen/PowerPC/mcm-2.ll
index f0dff4c..d4f40f7 100644
--- a/llvm/test/CodeGen/PowerPC/mcm-2.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-2.ll
@@ -17,7 +17,7 @@ entry:
   ret i32 %0
 }
 
-; MEDIUM: test_fn_static:
+; MEDIUM-LABEL: test_fn_static:
 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
 ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
@@ -26,7 +26,7 @@ entry:
 ; MEDIUM: .local [[VAR]]
 ; MEDIUM: .comm [[VAR]],4,4
 
-; LARGE: test_fn_static:
+; LARGE-LABEL: test_fn_static:
 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
 ; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/llvm/test/CodeGen/PowerPC/mcm-3.ll b/llvm/test/CodeGen/PowerPC/mcm-3.ll
index b790550..ce151fb 100644
--- a/llvm/test/CodeGen/PowerPC/mcm-3.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-3.ll
@@ -17,7 +17,7 @@ entry:
   ret i32 %0
 }
 
-; MEDIUM: test_file_static:
+; MEDIUM-LABEL: test_file_static:
 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
 ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
@@ -28,7 +28,7 @@ entry:
 ; MEDIUM: [[VAR]]:
 ; MEDIUM: .long 5
 
-; LARGE: test_file_static:
+; LARGE-LABEL: test_file_static:
 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
 ; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/llvm/test/CodeGen/PowerPC/mcm-4.ll b/llvm/test/CodeGen/PowerPC/mcm-4.ll
index 8150f91..7d7b132 100644
--- a/llvm/test/CodeGen/PowerPC/mcm-4.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-4.ll
@@ -14,14 +14,14 @@ entry:
 
 ; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]:
 ; MEDIUM: .quad 4562098671269285104
-; MEDIUM: test_double_const:
+; MEDIUM-LABEL: test_double_const:
 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
 ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])
 
 ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
 ; LARGE: .quad 4562098671269285104
-; LARGE: test_double_const:
+; LARGE-LABEL: test_double_const:
 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
 ; LARGE: lfd {{[0-9]+}}, 0([[REG2]])
diff --git a/llvm/test/CodeGen/PowerPC/mcm-5.ll b/llvm/test/CodeGen/PowerPC/mcm-5.ll
index 1be27b7..92ddeca 100644
--- a/llvm/test/CodeGen/PowerPC/mcm-5.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-5.ll
@@ -51,7 +51,7 @@ sw.epilog:                                        ; preds = %sw.bb3, %sw.default
   ret i32 %5
 }
 
-; CHECK: test_jump_table:
+; CHECK-LABEL: test_jump_table:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: ldx {{[0-9]+}}, {{[0-9]+}}, [[REG2]]
diff --git a/llvm/test/CodeGen/PowerPC/mcm-6.ll b/llvm/test/CodeGen/PowerPC/mcm-6.ll
index 35efaaa..f7838b4 100644
--- a/llvm/test/CodeGen/PowerPC/mcm-6.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-6.ll
@@ -17,7 +17,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_tentative:
+; CHECK-LABEL: test_tentative:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/llvm/test/CodeGen/PowerPC/mcm-7.ll b/llvm/test/CodeGen/PowerPC/mcm-7.ll
index 0dd39ee..7caa13b 100644
--- a/llvm/test/CodeGen/PowerPC/mcm-7.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-7.ll
@@ -18,7 +18,7 @@ entry:
 
 declare signext i32 @foo(i32 signext)
 
-; CHECK: test_fnaddr:
+; CHECK-LABEL: test_fnaddr:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: .section .toc
diff --git a/llvm/test/CodeGen/PowerPC/mcm-8.ll b/llvm/test/CodeGen/PowerPC/mcm-8.ll
index 3ece786..643548f 100644
--- a/llvm/test/CodeGen/PowerPC/mcm-8.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-8.ll
@@ -16,7 +16,7 @@ entry:
   ret i8 %1
 }
 
-; CHECK: test_avext:
+; CHECK-LABEL: test_avext:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lbz {{[0-9]+}}, 0([[REG2]])
diff --git a/llvm/test/CodeGen/PowerPC/mcm-9.ll b/llvm/test/CodeGen/PowerPC/mcm-9.ll
index f366f45..e587f61 100644
--- a/llvm/test/CodeGen/PowerPC/mcm-9.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-9.ll
@@ -18,7 +18,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_external:
+; CHECK-LABEL: test_external:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/llvm/test/CodeGen/PowerPC/mcm-default.ll b/llvm/test/CodeGen/PowerPC/mcm-default.ll
index 19de253..8d4ff14 100644
--- a/llvm/test/CodeGen/PowerPC/mcm-default.ll
+++ b/llvm/test/CodeGen/PowerPC/mcm-default.ll
@@ -16,7 +16,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_external:
+; CHECK-LABEL: test_external:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/llvm/test/CodeGen/PowerPC/misched-inorder-latency.ll b/llvm/test/CodeGen/PowerPC/misched-inorder-latency.ll
index 8fae7ad..b259ff1 100644
--- a/llvm/test/CodeGen/PowerPC/misched-inorder-latency.ll
+++ b/llvm/test/CodeGen/PowerPC/misched-inorder-latency.ll
@@ -6,7 +6,7 @@ target triple = "powerpc64-bgq-linux"
 
 ; %val1 is a load live out of %entry. It should be hoisted
 ; above the add.
-; CHECK: testload:
+; CHECK-LABEL: testload:
 ; CHECK: %entry
 ; CHECK: lwz
 ; CHECK: addi
@@ -34,7 +34,7 @@ end:
 ; The prefetch gets a default latency of 3 cycles and should be hoisted
 ; above the add.
 ;
-; CHECK: testprefetch:
+; CHECK-LABEL: testprefetch:
 ; CHECK: %entry
 ; CHECK: dcbt
 ; CHECK: addi
diff --git a/llvm/test/CodeGen/PowerPC/ppc64-calls.ll b/llvm/test/CodeGen/PowerPC/ppc64-calls.ll
index c382edb..1f3bb71 100644
--- a/llvm/test/CodeGen/PowerPC/ppc64-calls.ll
+++ b/llvm/test/CodeGen/PowerPC/ppc64-calls.ll
@@ -12,7 +12,7 @@ define weak void @foo_weak() nounwind {
 
 ; Calls to local function does not require the TOC restore 'nop'
 define void @test_direct() nounwind readnone {
-; CHECK: test_direct:
+; CHECK-LABEL: test_direct:
   tail call void @foo() nounwind
 ; CHECK: bl foo
 ; CHECK-NOT: nop
@@ -22,7 +22,7 @@ define void @test_direct() nounwind readnone {
 ; Calls to weak function requires a TOC restore 'nop' because they
 ; may be overridden in a different module.
 define void @test_weak() nounwind readnone {
-; CHECK: test_weak:
+; CHECK-LABEL: test_weak:
   tail call void @foo_weak() nounwind
 ; CHECK: bl foo
 ; CHECK-NEXT: nop
@@ -31,7 +31,7 @@ define void @test_weak() nounwind readnone {
 
 ; Indirect calls requires a full stub creation
 define void @test_indirect(void ()* nocapture %fp) nounwind {
-; CHECK: test_indirect:
+; CHECK-LABEL: test_indirect:
   tail call void %fp() nounwind
 ; CHECK: ld [[FP:[0-9]+]], 0(3)
 ; CHECK: ld 11, 16(3)
@@ -44,7 +44,7 @@ define void @test_indirect(void ()* nocapture %fp) nounwind {
 
 ; Absolute vales should be have the TOC restore 'nop'
 define void @test_abs() nounwind {
-; CHECK: test_abs:
+; CHECK-LABEL: test_abs:
   tail call void inttoptr (i64 1024 to void ()*)() nounwind
 ; CHECK: bla 1024
 ; CHECK-NEXT: nop
@@ -55,7 +55,7 @@ declare double @sin(double) nounwind
 
 ; External functions call should also have a 'nop'
 define double @test_external(double %x) nounwind {
-; CHECK: test_external:
+; CHECK-LABEL: test_external:
   %call = tail call double @sin(double %x) nounwind
 ; CHECK: bl sin
 ; CHECK-NEXT: nop
diff --git a/llvm/test/CodeGen/PowerPC/rounding-ops.ll b/llvm/test/CodeGen/PowerPC/rounding-ops.ll
index 2b5e1c9..fa57ee2 100644
--- a/llvm/test/CodeGen/PowerPC/rounding-ops.ll
+++ b/llvm/test/CodeGen/PowerPC/rounding-ops.ll
@@ -7,7 +7,7 @@ define float @test1(float %x) nounwind  {
   %call = tail call float @floorf(float %x) nounwind readnone
   ret float %call
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: frim 1, 1
 
 ; CHECK-FM: test1:
@@ -20,7 +20,7 @@ define double @test2(double %x) nounwind  {
   %call = tail call double @floor(double %x) nounwind readnone
   ret double %call
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: frim 1, 1
 
 ; CHECK-FM: test2:
@@ -33,7 +33,7 @@ define float @test3(float %x) nounwind  {
   %call = tail call float @nearbyintf(float %x) nounwind readnone
   ret float %call
 
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK-NOT: frin
 
 ; CHECK-FM: test3:
@@ -46,7 +46,7 @@ define double @test4(double %x) nounwind  {
   %call = tail call double @nearbyint(double %x) nounwind readnone
   ret double %call
 
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK-NOT: frin
 
 ; CHECK-FM: test4:
@@ -59,7 +59,7 @@ define float @test5(float %x) nounwind  {
   %call = tail call float @ceilf(float %x) nounwind readnone
   ret float %call
 
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: frip 1, 1
 
 ; CHECK-FM: test5:
@@ -72,7 +72,7 @@ define double @test6(double %x) nounwind  {
   %call = tail call double @ceil(double %x) nounwind readnone
   ret double %call
 
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: frip 1, 1
 
 ; CHECK-FM: test6:
@@ -85,7 +85,7 @@ define float @test9(float %x) nounwind  {
   %call = tail call float @truncf(float %x) nounwind readnone
   ret float %call
 
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: friz 1, 1
 
 ; CHECK-FM: test9:
@@ -98,7 +98,7 @@ define double @test10(double %x) nounwind  {
   %call = tail call double @trunc(double %x) nounwind readnone
   ret double %call
 
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: friz 1, 1
 
 ; CHECK-FM: test10:
@@ -112,7 +112,7 @@ define void @test11(float %x, float* %y) nounwind  {
   store float %call, float* %y
   ret void
 
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK-NOT: frin
 
 ; CHECK-FM: test11:
@@ -131,7 +131,7 @@ define void @test12(double %x, double* %y) nounwind  {
   store double %call, double* %y
   ret void
 
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK-NOT: frin
 
 ; CHECK-FM: test12:
diff --git a/llvm/test/CodeGen/PowerPC/vaddsplat.ll b/llvm/test/CodeGen/PowerPC/vaddsplat.ll
index e65148a..4236fab 100644
--- a/llvm/test/CodeGen/PowerPC/vaddsplat.ll
+++ b/llvm/test/CodeGen/PowerPC/vaddsplat.ll
@@ -16,7 +16,7 @@ define void @test_v4i32_pos_even(%v4i32* %P, %v4i32* %S) {
        ret void
 }
 
-; CHECK: test_v4i32_pos_even:
+; CHECK-LABEL: test_v4i32_pos_even:
 ; CHECK: vspltisw [[REG1:[0-9]+]], 9
 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -27,7 +27,7 @@ define void @test_v4i32_neg_even(%v4i32* %P, %v4i32* %S) {
        ret void
 }
 
-; CHECK: test_v4i32_neg_even:
+; CHECK-LABEL: test_v4i32_neg_even:
 ; CHECK: vspltisw [[REG1:[0-9]+]], -14
 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -38,7 +38,7 @@ define void @test_v8i16_pos_even(%v8i16* %P, %v8i16* %S) {
        ret void
 }
 
-; CHECK: test_v8i16_pos_even:
+; CHECK-LABEL: test_v8i16_pos_even:
 ; CHECK: vspltish [[REG1:[0-9]+]], 15
 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -49,7 +49,7 @@ define void @test_v8i16_neg_even(%v8i16* %P, %v8i16* %S) {
        ret void
 }
 
-; CHECK: test_v8i16_neg_even:
+; CHECK-LABEL: test_v8i16_neg_even:
 ; CHECK: vspltish [[REG1:[0-9]+]], -16
 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -60,7 +60,7 @@ define void @test_v16i8_pos_even(%v16i8* %P, %v16i8* %S) {
        ret void
 }
 
-; CHECK: test_v16i8_pos_even:
+; CHECK-LABEL: test_v16i8_pos_even:
 ; CHECK: vspltisb [[REG1:[0-9]+]], 8
 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -71,7 +71,7 @@ define void @test_v16i8_neg_even(%v16i8* %P, %v16i8* %S) {
        ret void
 }
 
-; CHECK: test_v16i8_neg_even:
+; CHECK-LABEL: test_v16i8_neg_even:
 ; CHECK: vspltisb [[REG1:[0-9]+]], -9
 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -82,7 +82,7 @@ define void @test_v4i32_pos_odd(%v4i32* %P, %v4i32* %S) {
        ret void
 }
 
-; CHECK: test_v4i32_pos_odd:
+; CHECK-LABEL: test_v4i32_pos_odd:
 ; CHECK: vspltisw [[REG2:[0-9]+]], -16
 ; CHECK: vspltisw [[REG1:[0-9]+]], 11
 ; CHECK: vsubuwm {{[0-9]+}}, [[REG1]], [[REG2]]
@@ -94,7 +94,7 @@ define void @test_v4i32_neg_odd(%v4i32* %P, %v4i32* %S) {
        ret void
 }
 
-; CHECK: test_v4i32_neg_odd:
+; CHECK-LABEL: test_v4i32_neg_odd:
 ; CHECK: vspltisw [[REG2:[0-9]+]], -16
 ; CHECK: vspltisw [[REG1:[0-9]+]], -11
 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG2]]
@@ -106,7 +106,7 @@ define void @test_v8i16_pos_odd(%v8i16* %P, %v8i16* %S) {
        ret void
 }
 
-; CHECK: test_v8i16_pos_odd:
+; CHECK-LABEL: test_v8i16_pos_odd:
 ; CHECK: vspltish [[REG2:[0-9]+]], -16
 ; CHECK: vspltish [[REG1:[0-9]+]], 15
 ; CHECK: vsubuhm {{[0-9]+}}, [[REG1]], [[REG2]]
@@ -118,7 +118,7 @@ define void @test_v8i16_neg_odd(%v8i16* %P, %v8i16* %S) {
        ret void
 }
 
-; CHECK: test_v8i16_neg_odd:
+; CHECK-LABEL: test_v8i16_neg_odd:
 ; CHECK: vspltish [[REG2:[0-9]+]], -16
 ; CHECK: vspltish [[REG1:[0-9]+]], -15
 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG2]]
@@ -130,7 +130,7 @@ define void @test_v16i8_pos_odd(%v16i8* %P, %v16i8* %S) {
        ret void
 }
 
-; CHECK: test_v16i8_pos_odd:
+; CHECK-LABEL: test_v16i8_pos_odd:
 ; CHECK: vspltisb [[REG2:[0-9]+]], -16
 ; CHECK: vspltisb [[REG1:[0-9]+]], 1
 ; CHECK: vsububm {{[0-9]+}}, [[REG1]], [[REG2]]
@@ -142,7 +142,7 @@ define void @test_v16i8_neg_odd(%v16i8* %P, %v16i8* %S) {
        ret void
 }
 
-; CHECK: test_v16i8_neg_odd:
+; CHECK-LABEL: test_v16i8_neg_odd:
 ; CHECK: vspltisb [[REG2:[0-9]+]], -16
 ; CHECK: vspltisb [[REG1:[0-9]+]], -1
 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG2]]
diff --git a/llvm/test/CodeGen/PowerPC/varargs.ll b/llvm/test/CodeGen/PowerPC/varargs.ll
index 90f0480..dfd2056 100644
--- a/llvm/test/CodeGen/PowerPC/varargs.ll
+++ b/llvm/test/CodeGen/PowerPC/varargs.ll
@@ -7,14 +7,14 @@ define i8* @test1(i8** %foo) nounwind {
   ret i8* %A
 }
 
-; P32: test1:
+; P32-LABEL: test1:
 ; P32: lwz r2, 0(r3)
 ; P32: addi r4, r2, 4
 ; P32: stw r4, 0(r3)
 ; P32: lwz r3, 0(r2)
 ; P32: blr 
 
-; P64: test1:
+; P64-LABEL: test1:
 ; P64: ld r2, 0(r3)
 ; P64: addi r4, r2, 8
 ; P64: std r4, 0(r3)
diff --git a/llvm/test/CodeGen/PowerPC/vec_constants.ll b/llvm/test/CodeGen/PowerPC/vec_constants.ll
index e4799e5..f16b9f5 100644
--- a/llvm/test/CodeGen/PowerPC/vec_constants.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_constants.ll
@@ -17,14 +17,14 @@ define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind {
 	store <4 x float> %tmp13, <4 x float>* %P3
 	ret void
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NOT: CPI
 }
 
 define <4 x i32> @test_30() nounwind {
 	ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 >
 
-; CHECK: test_30:
+; CHECK-LABEL: test_30:
 ; CHECK: vspltisw
 ; CHECK-NEXT: vadduwm
 ; CHECK-NEXT: blr
@@ -33,7 +33,7 @@ define <4 x i32> @test_30() nounwind {
 define <4 x i32> @test_29() nounwind {
 	ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 >
 
-; CHECK: test_29:
+; CHECK-LABEL: test_29:
 ; CHECK: vspltisw
 ; CHECK-NEXT: vspltisw
 ; CHECK-NEXT: vsubuwm
@@ -43,7 +43,7 @@ define <4 x i32> @test_29() nounwind {
 define <8 x i16> @test_n30() nounwind {
 	ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 >
 
-; CHECK: test_n30:
+; CHECK-LABEL: test_n30:
 ; CHECK: vspltish
 ; CHECK-NEXT: vadduhm
 ; CHECK-NEXT: blr
@@ -52,7 +52,7 @@ define <8 x i16> @test_n30() nounwind {
 define <16 x i8> @test_n104() nounwind {
 	ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 >
 
-; CHECK: test_n104:
+; CHECK-LABEL: test_n104:
 ; CHECK: vspltisb
 ; CHECK-NEXT: vslb
 ; CHECK-NEXT: blr
@@ -61,7 +61,7 @@ define <16 x i8> @test_n104() nounwind {
 define <4 x i32> @test_vsldoi() nounwind {
 	ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 >
 
-; CHECK: test_vsldoi:
+; CHECK-LABEL: test_vsldoi:
 ; CHECK: vspltisw
 ; CHECK-NEXT: vsldoi
 ; CHECK-NEXT: blr
@@ -70,7 +70,7 @@ define <4 x i32> @test_vsldoi() nounwind {
 define <8 x i16> @test_vsldoi_65023() nounwind {
 	ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 >
 
-; CHECK: test_vsldoi_65023:
+; CHECK-LABEL: test_vsldoi_65023:
 ; CHECK: vspltish
 ; CHECK-NEXT: vsldoi
 ; CHECK-NEXT: blr
@@ -79,7 +79,7 @@ define <8 x i16> @test_vsldoi_65023() nounwind {
 define <4 x i32> @test_rol() nounwind {
 	ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
 
-; CHECK: test_rol:
+; CHECK-LABEL: test_rol:
 ; CHECK: vspltisw
 ; CHECK-NEXT: vrlw
 ; CHECK-NEXT: blr
diff --git a/llvm/test/CodeGen/PowerPC/vec_mul.ll b/llvm/test/CodeGen/PowerPC/vec_mul.ll
index 53bc75d..c376751 100644
--- a/llvm/test/CodeGen/PowerPC/vec_mul.ll
+++ b/llvm/test/CodeGen/PowerPC/vec_mul.ll
@@ -6,7 +6,7 @@ define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
 	%tmp3 = mul <4 x i32> %tmp, %tmp2		; <<4 x i32>> [#uses=1]
 	ret <4 x i32> %tmp3
 }
-; CHECK: test_v4i32:
+; CHECK-LABEL: test_v4i32:
 ; CHECK: vmsumuhm
 ; CHECK-NOT: mullw
 
@@ -16,7 +16,7 @@ define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) {
 	%tmp3 = mul <8 x i16> %tmp, %tmp2		; <<8 x i16>> [#uses=1]
 	ret <8 x i16> %tmp3
 }
-; CHECK: test_v8i16:
+; CHECK-LABEL: test_v8i16:
 ; CHECK: vmladduhm
 ; CHECK-NOT: mullw
 
@@ -26,7 +26,7 @@ define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) {
 	%tmp3 = mul <16 x i8> %tmp, %tmp2		; <<16 x i8>> [#uses=1]
 	ret <16 x i8> %tmp3
 }
-; CHECK: test_v16i8:
+; CHECK-LABEL: test_v16i8:
 ; CHECK: vmuloub
 ; CHECK: vmuleub
 ; CHECK-NOT: mullw
@@ -40,7 +40,7 @@ define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) {
 ; Check the creation of a negative zero float vector by creating a vector of
 ; all bits set and shifting it 31 bits to left, resulting a an vector of 
 ; 4 x 0x80000000 (-0.0 as float).
-; CHECK: test_float:
+; CHECK-LABEL: test_float:
 ; CHECK: vspltisw [[ZNEG:[0-9]+]], -1
 ; CHECK: vslw     {{[0-9]+}}, [[ZNEG]], [[ZNEG]]
 ; CHECK: vmaddfp
diff --git a/llvm/test/CodeGen/SPARC/basictest.ll b/llvm/test/CodeGen/SPARC/basictest.ll
index ce60653..7004af9 100644
--- a/llvm/test/CodeGen/SPARC/basictest.ll
+++ b/llvm/test/CodeGen/SPARC/basictest.ll
@@ -3,7 +3,7 @@
 define i32 @test0(i32 %X) {
 	%tmp.1 = add i32 %X, 1
 	ret i32 %tmp.1
-; CHECK: test0:
+; CHECK-LABEL: test0:
 ; CHECK: add %o0, 1, %o0
 }
 
@@ -13,7 +13,7 @@ define i32 @test1(i32 %X, i32 %Y) {
         %A = xor i32 %X, %Y
         %B = xor i32 %A, -1
         ret i32 %B
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: xnor %o0, %o1, %o0
 }
 
@@ -21,7 +21,7 @@ define i32 @test2(i32 %X, i32 %Y) {
         %A = xor i32 %X, -1
         %B = xor i32 %A, %Y
         ret i32 %B
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: xnor %o0, %o1, %o0
 }
 
diff --git a/llvm/test/CodeGen/SPARC/float.ll b/llvm/test/CodeGen/SPARC/float.ll
index ab46fb3..b35eb6c 100644
--- a/llvm/test/CodeGen/SPARC/float.ll
+++ b/llvm/test/CodeGen/SPARC/float.ll
@@ -3,7 +3,7 @@
 ; RUN: llc -march=sparc -mattr=v9 < %s | FileCheck %s -check-prefix=V9
 
 
-; V8:     test_neg:
+; V8-LABEL:     test_neg:
 ; V8:     call get_double
 ; V8:     fnegs %f0, %f0
 
@@ -13,7 +13,7 @@
 ; V8-UNOPT:     fmovs {{.+}}, %f0
 ; V8-UNOPT:     fmovs {{.+}}, %f1
 
-; V9:     test_neg:
+; V9-LABEL:     test_neg:
 ; V9:     fnegd %f0, %f0
 
 define double @test_neg() {
@@ -23,7 +23,7 @@ entry:
   ret double %1
 }
 
-; V8:     test_abs:
+; V8-LABEL:     test_abs:
 ; V8:     fabss %f0, %f0
 
 ; V8-UNOPT:     test_abs:
@@ -32,7 +32,7 @@ entry:
 ; V8-UNOPT:     fmovs {{.+}}, %f0
 ; V8-UNOPT:     fmovs {{.+}}, %f1
 
-; V9:     test_abs:
+; V9-LABEL:     test_abs:
 ; V9:     fabsd %f0, %f0
 
 define double @test_abs() {
diff --git a/llvm/test/CodeGen/Thumb/ispositive.ll b/llvm/test/CodeGen/Thumb/ispositive.ll
index eac3ef2..7b28227 100644
--- a/llvm/test/CodeGen/Thumb/ispositive.ll
+++ b/llvm/test/CodeGen/Thumb/ispositive.ll
@@ -2,7 +2,7 @@
 
 define i32 @test1(i32 %X) {
 entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: lsrs r0, r0, #31
         icmp slt i32 %X, 0              ; <i1>:0 [#uses=1]
         zext i1 %0 to i32               ; <i32>:1 [#uses=1]
diff --git a/llvm/test/CodeGen/Thumb/large-stack.ll b/llvm/test/CodeGen/Thumb/large-stack.ll
index 680976e..6fa6231 100644
--- a/llvm/test/CodeGen/Thumb/large-stack.ll
+++ b/llvm/test/CodeGen/Thumb/large-stack.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=thumb-apple-ios | FileCheck %s
 
 define void @test1() {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: sub sp, #256
 ; CHECK: add sp, #256
     %tmp = alloca [ 64 x i32 ] , align 4
@@ -9,7 +9,7 @@ define void @test1() {
 }
 
 define void @test2() {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: ldr.n r0, LCPI
 ; CHECK: add sp, r0
 ; CHECK: subs r4, r7, #4
@@ -19,7 +19,7 @@ define void @test2() {
 }
 
 define i32 @test3() {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: ldr.n r1, LCPI
 ; CHECK: add sp, r1
 ; CHECK: ldr.n r1, LCPI
diff --git a/llvm/test/CodeGen/Thumb/rev.ll b/llvm/test/CodeGen/Thumb/rev.ll
index 5e163f8..dcba00e 100644
--- a/llvm/test/CodeGen/Thumb/rev.ll
+++ b/llvm/test/CodeGen/Thumb/rev.ll
@@ -32,7 +32,7 @@ define i32 @test2(i32 %X) nounwind {
 ; rdar://9147637
 define i32 @test3(i16 zeroext %a) nounwind {
 entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: revsh r0, r0
   %0 = tail call i16 @llvm.bswap.i16(i16 %a)
   %1 = sext i16 %0 to i32
@@ -43,7 +43,7 @@ declare i16 @llvm.bswap.i16(i16) nounwind readnone
 
 define i32 @test4(i16 zeroext %a) nounwind {
 entry:
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: revsh r0, r0
   %conv = zext i16 %a to i32
   %shr9 = lshr i16 %a, 8
diff --git a/llvm/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll b/llvm/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll
index c153092..c662620 100644
--- a/llvm/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll
+++ b/llvm/test/CodeGen/Thumb2/2010-02-11-phi-cycle.ll
@@ -2,7 +2,7 @@
 target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32-n32"
 
 define i32 @test(i32 %n) nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: mov
 ; CHECK: return
 entry:
@@ -30,7 +30,7 @@ return:                                           ; preds = %bb, %entry
 }
 
 define i32 @test_dead_cycle(i32 %n) nounwind {
-; CHECK: test_dead_cycle:
+; CHECK-LABEL: test_dead_cycle:
 ; CHECK: blx
 ; CHECK-NOT: mov
 ; CHECK: blx
diff --git a/llvm/test/CodeGen/Thumb2/2013-03-06-vector-sext-operand-scalarize.ll b/llvm/test/CodeGen/Thumb2/2013-03-06-vector-sext-operand-scalarize.ll
index 203815f..974fade 100644
--- a/llvm/test/CodeGen/Thumb2/2013-03-06-vector-sext-operand-scalarize.ll
+++ b/llvm/test/CodeGen/Thumb2/2013-03-06-vector-sext-operand-scalarize.ll
@@ -3,7 +3,7 @@
 ; Testing that these don't crash/assert. The loop vectorizer can end up
 ; with odd constructs like this. The code actually generated is incidental.
 define <1 x i64> @test_zext(i32 %a) nounwind {
-; CHECK: test_zext:
+; CHECK-LABEL: test_zext:
   %Cmp = icmp uge i32 %a, 42
   %vec = insertelement <1 x i1> zeroinitializer, i1 %Cmp, i32 0
   %Se = zext <1 x i1> %vec to <1 x i64>
@@ -11,7 +11,7 @@ define <1 x i64> @test_zext(i32 %a) nounwind {
 }
 
 define <1 x i64> @test_sext(i32 %a) nounwind {
-; CHECK: test_sext:
+; CHECK-LABEL: test_sext:
   %Cmp = icmp uge i32 %a, 42
   %vec = insertelement <1 x i1> zeroinitializer, i1 %Cmp, i32 0
   %Se = sext <1 x i1> %vec to <1 x i64>
diff --git a/llvm/test/CodeGen/Thumb2/large-stack.ll b/llvm/test/CodeGen/Thumb2/large-stack.ll
index 68b5d1c..36f3ce2 100644
--- a/llvm/test/CodeGen/Thumb2/large-stack.ll
+++ b/llvm/test/CodeGen/Thumb2/large-stack.ll
@@ -2,19 +2,19 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 -mtriple=arm-linux-gnueabi | FileCheck %s -check-prefix=LINUX
 
 define void @test1() {
-; DARWIN: test1:
+; DARWIN-LABEL: test1:
 ; DARWIN: sub sp, #256
-; LINUX: test1:
+; LINUX-LABEL: test1:
 ; LINUX: sub sp, #256
     %tmp = alloca [ 64 x i32 ] , align 4
     ret void
 }
 
 define void @test2() {
-; DARWIN: test2:
+; DARWIN-LABEL: test2:
 ; DARWIN: sub.w sp, sp, #4160
 ; DARWIN: sub sp, #8
-; LINUX: test2:
+; LINUX-LABEL: test2:
 ; LINUX: sub.w sp, sp, #4160
 ; LINUX: sub sp, #8
     %tmp = alloca [ 4168 x i8 ] , align 4
@@ -22,11 +22,11 @@ define void @test2() {
 }
 
 define i32 @test3() {
-; DARWIN: test3:
+; DARWIN-LABEL: test3:
 ; DARWIN: push    {r4, r7, lr}
 ; DARWIN: sub.w sp, sp, #805306368
 ; DARWIN: sub sp, #20
-; LINUX: test3:
+; LINUX-LABEL: test3:
 ; LINUX: push.w {r4, r7, r11, lr}
 ; LINUX: sub.w sp, sp, #805306368
 ; LINUX: sub sp, #16
diff --git a/llvm/test/CodeGen/Thumb2/thumb2-pack.ll b/llvm/test/CodeGen/Thumb2/thumb2-pack.ll
index 5deae1b..1052dd2 100644
--- a/llvm/test/CodeGen/Thumb2/thumb2-pack.ll
+++ b/llvm/test/CodeGen/Thumb2/thumb2-pack.ll
@@ -99,7 +99,7 @@ define i32 @test8(i32 %X, i32 %Y) {
 	ret i32 %tmp57
 }
 
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: pkhtb r0, r0, r1, asr #16
 define i32 @test9(i32 %src1, i32 %src2) {
 entry:
diff --git a/llvm/test/CodeGen/Thumb2/thumb2-str_post.ll b/llvm/test/CodeGen/Thumb2/thumb2-str_post.ll
index bbfb447..2133d28 100644
--- a/llvm/test/CodeGen/Thumb2/thumb2-str_post.ll
+++ b/llvm/test/CodeGen/Thumb2/thumb2-str_post.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=thumb -mattr=+thumb2 | FileCheck %s
 
 define i16 @test1(i32* %X, i16* %A) {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: strh {{.*}}[{{.*}}], #-4
         %Y = load i32* %X               ; <i32> [#uses=1]
         %tmp1 = trunc i32 %Y to i16             ; <i16> [#uses=1]
@@ -12,7 +12,7 @@ define i16 @test1(i32* %X, i16* %A) {
 }
 
 define i32 @test2(i32* %X, i32* %A) {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: str {{.*}}[{{.*}}],
         %Y = load i32* %X               ; <i32> [#uses=1]
         store i32 %Y, i32* %A
diff --git a/llvm/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll b/llvm/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll
index ab888e6..792ebef 100644
--- a/llvm/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll
+++ b/llvm/test/CodeGen/Thumb2/thumb2-sxt-uxt.ll
@@ -1,28 +1,28 @@
 ; RUN: llc < %s -march=thumb -mcpu=cortex-m3 | FileCheck %s
 
 define i32 @test1(i16 zeroext %z) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: sxth
   %r = sext i16 %z to i32
   ret i32 %r
 }
 
 define i32 @test2(i8 zeroext %z) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: sxtb
   %r = sext i8 %z to i32
   ret i32 %r
 }
 
 define i32 @test3(i16 signext %z) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: uxth
   %r = zext i16 %z to i32
   ret i32 %r
 }
 
 define i32 @test4(i8 signext %z) nounwind {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: uxtb
   %r = zext i8 %z to i32
   ret i32 %r
diff --git a/llvm/test/CodeGen/X86/2007-02-04-OrAddrMode.ll b/llvm/test/CodeGen/X86/2007-02-04-OrAddrMode.ll
index b0eb1c5..cea4d9d 100644
--- a/llvm/test/CodeGen/X86/2007-02-04-OrAddrMode.ll
+++ b/llvm/test/CodeGen/X86/2007-02-04-OrAddrMode.ll
@@ -2,7 +2,7 @@
 
 ;; This example can't fold the or into an LEA.
 define i32 @test(float ** %tmp2, i32 %tmp12) nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: ret
 ; CHECK: orl $1, %{{.*}}
 ; CHECK: ret
@@ -18,7 +18,7 @@ define i32 @test(float ** %tmp2, i32 %tmp12) nounwind {
 
 ;; This can!
 define i32 @test2(i32 %a, i32 %b) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK-NOT: ret
 ; CHECK: leal 3(,%{{.*}},8)
 ; CHECK: ret
diff --git a/llvm/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll b/llvm/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll
index b48ce84..cbc1bc4 100644
--- a/llvm/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll
+++ b/llvm/test/CodeGen/X86/2007-02-23-DAGCombine-Miscompile.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=x86 | FileCheck %s
 
 define i32 @test(i1 %X) {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: ret
 ; CHECK: movl $1, %eax
 ; CHECK: ret
diff --git a/llvm/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll b/llvm/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
index e2cd750..3e1786b 100644
--- a/llvm/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
+++ b/llvm/test/CodeGen/X86/2007-03-24-InlineAsmXConstraint.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:32:32"
 target triple = "i686-apple-darwin9"
 
 define void @test() {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: ret
 ; CHECK: psrlw $8, %xmm0
 ; CHECK: ret
diff --git a/llvm/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll b/llvm/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll
index 6e9a629..d4805b4 100644
--- a/llvm/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll
+++ b/llvm/test/CodeGen/X86/2008-04-26-Asm-Optimize-Imm.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 target triple = "i386-apple-darwin8"
 
 define void @test() nounwind  {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: ret
 ; CHECK: 1 $2 3
 ; CHECK: ret
diff --git a/llvm/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll b/llvm/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll
index 39c213f..7515e80 100644
--- a/llvm/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll
+++ b/llvm/test/CodeGen/X86/2011-12-26-extractelement-duplicate-load.ll
@@ -5,7 +5,7 @@
 ; the chains correctly.
 ; PR10747
 
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: pextrd $2, %xmm
 define <4 x i32> @test(<4 x i32>* %p) {
   %v = load <4 x i32>* %p
diff --git a/llvm/test/CodeGen/X86/3addr-or.ll b/llvm/test/CodeGen/X86/3addr-or.ll
index 912bdc2..76fabbf 100644
--- a/llvm/test/CodeGen/X86/3addr-or.ll
+++ b/llvm/test/CodeGen/X86/3addr-or.ll
@@ -3,7 +3,7 @@
 
 define i32 @test1(i32 %x) nounwind readnone ssp {
 entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: leal 3(%rdi), %eax
   %0 = shl i32 %x, 5                              ; <i32> [#uses=1]
   %1 = or i32 %0, 3                               ; <i32> [#uses=1]
@@ -11,7 +11,7 @@ entry:
 }
 
 define i64 @test2(i8 %A, i8 %B) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: shrq $4
 ; CHECK-NOT: movq
 ; CHECK-NOT: orq
@@ -31,7 +31,7 @@ define i64 @test2(i8 %A, i8 %B) nounwind {
 define void @test3(i32 %x, i32* %P) nounwind readnone ssp {
 entry:
 ; No reason to emit an add here, should be an or.
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: orl $3, %edi
   %0 = shl i32 %x, 5
   %1 = or i32 %0, 3
@@ -45,7 +45,7 @@ entry:
   %and2 = and i32 %b, 16
   %or = or i32 %and2, %and
   ret i32 %or
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: leal	(%rsi,%rdi), %eax
 }
 
@@ -56,6 +56,6 @@ entry:
   %or = or i32 %and2, %and
   store i32 %or, i32* %P, align 4
   ret void
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: orl
 }
diff --git a/llvm/test/CodeGen/X86/add-of-carry.ll b/llvm/test/CodeGen/X86/add-of-carry.ll
index 4e30f2b..1513fcb 100644
--- a/llvm/test/CodeGen/X86/add-of-carry.ll
+++ b/llvm/test/CodeGen/X86/add-of-carry.ll
@@ -3,7 +3,7 @@
 
 define i32 @test1(i32 %sum, i32 %x) nounwind readnone ssp {
 entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: cmpl %ecx, %eax
 ; CHECK-NOT: addl
 ; CHECK: adcl $0, %eax
@@ -15,7 +15,7 @@ entry:
 }
 
 ; Instcombine transforms test1 into test2:
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movl
 ; CHECK-NEXT: addl
 ; CHECK-NEXT: adcl $0
@@ -37,7 +37,7 @@ entry:
   %dec = sext i1 %cmp to i32
   %dec.res = add nsw i32 %dec, %res
   ret i32 %dec.res
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: cmpl
 ; CHECK: sbbl
 ; CHECK: ret
diff --git a/llvm/test/CodeGen/X86/add.ll b/llvm/test/CodeGen/X86/add.ll
index 5fe08ed..f36577b 100644
--- a/llvm/test/CodeGen/X86/add.ll
+++ b/llvm/test/CodeGen/X86/add.ll
@@ -39,11 +39,11 @@ normal:
 overflow:
   ret i1 false
   
-; X32: test4:
+; X32-LABEL: test4:
 ; X32: addl
 ; X32-NEXT: jo
 
-; X64:        test4:
+; X64-LABEL:        test4:
 ; X64:          addl	%e[[A1:si|dx]], %e[[A0:di|cx]]
 ; X64-NEXT:	jo
 }
@@ -62,11 +62,11 @@ normal:
 carry:
   ret i1 false
 
-; X32: test5:
+; X32-LABEL: test5:
 ; X32: addl
 ; X32-NEXT: jb
 
-; X64:        test5:
+; X64-LABEL:        test5:
 ; X64:          addl	%e[[A1]], %e[[A0]]
 ; X64-NEXT:	jb
 }
@@ -81,13 +81,13 @@ define i64 @test6(i64 %A, i32 %B) nounwind {
         %tmp5 = add i64 %tmp3, %A               ; <i64> [#uses=1]
         ret i64 %tmp5
 
-; X32: test6:
+; X32-LABEL: test6:
 ; X32:	    movl 12(%esp), %edx
 ; X32-NEXT: addl 8(%esp), %edx
 ; X32-NEXT: movl 4(%esp), %eax
 ; X32-NEXT: ret
         
-; X64: test6:
+; X64-LABEL: test6:
 ; X64:	shlq	$32, %r[[A1]]
 ; X64:	leaq	(%r[[A1]],%r[[A0]]), %rax
 ; X64:	ret
@@ -98,7 +98,7 @@ define {i32, i1} @test7(i32 %v1, i32 %v2) nounwind {
    ret {i32, i1} %t
 }
 
-; X64: test7:
+; X64-LABEL: test7:
 ; X64: addl %e[[A1]], %e
 ; X64-NEXT: setb %dl
 ; X64: ret
@@ -117,7 +117,7 @@ entry:
     ret {i64, i1} %final1
 }
 
-; X64: test8:
+; X64-LABEL: test8:
 ; X64: addq
 ; X64-NEXT: setb
 ; X64: ret
@@ -127,7 +127,7 @@ define i32 @test9(i32 %x, i32 %y) nounwind readnone {
   %sub = sext i1 %cmp to i32
   %cond = add i32 %sub, %y
   ret i32 %cond
-; X64: test9:
+; X64-LABEL: test9:
 ; X64: cmpl $10
 ; X64: sete
 ; X64: subl
@@ -140,11 +140,11 @@ entry:
   %obit = extractvalue {i32, i1} %t, 1
   ret i1 %obit
 
-; X32: test10:
+; X32-LABEL: test10:
 ; X32: incl
 ; X32-NEXT: seto
 
-; X64: test10:
+; X64-LABEL: test10:
 ; X64: incl
 ; X64-NEXT: seto
 }
diff --git a/llvm/test/CodeGen/X86/asm-modifier.ll b/llvm/test/CodeGen/X86/asm-modifier.ll
index 44f972e..47b185a 100644
--- a/llvm/test/CodeGen/X86/asm-modifier.ll
+++ b/llvm/test/CodeGen/X86/asm-modifier.ll
@@ -5,7 +5,7 @@ target triple = "i386-apple-darwin9.6"
 
 define i32 @test1() nounwind {
 entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: movw	%gs:6, %ax
   %asmtmp.i = tail call i16 asm "movw\09%gs:${1:a}, ${0:w}", "=r,ir,~{dirflag},~{fpsr},~{flags}"(i32 6) nounwind ; <i16> [#uses=1]
   %0 = zext i16 %asmtmp.i to i32                  ; <i32> [#uses=1]
@@ -14,7 +14,7 @@ entry:
 
 define zeroext i16 @test2(i32 %address) nounwind {
 entry:
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movw	%gs:(%eax), %ax
   %asmtmp = tail call i16 asm "movw\09%gs:${1:a}, ${0:w}", "=r,ir,~{dirflag},~{fpsr},~{flags}"(i32 %address) nounwind ; <i16> [#uses=1]
   ret i16 %asmtmp
@@ -25,7 +25,7 @@ entry:
 
 define void @test3() nounwind {
 entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: movl _n, %eax
   call void asm sideeffect "movl ${0:a}, %eax", "ir,~{dirflag},~{fpsr},~{flags},~{eax}"(i32* @n) nounwind
   ret void
@@ -33,7 +33,7 @@ entry:
 
 define void @test4() nounwind {
 entry:
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: movl	L_y$non_lazy_ptr, %ecx
 ; CHECK: movl (%ecx), %eax
   call void asm sideeffect "movl ${0:a}, %eax", "ir,~{dirflag},~{fpsr},~{flags},~{eax}"(i32* @y) nounwind
diff --git a/llvm/test/CodeGen/X86/atom-lea-sp.ll b/llvm/test/CodeGen/X86/atom-lea-sp.ll
index 19482e1..1df1974 100644
--- a/llvm/test/CodeGen/X86/atom-lea-sp.ll
+++ b/llvm/test/CodeGen/X86/atom-lea-sp.ll
@@ -5,13 +5,13 @@ declare void @use_arr(i8*)
 declare void @many_params(i32, i32, i32, i32, i32, i32)
 
 define void @test1() nounwind {
-; ATOM: test1:
+; ATOM-LABEL: test1:
 ; ATOM: leal -1052(%esp), %esp
 ; ATOM-NOT: sub
 ; ATOM: call
 ; ATOM: leal 1052(%esp), %esp
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: subl
 ; CHECK: call
 ; CHECK-NOT: lea
@@ -22,23 +22,23 @@ define void @test1() nounwind {
 }
 
 define void @test2() nounwind {
-; ATOM: test2:
+; ATOM-LABEL: test2:
 ; ATOM: leal -28(%esp), %esp
 ; ATOM: call
 ; ATOM: leal 28(%esp), %esp
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK-NOT: lea
   call void @many_params(i32 1, i32 2, i32 3, i32 4, i32 5, i32 6)
   ret void
 }
 
 define void @test3() nounwind {
-; ATOM: test3:
+; ATOM-LABEL: test3:
 ; ATOM: leal -8(%esp), %esp
 ; ATOM: leal 8(%esp), %esp
 
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK-NOT: lea
   %x = alloca i32, align 4
   %y = alloca i32, align 4
diff --git a/llvm/test/CodeGen/X86/avx-brcond.ll b/llvm/test/CodeGen/X86/avx-brcond.ll
index d52ae52..4313a15 100644
--- a/llvm/test/CodeGen/X86/avx-brcond.ll
+++ b/llvm/test/CodeGen/X86/avx-brcond.ll
@@ -5,7 +5,7 @@ declare i32 @llvm.x86.avx.ptestc.256(<4 x i64> %p1, <4 x i64> %p2) nounwind
 
 define <4 x float> @test1(<4 x i64> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: vptest
 ; CHECK-NEXT:	jne
 ; CHECK: ret
@@ -29,7 +29,7 @@ return:
 
 define <4 x float> @test3(<4 x i64> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: vptest
 ; CHECK-NEXT:	jne
 ; CHECK: ret
@@ -53,7 +53,7 @@ return:
 
 define <4 x float> @test4(<4 x i64> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: vptest
 ; CHECK-NEXT:	jae
 ; CHECK: ret
@@ -77,7 +77,7 @@ return:
 
 define <4 x float> @test6(<4 x i64> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: vptest
 ; CHECK-NEXT:	jae
 ; CHECK: ret
@@ -101,7 +101,7 @@ return:
 
 define <4 x float> @test7(<4 x i64> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: vptest
 ; CHECK-NEXT:	jne
 ; CHECK: ret
@@ -125,7 +125,7 @@ return:
 
 define <4 x float> @test8(<4 x i64> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: vptest
 ; CHECK-NEXT:	je
 ; CHECK: ret
diff --git a/llvm/test/CodeGen/X86/avx-fp2int.ll b/llvm/test/CodeGen/X86/avx-fp2int.ll
index a3aadde..8beaac6 100644
--- a/llvm/test/CodeGen/X86/avx-fp2int.ll
+++ b/llvm/test/CodeGen/X86/avx-fp2int.ll
@@ -2,10 +2,10 @@
 
 ;; Check that FP_TO_SINT and FP_TO_UINT generate convert with truncate
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: vcvttpd2dqy
 ; CHECK: ret
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: vcvttpd2dqy
 ; CHECK: ret
 
diff --git a/llvm/test/CodeGen/X86/avx-shuffle.ll b/llvm/test/CodeGen/X86/avx-shuffle.ll
index 73faa1f..655902a8 100644
--- a/llvm/test/CodeGen/X86/avx-shuffle.ll
+++ b/llvm/test/CodeGen/X86/avx-shuffle.ll
@@ -4,14 +4,14 @@
 define <4 x float> @test1(<4 x float> %a) nounwind {
   %b = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 undef, i32 undef>
   ret <4 x float> %b
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: vshufps
 ; CHECK: vpshufd
 }
 
 ; rdar://10538417
 define <3 x i64> @test2(<2 x i64> %v) nounwind readnone {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: vinsertf128
   %1 = shufflevector <2 x i64> %v, <2 x i64> %v, <3 x i32> <i32 0, i32 1, i32 undef>
   %2 = shufflevector <3 x i64> zeroinitializer, <3 x i64> %1, <3 x i32> <i32 3, i32 4, i32 2>
@@ -22,7 +22,7 @@ define <3 x i64> @test2(<2 x i64> %v) nounwind readnone {
 define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind {
   %c = shufflevector <4 x i64> %a, <4 x i64> %b, <4 x i32> <i32 4, i32 5, i32 2, i32 undef>
   ret <4 x i64> %c
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: vperm2f128
 ; CHECK: ret
 }
@@ -30,7 +30,7 @@ define <4 x i64> @test3(<4 x i64> %a, <4 x i64> %b) nounwind {
 define <8 x float> @test4(float %a) nounwind {
   %b = insertelement <8 x float> zeroinitializer, float %a, i32 0
   ret <8 x float> %b
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: vinsertf128
 }
 
diff --git a/llvm/test/CodeGen/X86/avx-varargs-x86_64.ll b/llvm/test/CodeGen/X86/avx-varargs-x86_64.ll
index b0932bd..f73174d 100644
--- a/llvm/test/CodeGen/X86/avx-varargs-x86_64.ll
+++ b/llvm/test/CodeGen/X86/avx-varargs-x86_64.ll
@@ -5,7 +5,7 @@
 @x = common global <8 x float> zeroinitializer, align 32
 declare i32 @f(i32, ...)
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: vmovaps	%ymm0, (%rsp)
 define void @test1() nounwind uwtable ssp {
 entry:
diff --git a/llvm/test/CodeGen/X86/avx2-arith.ll b/llvm/test/CodeGen/X86/avx2-arith.ll
index 2c0b668..dee4bd3c 100644
--- a/llvm/test/CodeGen/X86/avx2-arith.ll
+++ b/llvm/test/CodeGen/X86/avx2-arith.ll
@@ -146,4 +146,4 @@ define <8 x i16> @mul_const8(<8 x i16> %x) {
 define <8 x i32> @mul_const9(<8 x i32> %x) {
   %y = mul <8 x i32> %x, <i32 2, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0>
   ret <8 x i32> %y
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/X86/avx2-palignr.ll b/llvm/test/CodeGen/X86/avx2-palignr.ll
index 53b9da3..176e02c 100644
--- a/llvm/test/CodeGen/X86/avx2-palignr.ll
+++ b/llvm/test/CodeGen/X86/avx2-palignr.ll
@@ -1,56 +1,56 @@
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core-avx2 -mattr=+avx2 | FileCheck %s
 
 define <8 x i32> @test1(<8 x i32> %A, <8 x i32> %B) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: vpalignr $4
   %C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 7, i32 12>
   ret <8 x i32> %C
 }
 
 define <8 x i32> @test2(<8 x i32> %A, <8 x i32> %B) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: vpalignr $4
   %C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 1, i32 2, i32 3, i32 8, i32 5, i32 6, i32 undef, i32 12>
   ret <8 x i32> %C
 }
 
 define <8 x i32> @test3(<8 x i32> %A, <8 x i32> %B) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: vpalignr $4
   %C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 1, i32 undef, i32 3, i32 8, i32 5, i32 6, i32 7, i32 12>
   ret <8 x i32> %C
 }
 ;
 define <8 x i32> @test4(<8 x i32> %A, <8 x i32> %B) nounwind {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: vpalignr $8
   %C = shufflevector <8 x i32> %A, <8 x i32> %B, <8 x i32> <i32 10, i32 11, i32 undef, i32 1, i32 14, i32 15, i32 4, i32 5>
   ret <8 x i32> %C
 }
 
 define <16 x i16> @test5(<16 x i16> %A, <16 x i16> %B) nounwind {
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: vpalignr $6
   %C = shufflevector <16 x i16> %A, <16 x i16> %B, <16 x i32> <i32 3, i32 4, i32 undef, i32 6, i32 7, i32 16, i32 17, i32 18, i32 11, i32 12, i32 13, i32 undef, i32 15, i32 24, i32 25, i32 26>
   ret <16 x i16> %C
 }
 
 define <16 x i16> @test6(<16 x i16> %A, <16 x i16> %B) nounwind {
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: vpalignr $6
   %C = shufflevector <16 x i16> %A, <16 x i16> %B, <16 x i32> <i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 11, i32 12, i32 13, i32 undef, i32 15, i32 24, i32 25, i32 26>
   ret <16 x i16> %C
 }
 
 define <16 x i16> @test7(<16 x i16> %A, <16 x i16> %B) nounwind {
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: vpalignr $6
   %C = shufflevector <16 x i16> %A, <16 x i16> %B, <16 x i32> <i32 3, i32 4, i32 5, i32 6, i32 7, i32 16, i32 17, i32 18, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   ret <16 x i16> %C
 }
 
 define <32 x i8> @test8(<32 x i8> %A, <32 x i8> %B) nounwind {
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: palignr $5
   %C = shufflevector <32 x i8> %A, <32 x i8> %B, <32 x i32> <i32 5, i32 6, i32 7, i32 undef, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 32, i32 33, i32 34, i32 35, i32 36, i32 21, i32 22, i32 23, i32 24, i32 25, i32 26, i32 27, i32 28, i32 29, i32 30, i32 31, i32 48, i32 49, i32 50, i32 51, i32 52>
   ret <32 x i8> %C
diff --git a/llvm/test/CodeGen/X86/avx2-vector-shifts.ll b/llvm/test/CodeGen/X86/avx2-vector-shifts.ll
index ca18a60..a978d93 100644
--- a/llvm/test/CodeGen/X86/avx2-vector-shifts.ll
+++ b/llvm/test/CodeGen/X86/avx2-vector-shifts.ll
@@ -8,7 +8,7 @@ entry:
   ret <16 x i16> %shl
 }
 
-; CHECK: test_sllw_1:
+; CHECK-LABEL: test_sllw_1:
 ; CHECK: vpsllw  $0, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -18,7 +18,7 @@ entry:
   ret <16 x i16> %shl
 }
 
-; CHECK: test_sllw_2:
+; CHECK-LABEL: test_sllw_2:
 ; CHECK: vpaddw  %ymm0, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -28,7 +28,7 @@ entry:
   ret <16 x i16> %shl
 }
 
-; CHECK: test_sllw_3:
+; CHECK-LABEL: test_sllw_3:
 ; CHECK: vxorps  %ymm0, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -38,7 +38,7 @@ entry:
   ret <8 x i32> %shl
 }
 
-; CHECK: test_slld_1:
+; CHECK-LABEL: test_slld_1:
 ; CHECK: vpslld  $0, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -48,7 +48,7 @@ entry:
   ret <8 x i32> %shl
 }
 
-; CHECK: test_slld_2:
+; CHECK-LABEL: test_slld_2:
 ; CHECK: vpaddd  %ymm0, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -58,7 +58,7 @@ entry:
   ret <8 x i32> %shl
 }
 
-; CHECK: test_slld_3:
+; CHECK-LABEL: test_slld_3:
 ; CHECK: vxorps  %ymm0, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -68,7 +68,7 @@ entry:
   ret <4 x i64> %shl
 }
 
-; CHECK: test_sllq_1:
+; CHECK-LABEL: test_sllq_1:
 ; CHECK: vpsllq  $0, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -78,7 +78,7 @@ entry:
   ret <4 x i64> %shl
 }
 
-; CHECK: test_sllq_2:
+; CHECK-LABEL: test_sllq_2:
 ; CHECK: vpaddq  %ymm0, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -88,7 +88,7 @@ entry:
   ret <4 x i64> %shl
 }
 
-; CHECK: test_sllq_3:
+; CHECK-LABEL: test_sllq_3:
 ; CHECK: vxorps  %ymm0, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -100,7 +100,7 @@ entry:
   ret <16 x i16> %shl
 }
 
-; CHECK: test_sraw_1:
+; CHECK-LABEL: test_sraw_1:
 ; CHECK: vpsraw  $0, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -110,7 +110,7 @@ entry:
   ret <16 x i16> %shl
 }
 
-; CHECK: test_sraw_2:
+; CHECK-LABEL: test_sraw_2:
 ; CHECK: vpsraw  $1, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -120,7 +120,7 @@ entry:
   ret <16 x i16> %shl
 }
 
-; CHECK: test_sraw_3:
+; CHECK-LABEL: test_sraw_3:
 ; CHECK: vpsraw  $16, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -130,7 +130,7 @@ entry:
   ret <8 x i32> %shl
 }
 
-; CHECK: test_srad_1:
+; CHECK-LABEL: test_srad_1:
 ; CHECK: vpsrad  $0, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -140,7 +140,7 @@ entry:
   ret <8 x i32> %shl
 }
 
-; CHECK: test_srad_2:
+; CHECK-LABEL: test_srad_2:
 ; CHECK: vpsrad  $1, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -150,7 +150,7 @@ entry:
   ret <8 x i32> %shl
 }
 
-; CHECK: test_srad_3:
+; CHECK-LABEL: test_srad_3:
 ; CHECK: vpsrad  $32, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -162,7 +162,7 @@ entry:
   ret <16 x i16> %shl
 }
 
-; CHECK: test_srlw_1:
+; CHECK-LABEL: test_srlw_1:
 ; CHECK: vpsrlw  $0, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -172,7 +172,7 @@ entry:
   ret <16 x i16> %shl
 }
 
-; CHECK: test_srlw_2:
+; CHECK-LABEL: test_srlw_2:
 ; CHECK: vpsrlw  $1, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -182,7 +182,7 @@ entry:
   ret <16 x i16> %shl
 }
 
-; CHECK: test_srlw_3:
+; CHECK-LABEL: test_srlw_3:
 ; CHECK: vxorps  %ymm0, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -192,7 +192,7 @@ entry:
   ret <8 x i32> %shl
 }
 
-; CHECK: test_srld_1:
+; CHECK-LABEL: test_srld_1:
 ; CHECK: vpsrld  $0, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -202,7 +202,7 @@ entry:
   ret <8 x i32> %shl
 }
 
-; CHECK: test_srld_2:
+; CHECK-LABEL: test_srld_2:
 ; CHECK: vpsrld  $1, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -212,7 +212,7 @@ entry:
   ret <8 x i32> %shl
 }
 
-; CHECK: test_srld_3:
+; CHECK-LABEL: test_srld_3:
 ; CHECK: vxorps  %ymm0, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -222,7 +222,7 @@ entry:
   ret <4 x i64> %shl
 }
 
-; CHECK: test_srlq_1:
+; CHECK-LABEL: test_srlq_1:
 ; CHECK: vpsrlq  $0, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -232,7 +232,7 @@ entry:
   ret <4 x i64> %shl
 }
 
-; CHECK: test_srlq_2:
+; CHECK-LABEL: test_srlq_2:
 ; CHECK: vpsrlq  $1, %ymm0, %ymm0
 ; CHECK: ret
 
@@ -242,6 +242,6 @@ entry:
   ret <4 x i64> %shl
 }
 
-; CHECK: test_srlq_3:
+; CHECK-LABEL: test_srlq_3:
 ; CHECK: vxorps  %ymm0, %ymm0, %ymm0
 ; CHECK: ret
diff --git a/llvm/test/CodeGen/X86/block-placement.ll b/llvm/test/CodeGen/X86/block-placement.ll
index 139f8b0..d3e05d6 100644
--- a/llvm/test/CodeGen/X86/block-placement.ll
+++ b/llvm/test/CodeGen/X86/block-placement.ll
@@ -5,7 +5,7 @@ declare void @error(i32 %i, i32 %a, i32 %b)
 define i32 @test_ifchains(i32 %i, i32* %a, i32 %b) {
 ; Test a chain of ifs, where the block guarded by the if is error handling code
 ; that is not expected to run.
-; CHECK: test_ifchains:
+; CHECK-LABEL: test_ifchains:
 ; CHECK: %entry
 ; CHECK-NOT: .align
 ; CHECK: %else1
@@ -79,7 +79,7 @@ exit:
 
 define i32 @test_loop_cold_blocks(i32 %i, i32* %a) {
 ; Check that we sink cold loop blocks after the hot loop body.
-; CHECK: test_loop_cold_blocks:
+; CHECK-LABEL: test_loop_cold_blocks:
 ; CHECK: %entry
 ; CHECK-NOT: .align
 ; CHECK: %unlikely1
@@ -128,7 +128,7 @@ exit:
 
 define i32 @test_loop_early_exits(i32 %i, i32* %a) {
 ; Check that we sink early exit blocks out of loop bodies.
-; CHECK: test_loop_early_exits:
+; CHECK-LABEL: test_loop_early_exits:
 ; CHECK: %entry
 ; CHECK: %body1
 ; CHECK: %body2
@@ -180,7 +180,7 @@ exit:
 define i32 @test_loop_rotate(i32 %i, i32* %a) {
 ; Check that we rotate conditional exits from the loop to the bottom of the
 ; loop, eliminating unconditional branches to the top.
-; CHECK: test_loop_rotate:
+; CHECK-LABEL: test_loop_rotate:
 ; CHECK: %entry
 ; CHECK: %body1
 ; CHECK: %body0
@@ -210,7 +210,7 @@ exit:
 define i32 @test_no_loop_rotate(i32 %i, i32* %a) {
 ; Check that we don't try to rotate a loop which is already laid out with
 ; fallthrough opportunities into the top and out of the bottom.
-; CHECK: test_no_loop_rotate:
+; CHECK-LABEL: test_no_loop_rotate:
 ; CHECK: %entry
 ; CHECK: %body0
 ; CHECK: %body1
@@ -278,7 +278,7 @@ exit:
 define i32 @test_loop_align(i32 %i, i32* %a) {
 ; Check that we provide basic loop body alignment with the block placement
 ; pass.
-; CHECK: test_loop_align:
+; CHECK-LABEL: test_loop_align:
 ; CHECK: %entry
 ; CHECK: .align [[ALIGN:[0-9]+]],
 ; CHECK-NEXT: %body
@@ -303,7 +303,7 @@ exit:
 
 define i32 @test_nested_loop_align(i32 %i, i32* %a, i32* %b) {
 ; Check that we provide nested loop body alignment.
-; CHECK: test_nested_loop_align:
+; CHECK-LABEL: test_nested_loop_align:
 ; CHECK: %entry
 ; CHECK: .align [[ALIGN]],
 ; CHECK-NEXT: %loop.body.1
@@ -1096,7 +1096,7 @@ define i32 @test_cold_calls(i32* %a) {
 ; Test that edges to blocks post-dominated by cold calls are
 ; marked as not expected to be taken.  They should be laid out
 ; at the bottom.
-; CHECK: test_cold_calls:
+; CHECK-LABEL: test_cold_calls:
 ; CHECK: %entry
 ; CHECK: %else
 ; CHECK: %exit
diff --git a/llvm/test/CodeGen/X86/brcond.ll b/llvm/test/CodeGen/X86/brcond.ll
index bc4032b..3ebe1a1 100644
--- a/llvm/test/CodeGen/X86/brcond.ll
+++ b/llvm/test/CodeGen/X86/brcond.ll
@@ -4,7 +4,7 @@
 
 define i32 @test1(i32 %a, i32 %b) nounwind ssp {
 entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: xorb
 ; CHECK-NOT: andb
 ; CHECK-NOT: shrb
@@ -44,7 +44,7 @@ bb1:                                              ; preds = %entry
 
 return:                                           ; preds = %entry
   ret i32 192
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK:	movl	4(%esp), %eax
 ; CHECK-NEXT:	orl	8(%esp), %eax
 ; CHECK-NEXT:	jne	LBB1_2
@@ -63,7 +63,7 @@ bb1:                                              ; preds = %entry
 
 return:                                           ; preds = %entry
   ret i32 192
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK:	movl	4(%esp), %eax
 ; CHECK-NEXT:	orl	8(%esp), %eax
 ; CHECK-NEXT:	je	LBB2_2
@@ -113,7 +113,7 @@ declare i32 @llvm.x86.sse41.ptestc(<4 x float> %p1, <4 x float> %p2) nounwind
 
 define <4 x float> @test5(<4 x float> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: ptest
 ; CHECK-NEXT:	jne
 ; CHECK: ret
@@ -137,7 +137,7 @@ return:
 
 define <4 x float> @test7(<4 x float> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: ptest
 ; CHECK-NEXT:	jne
 ; CHECK: ret
@@ -161,7 +161,7 @@ return:
 
 define <4 x float> @test8(<4 x float> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: ptest
 ; CHECK-NEXT:	jae
 ; CHECK: ret
@@ -185,7 +185,7 @@ return:
 
 define <4 x float> @test10(<4 x float> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: ptest
 ; CHECK-NEXT:	jae
 ; CHECK: ret
@@ -209,7 +209,7 @@ return:
 
 define <4 x float> @test11(<4 x float> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK: ptest
 ; CHECK-NEXT:	jne
 ; CHECK: ret
@@ -233,7 +233,7 @@ return:
 
 define <4 x float> @test12(<4 x float> %a, <4 x float> %b) nounwind {
 entry:
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK: ptest
 ; CHECK-NEXT:	je
 ; CHECK: ret
diff --git a/llvm/test/CodeGen/X86/btq.ll b/llvm/test/CodeGen/X86/btq.ll
index 9c137a7..add6576 100644
--- a/llvm/test/CodeGen/X86/btq.ll
+++ b/llvm/test/CodeGen/X86/btq.ll
@@ -7,7 +7,7 @@ define void @test1(i64 %foo) nounwind {
   %tobool = icmp eq i64 %and, 0
   br i1 %tobool, label %if.end, label %if.then
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: btq $32
 
 if.then:
@@ -23,7 +23,7 @@ define void @test2(i64 %foo) nounwind {
   %tobool = icmp eq i64 %and, 0
   br i1 %tobool, label %if.end, label %if.then
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: testl $-2147483648
 
 if.then:
diff --git a/llvm/test/CodeGen/X86/cmov-fp.ll b/llvm/test/CodeGen/X86/cmov-fp.ll
index ca91f9e..768af94 100644
--- a/llvm/test/CodeGen/X86/cmov-fp.ll
+++ b/llvm/test/CodeGen/X86/cmov-fp.ll
@@ -9,16 +9,16 @@ define double @test1(i32 %a, i32 %b, double %x) nounwind {
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 
-; SSE: test1:
+; SSE-LABEL: test1:
 ; SSE: movsd
 
-; NOSSE2: test1:
+; NOSSE2-LABEL: test1:
 ; NOSSE2: fcmovnbe
 
-; NOSSE1: test1:
+; NOSSE1-LABEL: test1:
 ; NOSSE1: fcmovnbe
 
-; NOCMOV: test1:
+; NOCMOV-LABEL: test1:
 ; NOCMOV: fstp
 
 }
@@ -28,16 +28,16 @@ define double @test2(i32 %a, i32 %b, double %x) nounwind {
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 
-; SSE: test2:
+; SSE-LABEL: test2:
 ; SSE: movsd
 
-; NOSSE2: test2:
+; NOSSE2-LABEL: test2:
 ; NOSSE2: fcmovnb
 
-; NOSSE1: test2:
+; NOSSE1-LABEL: test2:
 ; NOSSE1: fcmovnb
 
-; NOCMOV: test2:
+; NOCMOV-LABEL: test2:
 ; NOCMOV: fstp
 }
 
@@ -46,16 +46,16 @@ define double @test3(i32 %a, i32 %b, double %x) nounwind {
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 
-; SSE: test3:
+; SSE-LABEL: test3:
 ; SSE: movsd
 
-; NOSSE2: test3:
+; NOSSE2-LABEL: test3:
 ; NOSSE2: fcmovb
 
-; NOSSE1: test3:
+; NOSSE1-LABEL: test3:
 ; NOSSE1: fcmovb
 
-; NOCMOV: test3:
+; NOCMOV-LABEL: test3:
 ; NOCMOV: fstp
 }
 
@@ -64,16 +64,16 @@ define double @test4(i32 %a, i32 %b, double %x) nounwind {
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 
-; SSE: test4:
+; SSE-LABEL: test4:
 ; SSE: movsd
 
-; NOSSE2: test4:
+; NOSSE2-LABEL: test4:
 ; NOSSE2: fcmovbe
 
-; NOSSE1: test4:
+; NOSSE1-LABEL: test4:
 ; NOSSE1: fcmovbe
 
-; NOCMOV: test4:
+; NOCMOV-LABEL: test4:
 ; NOCMOV: fstp
 }
 
@@ -82,16 +82,16 @@ define double @test5(i32 %a, i32 %b, double %x) nounwind {
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 
-; SSE: test5:
+; SSE-LABEL: test5:
 ; SSE: movsd
 
-; NOSSE2: test5:
+; NOSSE2-LABEL: test5:
 ; NOSSE2: fstp
 
-; NOSSE1: test5:
+; NOSSE1-LABEL: test5:
 ; NOSSE1: fstp
 
-; NOCMOV: test5:
+; NOCMOV-LABEL: test5:
 ; NOCMOV: fstp
 }
 
@@ -100,16 +100,16 @@ define double @test6(i32 %a, i32 %b, double %x) nounwind {
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 
-; SSE: test6:
+; SSE-LABEL: test6:
 ; SSE: movsd
 
-; NOSSE2: test6:
+; NOSSE2-LABEL: test6:
 ; NOSSE2: fstp
 
-; NOSSE1: test6:
+; NOSSE1-LABEL: test6:
 ; NOSSE1: fstp
 
-; NOCMOV: test6:
+; NOCMOV-LABEL: test6:
 ; NOCMOV: fstp
 }
 
@@ -118,16 +118,16 @@ define double @test7(i32 %a, i32 %b, double %x) nounwind {
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 
-; SSE: test7:
+; SSE-LABEL: test7:
 ; SSE: movsd
 
-; NOSSE2: test7:
+; NOSSE2-LABEL: test7:
 ; NOSSE2: fstp
 
-; NOSSE1: test7:
+; NOSSE1-LABEL: test7:
 ; NOSSE1: fstp
 
-; NOCMOV: test7:
+; NOCMOV-LABEL: test7:
 ; NOCMOV: fstp
 }
 
@@ -136,16 +136,16 @@ define double @test8(i32 %a, i32 %b, double %x) nounwind {
   %sel = select i1 %cmp, double 99.0, double %x
   ret double %sel
 
-; SSE: test8:
+; SSE-LABEL: test8:
 ; SSE: movsd
 
-; NOSSE2: test8:
+; NOSSE2-LABEL: test8:
 ; NOSSE2: fstp
 
-; NOSSE1: test8:
+; NOSSE1-LABEL: test8:
 ; NOSSE1: fstp
 
-; NOCMOV: test8:
+; NOCMOV-LABEL: test8:
 ; NOCMOV: fstp
 }
 
@@ -154,16 +154,16 @@ define float @test9(i32 %a, i32 %b, float %x) nounwind {
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 
-; SSE: test9:
+; SSE-LABEL: test9:
 ; SSE: movss
 
-; NOSSE2: test9:
+; NOSSE2-LABEL: test9:
 ; NOSSE2: movss
 
-; NOSSE1: test9:
+; NOSSE1-LABEL: test9:
 ; NOSSE1: fcmovnbe
 
-; NOCMOV: test9:
+; NOCMOV-LABEL: test9:
 ; NOCMOV: fstp
 }
 
@@ -172,16 +172,16 @@ define float @test10(i32 %a, i32 %b, float %x) nounwind {
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 
-; SSE: test10:
+; SSE-LABEL: test10:
 ; SSE: movss
 
-; NOSSE2: test10:
+; NOSSE2-LABEL: test10:
 ; NOSSE2: movss
 
-; NOSSE1: test10:
+; NOSSE1-LABEL: test10:
 ; NOSSE1: fcmovnb
 
-; NOCMOV: test10:
+; NOCMOV-LABEL: test10:
 ; NOCMOV: fstp
 }
 
@@ -190,16 +190,16 @@ define float @test11(i32 %a, i32 %b, float %x) nounwind {
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 
-; SSE: test11:
+; SSE-LABEL: test11:
 ; SSE: movss
 
-; NOSSE2: test11:
+; NOSSE2-LABEL: test11:
 ; NOSSE2: movss
 
-; NOSSE1: test11:
+; NOSSE1-LABEL: test11:
 ; NOSSE1: fcmovb
 
-; NOCMOV: test11:
+; NOCMOV-LABEL: test11:
 ; NOCMOV: fstp
 }
 
@@ -208,16 +208,16 @@ define float @test12(i32 %a, i32 %b, float %x) nounwind {
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 
-; SSE: test12:
+; SSE-LABEL: test12:
 ; SSE: movss
 
-; NOSSE2: test12:
+; NOSSE2-LABEL: test12:
 ; NOSSE2: movss
 
-; NOSSE1: test12:
+; NOSSE1-LABEL: test12:
 ; NOSSE1: fcmovbe
 
-; NOCMOV: test12:
+; NOCMOV-LABEL: test12:
 ; NOCMOV: fstp
 }
 
@@ -226,16 +226,16 @@ define float @test13(i32 %a, i32 %b, float %x) nounwind {
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 
-; SSE: test13:
+; SSE-LABEL: test13:
 ; SSE: movss
 
-; NOSSE2: test13:
+; NOSSE2-LABEL: test13:
 ; NOSSE2: movss
 
-; NOSSE1: test13:
+; NOSSE1-LABEL: test13:
 ; NOSSE1: fstp
 
-; NOCMOV: test13:
+; NOCMOV-LABEL: test13:
 ; NOCMOV: fstp
 }
 
@@ -244,16 +244,16 @@ define float @test14(i32 %a, i32 %b, float %x) nounwind {
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 
-; SSE: test14:
+; SSE-LABEL: test14:
 ; SSE: movss
 
-; NOSSE2: test14:
+; NOSSE2-LABEL: test14:
 ; NOSSE2: movss
 
-; NOSSE1: test14:
+; NOSSE1-LABEL: test14:
 ; NOSSE1: fstp
 
-; NOCMOV: test14:
+; NOCMOV-LABEL: test14:
 ; NOCMOV: fstp
 }
 
@@ -262,16 +262,16 @@ define float @test15(i32 %a, i32 %b, float %x) nounwind {
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 
-; SSE: test15:
+; SSE-LABEL: test15:
 ; SSE: movss
 
-; NOSSE2: test15:
+; NOSSE2-LABEL: test15:
 ; NOSSE2: movss
 
-; NOSSE1: test15:
+; NOSSE1-LABEL: test15:
 ; NOSSE1: fstp
 
-; NOCMOV: test15:
+; NOCMOV-LABEL: test15:
 ; NOCMOV: fstp
 }
 
@@ -280,16 +280,16 @@ define float @test16(i32 %a, i32 %b, float %x) nounwind {
   %sel = select i1 %cmp, float 99.0, float %x
   ret float %sel
 
-; SSE: test16:
+; SSE-LABEL: test16:
 ; SSE: movss
 
-; NOSSE2: test16:
+; NOSSE2-LABEL: test16:
 ; NOSSE2: movss
 
-; NOSSE1: test16:
+; NOSSE1-LABEL: test16:
 ; NOSSE1: fstp
 
-; NOCMOV: test16:
+; NOCMOV-LABEL: test16:
 ; NOCMOV: fstp
 }
 
@@ -298,16 +298,16 @@ define x86_fp80 @test17(i32 %a, i32 %b, x86_fp80 %x) nounwind {
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 
-; SSE: test17:
+; SSE-LABEL: test17:
 ; SSE: fcmovnbe
 
-; NOSSE2: test17:
+; NOSSE2-LABEL: test17:
 ; NOSSE2: fcmovnbe
 
-; NOSSE1: test17:
+; NOSSE1-LABEL: test17:
 ; NOSSE1: fcmovnbe
 
-; NOCMOV: test17:
+; NOCMOV-LABEL: test17:
 ; NOCMOV: fstp
 }
 
@@ -316,16 +316,16 @@ define x86_fp80 @test18(i32 %a, i32 %b, x86_fp80 %x) nounwind {
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 
-; SSE: test18:
+; SSE-LABEL: test18:
 ; SSE: fcmovnb
 
-; NOSSE2: test18:
+; NOSSE2-LABEL: test18:
 ; NOSSE2: fcmovnb
 
-; NOSSE1: test18:
+; NOSSE1-LABEL: test18:
 ; NOSSE1: fcmovnb
 
-; NOCMOV: test18:
+; NOCMOV-LABEL: test18:
 ; NOCMOV: fstp
 }
 
@@ -334,16 +334,16 @@ define x86_fp80 @test19(i32 %a, i32 %b, x86_fp80 %x) nounwind {
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 
-; SSE: test19:
+; SSE-LABEL: test19:
 ; SSE: fcmovb
 
-; NOSSE2: test19:
+; NOSSE2-LABEL: test19:
 ; NOSSE2: fcmovb
 
-; NOSSE1: test19:
+; NOSSE1-LABEL: test19:
 ; NOSSE1: fcmovb
 
-; NOCMOV: test19:
+; NOCMOV-LABEL: test19:
 ; NOCMOV: fstp
 }
 
@@ -352,16 +352,16 @@ define x86_fp80 @test20(i32 %a, i32 %b, x86_fp80 %x) nounwind {
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 
-; SSE: test20:
+; SSE-LABEL: test20:
 ; SSE: fcmovbe
 
-; NOSSE2: test20:
+; NOSSE2-LABEL: test20:
 ; NOSSE2: fcmovbe
 
-; NOSSE1: test20:
+; NOSSE1-LABEL: test20:
 ; NOSSE1: fcmovbe
 
-; NOCMOV: test20:
+; NOCMOV-LABEL: test20:
 ; NOCMOV: fstp
 }
 
@@ -371,19 +371,19 @@ define x86_fp80 @test21(i32 %a, i32 %b, x86_fp80 %x) nounwind {
   ret x86_fp80 %sel
 
 ; We don't emit a branch for fp80, why?
-; SSE: test21:
+; SSE-LABEL: test21:
 ; SSE: testb
 ; SSE: fcmovne
 
-; NOSSE2: test21:
+; NOSSE2-LABEL: test21:
 ; NOSSE2: testb
 ; NOSSE2: fcmovne
 
-; NOSSE1: test21:
+; NOSSE1-LABEL: test21:
 ; NOSSE1: testb
 ; NOSSE1: fcmovne
 
-; NOCMOV: test21:
+; NOCMOV-LABEL: test21:
 ; NOCMOV: fstp
 }
 
@@ -392,19 +392,19 @@ define x86_fp80 @test22(i32 %a, i32 %b, x86_fp80 %x) nounwind {
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 
-; SSE: test22:
+; SSE-LABEL: test22:
 ; SSE: testb
 ; SSE: fcmovne
 
-; NOSSE2: test22:
+; NOSSE2-LABEL: test22:
 ; NOSSE2: testb
 ; NOSSE2: fcmovne
 
-; NOSSE1: test22:
+; NOSSE1-LABEL: test22:
 ; NOSSE1: testb
 ; NOSSE1: fcmovne
 
-; NOCMOV: test22:
+; NOCMOV-LABEL: test22:
 ; NOCMOV: fstp
 }
 
@@ -413,19 +413,19 @@ define x86_fp80 @test23(i32 %a, i32 %b, x86_fp80 %x) nounwind {
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 
-; SSE: test23:
+; SSE-LABEL: test23:
 ; SSE: testb
 ; SSE: fcmovne
 
-; NOSSE2: test23:
+; NOSSE2-LABEL: test23:
 ; NOSSE2: testb
 ; NOSSE2: fcmovne
 
-; NOSSE1: test23:
+; NOSSE1-LABEL: test23:
 ; NOSSE1: testb
 ; NOSSE1: fcmovne
 
-; NOCMOV: test23:
+; NOCMOV-LABEL: test23:
 ; NOCMOV: fstp
 }
 
@@ -434,18 +434,18 @@ define x86_fp80 @test24(i32 %a, i32 %b, x86_fp80 %x) nounwind {
   %sel = select i1 %cmp, x86_fp80 0xK4005C600000000000000, x86_fp80 %x
   ret x86_fp80 %sel
 
-; SSE: test24:
+; SSE-LABEL: test24:
 ; SSE: testb
 ; SSE: fcmovne
 
-; NOSSE2: test24:
+; NOSSE2-LABEL: test24:
 ; NOSSE2: testb
 ; NOSSE2: fcmovne
 
-; NOSSE1: test24:
+; NOSSE1-LABEL: test24:
 ; NOSSE1: testb
 ; NOSSE1: fcmovne
 
-; NOCMOV: test24:
+; NOCMOV-LABEL: test24:
 ; NOCMOV: fstp
 }
diff --git a/llvm/test/CodeGen/X86/cmov-into-branch.ll b/llvm/test/CodeGen/X86/cmov-into-branch.ll
index 780746a..cad8dd3 100644
--- a/llvm/test/CodeGen/X86/cmov-into-branch.ll
+++ b/llvm/test/CodeGen/X86/cmov-into-branch.ll
@@ -6,7 +6,7 @@ define i32 @test1(double %a, double* nocapture %b, i32 %x, i32 %y)  {
   %cmp = fcmp olt double %load, %a
   %cond = select i1 %cmp, i32 %x, i32 %y
   ret i32 %cond
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: ucomisd
 ; CHECK-NOT: cmov
 ; CHECK: j
@@ -18,7 +18,7 @@ define i32 @test2(double %a, double %b, i32 %x, i32 %y)  {
   %cmp = fcmp ogt double %a, %b
   %cond = select i1 %cmp, i32 %x, i32 %y
   ret i32 %cond
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: ucomisd
 ; CHECK: cmov
 }
@@ -29,7 +29,7 @@ define i32 @test3(i32 %a, i32* nocapture %b, i32 %x)  {
   %cmp = icmp ult i32 %load, %a
   %cond = select i1 %cmp, i32 %a, i32 %x
   ret i32 %cond
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: cmpl
 ; CHECK-NOT: cmov
 ; CHECK: j
@@ -43,7 +43,7 @@ define i32 @test4(i32 %a, i32* nocapture %b, i32 %x, i32 %y)  {
   %cond = select i1 %cmp, i32 %x, i32 %y
   %add = add i32 %cond, %load
   ret i32 %add
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: cmpl
 ; CHECK: cmov
 }
@@ -56,7 +56,7 @@ define i32 @test5(i32 %a, i32* nocapture %b, i32 %x, i32 %y) {
   %cond = select i1 %cmp1, i32 %a, i32 %y
   %cond5 = select i1 %cmp, i32 %cond, i32 %x
   ret i32 %cond5
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: cmpl
 ; CHECK: cmov
 ; CHECK: cmov
diff --git a/llvm/test/CodeGen/X86/cmov.ll b/llvm/test/CodeGen/X86/cmov.ll
index ed25c82..92c0445 100644
--- a/llvm/test/CodeGen/X86/cmov.ll
+++ b/llvm/test/CodeGen/X86/cmov.ll
@@ -3,7 +3,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 
 define i32 @test1(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
 entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: movl	$12, %eax
 ; CHECK-NEXT: btl
 ; CHECK-NEXT: cmovael	(%rcx), %eax
@@ -18,7 +18,7 @@ entry:
 }
 define i32 @test2(i32 %x, i32 %n, i32 %w, i32* %vp) nounwind readnone {
 entry:
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movl	$12, %eax
 ; CHECK-NEXT: btl
 ; CHECK-NEXT: cmovbl	(%rcx), %eax
@@ -40,7 +40,7 @@ entry:
 declare void @bar(i64) nounwind
 
 define void @test3(i64 %a, i64 %b, i1 %p) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK:      cmovnel %edi, %esi
 ; CHECK-NEXT: movl    %esi, %edi
 
@@ -87,7 +87,7 @@ bb.i.i.i:                                         ; preds = %entry
   %4 = load volatile i8* @g_100, align 1          ; <i8> [#uses=0]
   br label %func_4.exit.i
 
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: g_100
 ; CHECK: testb
 ; CHECK-NOT: xor
@@ -119,7 +119,7 @@ declare i32 @printf(i8* nocapture, ...) nounwind
 ; rdar://6668608
 define i32 @test5(i32* nocapture %P) nounwind readonly {
 entry:
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: 	setg	%al
 ; CHECK:	movzbl	%al, %eax
 ; CHECK:	orl	$-2, %eax
@@ -133,7 +133,7 @@ entry:
 
 define i32 @test6(i32* nocapture %P) nounwind readonly {
 entry:
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: 	setl	%al
 ; CHECK:	movzbl	%al, %eax
 ; CHECK:	leal	4(%rax,%rax,8), %eax
@@ -148,7 +148,7 @@ entry:
 ; Don't try to use a 16-bit conditional move to do an 8-bit select,
 ; because it isn't worth it. Just use a branch instead.
 define i8 @test7(i1 inreg %c, i8 inreg %a, i8 inreg %b) nounwind {
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK:     testb	$1, %dil
 ; CHECK-NEXT:     jne	LBB
 
diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll
index 5f5ba21..551d9bc 100644
--- a/llvm/test/CodeGen/X86/cmp.ll
+++ b/llvm/test/CodeGen/X86/cmp.ll
@@ -10,7 +10,7 @@ cond_true:		; preds = %0
 
 ReturnBlock:		; preds = %0
 	ret i32 0
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: cmpl	$0, (%rsi)
 }
 
@@ -25,7 +25,7 @@ cond_true:		; preds = %0
 
 ReturnBlock:		; preds = %0
 	ret i32 0
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movl	(%rsi), %eax
 ; CHECK: shll	$3, %eax
 ; CHECK: testl	%eax, %eax
@@ -35,7 +35,7 @@ define i64 @test3(i64 %x) nounwind {
   %t = icmp eq i64 %x, 0
   %r = zext i1 %t to i64
   ret i64 %r
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: 	testq	%rdi, %rdi
 ; CHECK: 	sete	%al
 ; CHECK: 	movzbl	%al, %eax
@@ -46,7 +46,7 @@ define i64 @test4(i64 %x) nounwind {
   %t = icmp slt i64 %x, 1
   %r = zext i1 %t to i64
   ret i64 %r
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: 	testq	%rdi, %rdi
 ; CHECK: 	setle	%al
 ; CHECK: 	movzbl	%al, %eax
@@ -67,7 +67,7 @@ define i32 @test5(double %A) nounwind  {
 
  bb12:; preds = %entry
  ret i32 32
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: ucomisd	LCPI4_0(%rip), %xmm0
 ; CHECK: ucomisd	LCPI4_1(%rip), %xmm0
 }
@@ -85,7 +85,7 @@ T:
   
 F:
   ret i32 0
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: cmpq	$0, -8(%rsp)
 ; CHECK: encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00]
 }
@@ -93,7 +93,7 @@ F:
 ; rdar://11866926
 define i32 @test7(i64 %res) nounwind {
 entry:
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK-NOT: movabsq
 ; CHECK: shrq $32, %rdi
 ; CHECK: sete
@@ -104,7 +104,7 @@ entry:
 
 define i32 @test8(i64 %res) nounwind {
 entry:
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK-NOT: movabsq
 ; CHECK: shrq $32, %rdi
 ; CHECK: cmpq $3, %rdi
@@ -115,7 +115,7 @@ entry:
 
 define i32 @test9(i64 %res) nounwind {
 entry:
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK-NOT: movabsq
 ; CHECK: shrq $33, %rdi
 ; CHECK: sete
@@ -126,7 +126,7 @@ entry:
 
 define i32 @test10(i64 %res) nounwind {
 entry:
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK-NOT: movabsq
 ; CHECK: shrq $32, %rdi
 ; CHECK: setne
@@ -138,7 +138,7 @@ entry:
 ; rdar://9758774
 define i32 @test11(i64 %l) nounwind {
 entry:
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK-NOT: movabsq
 ; CHECK-NOT: andq
 ; CHECK: shrq $47, %rdi
@@ -150,7 +150,7 @@ entry:
 }
 
 define i32 @test12() uwtable ssp {
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK: testb
   %1 = call zeroext i1 @test12b()
   br i1 %1, label %2, label %3
diff --git a/llvm/test/CodeGen/X86/conditional-indecrement.ll b/llvm/test/CodeGen/X86/conditional-indecrement.ll
index a3a0c39..c3e7118 100644
--- a/llvm/test/CodeGen/X86/conditional-indecrement.ll
+++ b/llvm/test/CodeGen/X86/conditional-indecrement.ll
@@ -5,7 +5,7 @@ define i32 @test1(i32 %a, i32 %b) nounwind readnone {
   %inc = zext i1 %not.cmp to i32
   %retval.0 = add i32 %inc, %b
   ret i32 %retval.0
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: cmpl $1
 ; CHECK: sbbl $-1
 ; CHECK: ret
@@ -16,7 +16,7 @@ define i32 @test2(i32 %a, i32 %b) nounwind readnone {
   %inc = zext i1 %cmp to i32
   %retval.0 = add i32 %inc, %b
   ret i32 %retval.0
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: cmpl $1
 ; CHECK: adcl $0
 ; CHECK: ret
@@ -27,7 +27,7 @@ define i32 @test3(i32 %a, i32 %b) nounwind readnone {
   %inc = zext i1 %cmp to i32
   %retval.0 = add i32 %inc, %b
   ret i32 %retval.0
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: cmpl $1
 ; CHECK: adcl $0
 ; CHECK: ret
@@ -38,7 +38,7 @@ define i32 @test4(i32 %a, i32 %b) nounwind readnone {
   %inc = zext i1 %not.cmp to i32
   %retval.0 = add i32 %inc, %b
   ret i32 %retval.0
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: cmpl $1
 ; CHECK: sbbl $-1
 ; CHECK: ret
@@ -49,7 +49,7 @@ define i32 @test5(i32 %a, i32 %b) nounwind readnone {
   %inc = zext i1 %not.cmp to i32
   %retval.0 = sub i32 %b, %inc
   ret i32 %retval.0
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: cmpl $1
 ; CHECK: adcl $-1
 ; CHECK: ret
@@ -60,7 +60,7 @@ define i32 @test6(i32 %a, i32 %b) nounwind readnone {
   %inc = zext i1 %cmp to i32
   %retval.0 = sub i32 %b, %inc
   ret i32 %retval.0
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: cmpl $1
 ; CHECK: sbbl $0
 ; CHECK: ret
@@ -71,7 +71,7 @@ define i32 @test7(i32 %a, i32 %b) nounwind readnone {
   %inc = zext i1 %cmp to i32
   %retval.0 = sub i32 %b, %inc
   ret i32 %retval.0
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: cmpl $1
 ; CHECK: sbbl $0
 ; CHECK: ret
@@ -82,7 +82,7 @@ define i32 @test8(i32 %a, i32 %b) nounwind readnone {
   %inc = zext i1 %not.cmp to i32
   %retval.0 = sub i32 %b, %inc
   ret i32 %retval.0
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: cmpl $1
 ; CHECK: adcl $-1
 ; CHECK: ret
diff --git a/llvm/test/CodeGen/X86/critical-edge-split-2.ll b/llvm/test/CodeGen/X86/critical-edge-split-2.ll
index 70301cd..44205d6 100644
--- a/llvm/test/CodeGen/X86/critical-edge-split-2.ll
+++ b/llvm/test/CodeGen/X86/critical-edge-split-2.ll
@@ -22,7 +22,7 @@ cond.end.i:                                       ; preds = %entry
   ret i16 %call1
 }
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: testb %dil, %dil
 ; CHECK: jne LBB0_2
 ; CHECK: divl
diff --git a/llvm/test/CodeGen/X86/ctpop-combine.ll b/llvm/test/CodeGen/X86/ctpop-combine.ll
index 0a3dfca..786f7f9 100644
--- a/llvm/test/CodeGen/X86/ctpop-combine.ll
+++ b/llvm/test/CodeGen/X86/ctpop-combine.ll
@@ -8,7 +8,7 @@ define i32 @test1(i64 %x) nounwind readnone {
   %cmp = icmp ugt i32 %cast, 1
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: leaq -1([[A0:%rdi|%rcx]])
 ; CHECK-NEXT: testq
 ; CHECK-NEXT: setne
@@ -21,7 +21,7 @@ define i32 @test2(i64 %x) nounwind readnone {
   %cmp = icmp ult i64 %count, 2
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: leaq -1([[A0]])
 ; CHECK-NEXT: testq
 ; CHECK-NEXT: sete
@@ -34,7 +34,7 @@ define i32 @test3(i64 %x) nounwind readnone {
   %cmp = icmp ult i6 %cast, 2
   %conv = zext i1 %cmp to i32
   ret i32 %conv
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: cmpb $2
 ; CHECK: ret
 }
diff --git a/llvm/test/CodeGen/X86/dag-rauw-cse.ll b/llvm/test/CodeGen/X86/dag-rauw-cse.ll
index eca8c86..12a2e62 100644
--- a/llvm/test/CodeGen/X86/dag-rauw-cse.ll
+++ b/llvm/test/CodeGen/X86/dag-rauw-cse.ll
@@ -2,7 +2,7 @@
 ; PR3018
 
 define i32 @test(i32 %A) nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: ret
 ; CHECK: orl $1
 ; CHECK: ret
diff --git a/llvm/test/CodeGen/X86/dagcombine-buildvector.ll b/llvm/test/CodeGen/X86/dagcombine-buildvector.ll
index dae91d5..cf631c3 100644
--- a/llvm/test/CodeGen/X86/dagcombine-buildvector.ll
+++ b/llvm/test/CodeGen/X86/dagcombine-buildvector.ll
@@ -3,7 +3,7 @@
 ; Shows a dag combine bug that will generate an illegal build vector
 ; with v2i64 build_vector i32, i32.
 
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: unpcklpd
 ; CHECK: movapd
 define void @test(<2 x double>* %dst, <4 x double> %src) nounwind {
@@ -13,7 +13,7 @@ entry:
         ret void
 }
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movdqa
 define void @test2(<4 x i16>* %src, <4 x i32>* %dest) nounwind {
 entry:
diff --git a/llvm/test/CodeGen/X86/dbg-value-terminator.ll b/llvm/test/CodeGen/X86/dbg-value-terminator.ll
index e7c1250..e8246ad 100644
--- a/llvm/test/CodeGen/X86/dbg-value-terminator.ll
+++ b/llvm/test/CodeGen/X86/dbg-value-terminator.ll
@@ -5,7 +5,7 @@
 ; verify-machineinstrs should ensure that DEBUG_VALUEs go before the
 ; terminator.
 ;
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: ##DEBUG_VALUE: i
 %a = type { i32, i32 }
 
diff --git a/llvm/test/CodeGen/X86/divide-by-constant.ll b/llvm/test/CodeGen/X86/divide-by-constant.ll
index 9669d97..98ae1d5 100644
--- a/llvm/test/CodeGen/X86/divide-by-constant.ll
+++ b/llvm/test/CodeGen/X86/divide-by-constant.ll
@@ -6,7 +6,7 @@ define zeroext i16 @test1(i16 zeroext %x) nounwind {
 entry:
 	%div = udiv i16 %x, 33
 	ret i16 %div
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: imull	$63551, %eax, %eax
 ; CHECK-NEXT: shrl	$21, %eax
 ; CHECK-NEXT: ret
@@ -17,7 +17,7 @@ entry:
   %div = udiv i16 %c, 3
   ret i16 %div
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: imull	$43691, %eax, %eax
 ; CHECK-NEXT: shrl	$17, %eax
 ; CHECK-NEXT: ret
@@ -28,7 +28,7 @@ entry:
   %div = udiv i8 %c, 3
   ret i8 %div
 
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: movzbl  8(%esp), %eax
 ; CHECK-NEXT: imull	$171, %eax, %eax
 ; CHECK-NEXT: shrl	$9, %eax
@@ -39,14 +39,14 @@ define signext i16 @test4(i16 signext %x) nounwind {
 entry:
 	%div = sdiv i16 %x, 33		; <i32> [#uses=1]
 	ret i16 %div
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: imull	$1986, %eax, %
 }
 
 define i32 @test5(i32 %A) nounwind {
         %tmp1 = udiv i32 %A, 1577682821         ; <i32> [#uses=1]
         ret i32 %tmp1
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: movl	$365384439, %eax
 ; CHECK: mull	4(%esp)
 }
@@ -55,7 +55,7 @@ define signext i16 @test6(i16 signext %x) nounwind {
 entry:
   %div = sdiv i16 %x, 10
   ret i16 %div
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: imull $26215, %eax, %ecx
 ; CHECK: sarl $18, %ecx
 ; CHECK: shrl $15, %eax
@@ -64,7 +64,7 @@ entry:
 define i32 @test7(i32 %x) nounwind {
   %div = udiv i32 %x, 28
   ret i32 %div
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: shrl $2
 ; CHECK: movl $613566757
 ; CHECK: mull
@@ -76,7 +76,7 @@ define i32 @test7(i32 %x) nounwind {
 define i8 @test8(i8 %x) nounwind {
   %div = udiv i8 %x, 78
   ret i8 %div
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: shrb %
 ; CHECK: imull $211
 ; CHECK: shrl $13
@@ -86,7 +86,7 @@ define i8 @test8(i8 %x) nounwind {
 define i8 @test9(i8 %x) nounwind {
   %div = udiv i8 %x, 116
   ret i8 %div
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: shrb $2
 ; CHECK: imull $71
 ; CHECK: shrl $11
diff --git a/llvm/test/CodeGen/X86/fabs.ll b/llvm/test/CodeGen/X86/fabs.ll
index af1867f..e330ee7 100644
--- a/llvm/test/CodeGen/X86/fabs.ll
+++ b/llvm/test/CodeGen/X86/fabs.ll
@@ -7,9 +7,9 @@ declare float @fabsf(float)
 
 declare x86_fp80 @fabsl(x86_fp80)
 
-; CHECK:  test1:
-; UNSAFE: test1:
-; NOOPT:  test1:
+; CHECK-LABEL:  test1:
+; UNSAFE-LABEL: test1:
+; NOOPT-LABEL:  test1:
 define float @test1(float %X) {
         %Y = call float @fabsf(float %X) readnone
         ret float %Y
@@ -21,9 +21,9 @@ define float @test1(float %X) {
 ; UNSAFE-NOT: fabs
 ; NOOPT-NOT:  fabsf
 
-; CHECK:  test2:
-; UNSAFE: test2:
-; NOOPT:  test2:
+; CHECK-LABEL:  test2:
+; UNSAFE-LABEL: test2:
+; NOOPT-LABEL:  test2:
 define double @test2(double %X) {
         %Y = fcmp oge double %X, -0.0
         %Z = fsub double -0.0, %X
@@ -38,9 +38,9 @@ define double @test2(double %X) {
 
 ; UNSAFE-NOT: fabs
 
-; CHECK:  test3:
-; UNSAFE: test3:
-; NOOPT:  test3:
+; CHECK-LABEL:  test3:
+; UNSAFE-LABEL: test3:
+; NOOPT-LABEL:  test3:
 define x86_fp80 @test3(x86_fp80 %X) {
         %Y = call x86_fp80 @fabsl(x86_fp80 %X) readnone
         ret x86_fp80 %Y
diff --git a/llvm/test/CodeGen/X86/fast-isel-call.ll b/llvm/test/CodeGen/X86/fast-isel-call.ll
index 3159741c..42d2b8b 100644
--- a/llvm/test/CodeGen/X86/fast-isel-call.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-call.ll
@@ -10,7 +10,7 @@ BB1:
 	ret i32 1
 BB2:
 	ret i32 0
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: calll
 ; CHECK-NEXT: testb	$1
 }
@@ -21,7 +21,7 @@ declare void @foo2(%struct.s* byval)
 define void @test2(%struct.s* %d) nounwind {
   call void @foo2(%struct.s* byval %d )
   ret void
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movl	(%eax)
 ; CHECK: movl {{.*}}, (%esp)
 ; CHECK: movl	4(%eax)
@@ -35,7 +35,7 @@ declare void @llvm.memset.p0i8.i32(i8* nocapture, i8, i32, i32, i1) nounwind
 define void @test3(i8* %a) {
   call void @llvm.memset.p0i8.i32(i8* %a, i8 0, i32 100, i32 1, i1 false)
   ret void
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK:   movl	{{.*}}, (%esp)
 ; CHECK:   movl	$0, 4(%esp)
 ; CHECK:   movl	$100, 8(%esp)
@@ -47,7 +47,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32,
 define void @test4(i8* %a, i8* %b) {
   call void @llvm.memcpy.p0i8.p0i8.i32(i8* %a, i8* %b, i32 100, i32 1, i1 false)
   ret void
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK:   movl	{{.*}}, (%esp)
 ; CHECK:   movl	{{.*}}, 4(%esp)
 ; CHECK:   movl	$100, 8(%esp)
diff --git a/llvm/test/CodeGen/X86/fast-isel-divrem-x86-64.ll b/llvm/test/CodeGen/X86/fast-isel-divrem-x86-64.ll
index f2afaa0..0fd0561 100644
--- a/llvm/test/CodeGen/X86/fast-isel-divrem-x86-64.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-divrem-x86-64.ll
@@ -6,7 +6,7 @@ entry:
   ret i64 %result
 }
 
-; CHECK: test_sdiv64:
+; CHECK-LABEL: test_sdiv64:
 ; CHECK: cqto
 ; CHECK: idivq
 
@@ -16,7 +16,7 @@ entry:
   ret i64 %result
 }
 
-; CHECK: test_srem64:
+; CHECK-LABEL: test_srem64:
 ; CHECK: cqto
 ; CHECK: idivq
 
@@ -26,7 +26,7 @@ entry:
   ret i64 %result
 }
 
-; CHECK: test_udiv64:
+; CHECK-LABEL: test_udiv64:
 ; CHECK: xorl
 ; CHECK: divq
 
@@ -36,6 +36,6 @@ entry:
   ret i64 %result
 }
 
-; CHECK: test_urem64:
+; CHECK-LABEL: test_urem64:
 ; CHECK: xorl
 ; CHECK: divq
diff --git a/llvm/test/CodeGen/X86/fast-isel-divrem.ll b/llvm/test/CodeGen/X86/fast-isel-divrem.ll
index 1a309a1..5828bec 100644
--- a/llvm/test/CodeGen/X86/fast-isel-divrem.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-divrem.ll
@@ -7,7 +7,7 @@ entry:
   ret i8 %result
 }
 
-; CHECK: test_sdiv8:
+; CHECK-LABEL: test_sdiv8:
 ; CHECK: movsbw
 ; CHECK: idivb
 
@@ -17,7 +17,7 @@ entry:
   ret i8 %result
 }
 
-; CHECK: test_srem8:
+; CHECK-LABEL: test_srem8:
 ; CHECK: movsbw
 ; CHECK: idivb
 
@@ -27,7 +27,7 @@ entry:
   ret i8 %result
 }
 
-; CHECK: test_udiv8:
+; CHECK-LABEL: test_udiv8:
 ; CHECK: movzbw
 ; CHECK: divb
 
@@ -37,7 +37,7 @@ entry:
   ret i8 %result
 }
 
-; CHECK: test_urem8:
+; CHECK-LABEL: test_urem8:
 ; CHECK: movzbw
 ; CHECK: divb
 
@@ -47,7 +47,7 @@ entry:
   ret i16 %result
 }
 
-; CHECK: test_sdiv16:
+; CHECK-LABEL: test_sdiv16:
 ; CHECK: cwtd
 ; CHECK: idivw
 
@@ -57,7 +57,7 @@ entry:
   ret i16 %result
 }
 
-; CHECK: test_srem16:
+; CHECK-LABEL: test_srem16:
 ; CHECK: cwtd
 ; CHECK: idivw
 
@@ -67,7 +67,7 @@ entry:
   ret i16 %result
 }
 
-; CHECK: test_udiv16:
+; CHECK-LABEL: test_udiv16:
 ; CHECK: xorl
 ; CHECK: divw
 
@@ -77,7 +77,7 @@ entry:
   ret i16 %result
 }
 
-; CHECK: test_urem16:
+; CHECK-LABEL: test_urem16:
 ; CHECK: xorl
 ; CHECK: divw
 
@@ -87,7 +87,7 @@ entry:
   ret i32 %result
 }
 
-; CHECK: test_sdiv32:
+; CHECK-LABEL: test_sdiv32:
 ; CHECK: cltd
 ; CHECK: idivl
 
@@ -97,7 +97,7 @@ entry:
   ret i32 %result
 }
 
-; CHECK: test_srem32:
+; CHECK-LABEL: test_srem32:
 ; CHECK: cltd
 ; CHECK: idivl
 
@@ -107,7 +107,7 @@ entry:
   ret i32 %result
 }
 
-; CHECK: test_udiv32:
+; CHECK-LABEL: test_udiv32:
 ; CHECK: xorl
 ; CHECK: divl
 
@@ -117,6 +117,6 @@ entry:
   ret i32 %result
 }
 
-; CHECK: test_urem32:
+; CHECK-LABEL: test_urem32:
 ; CHECK: xorl
 ; CHECK: divl
diff --git a/llvm/test/CodeGen/X86/fast-isel-extract.ll b/llvm/test/CodeGen/X86/fast-isel-extract.ll
index f63396e..3a4b2a6 100644
--- a/llvm/test/CodeGen/X86/fast-isel-extract.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-extract.ll
@@ -10,7 +10,7 @@ define void @test1(i64*) nounwind ssp {
   %4 = add i64 %3, 10
   store i64 %4, i64* %0
   ret void
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: callq _f
 ; CHECK-NEXT: addq	$10, %rax
 }
@@ -21,7 +21,7 @@ define void @test2(i64*) nounwind ssp {
   %4 = add i64 %3, 10
   store i64 %4, i64* %0
   ret void
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: callq _f
 ; CHECK-NEXT: addq	$10, %rdx
 }
diff --git a/llvm/test/CodeGen/X86/fast-isel-gep.ll b/llvm/test/CodeGen/X86/fast-isel-gep.ll
index f0375f8..4e47c74 100644
--- a/llvm/test/CodeGen/X86/fast-isel-gep.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-gep.ll
@@ -9,11 +9,11 @@ define i32 @test1(i32 %t3, i32* %t1) nounwind {
        %t9 = getelementptr i32* %t1, i32 %t3           ; <i32*> [#uses=1]
        %t15 = load i32* %t9            ; <i32> [#uses=1]
        ret i32 %t15
-; X32: test1:
+; X32-LABEL: test1:
 ; X32:  	movl	(%eax,%ecx,4), %eax
 ; X32:  	ret
 
-; X64: test1:
+; X64-LABEL: test1:
 ; X64:  	movslq	%e[[A0:di|cx]], %rax
 ; X64:  	movl	(%r[[A1:si|dx]],%rax,4), %eax
 ; X64:  	ret
@@ -23,11 +23,11 @@ define i32 @test2(i64 %t3, i32* %t1) nounwind {
        %t9 = getelementptr i32* %t1, i64 %t3           ; <i32*> [#uses=1]
        %t15 = load i32* %t9            ; <i32> [#uses=1]
        ret i32 %t15
-; X32: test2:
+; X32-LABEL: test2:
 ; X32:  	movl	(%edx,%ecx,4), %e
 ; X32:  	ret
 
-; X64: test2:
+; X64-LABEL: test2:
 ; X64:  	movl	(%r[[A1]],%r[[A0]],4), %eax
 ; X64:  	ret
 }
@@ -42,12 +42,12 @@ entry:
   ret i8 %B
   
   
-; X32: test3:
+; X32-LABEL: test3:
 ; X32:  	movl	4(%esp), %eax
 ; X32:  	movb	-2(%eax), %al
 ; X32:  	ret
 
-; X64: test3:
+; X64-LABEL: test3:
 ; X64:  	movb	-2(%r[[A0]]), %al
 ; X64:  	ret
 
@@ -66,9 +66,9 @@ entry:
   %tmp2 = load double* %arrayidx                  ; <double> [#uses=1]
   ret double %tmp2
 
-; X32: test4:
+; X32-LABEL: test4:
 ; X32: 128(%e{{.*}},%e{{.*}},8)
-; X64: test4:
+; X64-LABEL: test4:
 ; X64: 128(%r{{.*}},%r{{.*}},8)
 }
 
@@ -80,7 +80,7 @@ define i64 @test5(i8* %A, i32 %I, i64 %B) nounwind {
   %v10 = load i64* %v9
   %v11 = add i64 %B, %v10
   ret i64 %v11
-; X64: test5:
+; X64-LABEL: test5:
 ; X64: movslq	%e[[A1]], %rax
 ; X64-NEXT: (%r[[A0]],%rax),
 ; X64: ret
@@ -113,7 +113,7 @@ declare i8* @_ZNK18G__FastAllocString4dataEv() nounwind
 ; PR10605 / rdar://9930964 - Don't fold loads incorrectly.  The load should
 ; happen before the store.  
 define i32 @test7({i32,i32,i32}* %tmp1, i32 %tmp71, i32 %tmp63) nounwind  {
-; X64: test7:
+; X64-LABEL: test7:
 ; X64:    movl	8({{%rdi|%rcx}}), %eax
 ; X64:     movl	$4, 8({{%rdi|%rcx}})
 
diff --git a/llvm/test/CodeGen/X86/fast-isel-i1.ll b/llvm/test/CodeGen/X86/fast-isel-i1.ll
index bea18a1..9c042d3 100644
--- a/llvm/test/CodeGen/X86/fast-isel-i1.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-i1.ll
@@ -4,7 +4,7 @@
 declare i32 @test1a(i32)
 
 define i32 @test1(i32 %x) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: andb $1, %
 	%y = add i32 %x, -3
 	%t = call i32 @test1a(i32 %y)
@@ -23,7 +23,7 @@ exit:		; preds = %next
 
 define void @test2(i8* %a) nounwind {
 entry:
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movb {{.*}} %al
 ; CHECK-NEXT: xorb $1, %al
 ; CHECK-NEXT: testb $1
diff --git a/llvm/test/CodeGen/X86/fast-isel-x86-64.ll b/llvm/test/CodeGen/X86/fast-isel-x86-64.ll
index ad1520e..f7d2750 100644
--- a/llvm/test/CodeGen/X86/fast-isel-x86-64.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-x86-64.ll
@@ -11,7 +11,7 @@ define i32 @test1(i32 %i) nounwind ssp {
   ret i32 %and
 }
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: andl	$8, 
 
 
@@ -29,7 +29,7 @@ if.then:                                          ; preds = %entry
 
 if.end:                                           ; preds = %if.then, %entry
   ret void
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movq	%rdi, -8(%rsp)
 ; CHECK: cmpq	$42, -8(%rsp)
 }
@@ -41,7 +41,7 @@ if.end:                                           ; preds = %if.then, %entry
 define i64 @test3() nounwind {
   %A = ptrtoint i32* @G to i64
   ret i64 %A
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: movq _G@GOTPCREL(%rip), %rax
 ; CHECK-NEXT: ret
 }
@@ -57,7 +57,7 @@ define i32 @test4(i64 %idxprom9) nounwind {
   %conv = zext i8 %tmp11 to i32
   ret i32 %conv
 
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: movq	_rtx_length@GOTPCREL(%rip), %rax
 ; CHECK-NEXT: movzbl	(%rax,%rdi), %eax
 ; CHECK-NEXT: ret
@@ -70,7 +70,7 @@ define void @test5(i32 %x, i32* %p) nounwind {
   store i32 %y, i32* %p
   ret void
 
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: movl	$50000, %ecx
 ; CHECK: sarl	%cl, %edi
 ; CHECK: ret
@@ -82,7 +82,7 @@ entry:
   %mul = mul nsw i64 %x, 8
   ret i64 %mul
 
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: shlq	$3, %rdi
 }
 
@@ -90,7 +90,7 @@ define i32 @test7(i32 %x) nounwind ssp {
 entry:
   %mul = mul nsw i32 %x, 8
   ret i32 %mul
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: shll	$3, %edi
 }
 
@@ -101,7 +101,7 @@ entry:
   %add = add nsw i64 %x, 7
   ret i64 %add
 
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: addq	$7, %rdi
 }
 
@@ -109,7 +109,7 @@ define i64 @test9(i64 %x) nounwind ssp {
 entry:
   %add = mul nsw i64 %x, 7
   ret i64 %add
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: imulq	$7, %rdi, %rax
 }
 
@@ -117,14 +117,14 @@ entry:
 define i32 @test10(i32 %X) nounwind {
   %Y = udiv i32 %X, 8
   ret i32 %Y
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: shrl	$3, 
 }
 
 define i32 @test11(i32 %X) nounwind {
   %Y = sdiv exact i32 %X, 8
   ret i32 %Y
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK: sarl	$3, 
 }
 
@@ -141,7 +141,7 @@ if.then:                                          ; preds = %entry
 
 if.end:                                           ; preds = %if.then, %entry
   ret void
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK: testb	$1,
 ; CHECK-NEXT: je L
 ; CHECK-NEXT: movl $0, %edi
@@ -153,7 +153,7 @@ declare void @test13f(i1 %X)
 define void @test13() nounwind {
   call void @test13f(i1 0)
   ret void
-; CHECK: test13:
+; CHECK-LABEL: test13:
 ; CHECK: movl $0, %edi
 ; CHECK-NEXT: callq
 }
@@ -166,7 +166,7 @@ entry:
   %tobool = trunc i8 %tmp to i1
   call void @test13f(i1 zeroext %tobool) noredzone
   ret void
-; CHECK: test14:
+; CHECK-LABEL: test14:
 ; CHECK: andb	$1, 
 ; CHECK: callq
 }
@@ -177,7 +177,7 @@ declare void @llvm.memcpy.p0i8.p0i8.i64(i8*, i8*, i64, i32, i1)
 define void @test15(i8* %a, i8* %b) nounwind {
   call void @llvm.memcpy.p0i8.p0i8.i64(i8* %a, i8* %b, i64 4, i32 4, i1 false)
   ret void
-; CHECK: test15:
+; CHECK-LABEL: test15:
 ; CHECK-NEXT: movl	(%rsi), %eax
 ; CHECK-NEXT: movl	%eax, (%rdi)
 ; CHECK-NEXT: ret
@@ -186,7 +186,7 @@ define void @test15(i8* %a, i8* %b) nounwind {
 ; Handling for varargs calls
 declare void @test16callee(...) nounwind
 define void @test16() nounwind {
-; CHECK: test16:
+; CHECK-LABEL: test16:
 ; CHECK: movl $1, %edi
 ; CHECK: movb $0, %al
 ; CHECK: callq _test16callee
@@ -224,7 +224,7 @@ if.then:                                          ; preds = %entry
 
 if.else:                                          ; preds = %entry
   ret i32 2
-; CHECK: test17:
+; CHECK-LABEL: test17:
 ; CHECK: movl	(%rdi), %eax
 ; CHECK: callq _foo
 ; CHECK: cmpl	$5, %eax
@@ -235,7 +235,7 @@ if.else:                                          ; preds = %entry
 define void @test18(float* %p1) {
   store float 0.0, float* %p1
   ret void
-; CHECK: test18:
+; CHECK-LABEL: test18:
 ; CHECK: xorps
 }
 
@@ -243,7 +243,7 @@ define void @test18(float* %p1) {
 define void @test19(double* %p1) {
   store double 0.0, double* %p1
   ret void
-; CHECK: test19:
+; CHECK-LABEL: test19:
 ; CHECK: xorps
 }
 
@@ -254,7 +254,7 @@ entry:
   %tmp = alloca %struct.a, align 8
   call void @test20sret(%struct.a* sret %tmp)
   ret void
-; CHECK: test20:
+; CHECK-LABEL: test20:
 ; CHECK: leaq (%rsp), %rdi
 ; CHECK: callq _test20sret
 }
@@ -264,7 +264,7 @@ declare void @test20sret(%struct.a* sret)
 define void @test21(double* %p1) {
   store double -0.0, double* %p1
   ret void
-; CHECK: test21:
+; CHECK-LABEL: test21:
 ; CHECK-NOT: xor
 ; CHECK: movsd	LCPI
 }
@@ -279,7 +279,7 @@ entry:
   call void @foo22(i32 2)
   call void @foo22(i32 3)
   ret void
-; CHECK: test22:
+; CHECK-LABEL: test22:
 ; CHECK: movl	$0, %edi
 ; CHECK: callq	_foo22
 ; CHECK: movl	$1, %edi
@@ -297,7 +297,7 @@ define void @test23(i8* noalias sret %result) {
   %a = alloca i8
   %b = call i8* @foo23()
   ret void
-; CHECK: test23:
+; CHECK-LABEL: test23:
 ; CHECK: call
 ; CHECK: movq  %rdi, %rax
 ; CHECK: ret
diff --git a/llvm/test/CodeGen/X86/fast-isel-x86.ll b/llvm/test/CodeGen/X86/fast-isel-x86.ll
index 4caa3a0..ba86e88 100644
--- a/llvm/test/CodeGen/X86/fast-isel-x86.ll
+++ b/llvm/test/CodeGen/X86/fast-isel-x86.ll
@@ -1,7 +1,7 @@
 ; RUN: llc -fast-isel -O0 -mcpu=generic -mtriple=i386-apple-darwin10 -relocation-model=pic < %s | FileCheck %s
 
 ; This should use flds to set the return value.
-; CHECK: test0:
+; CHECK-LABEL: test0:
 ; CHECK: flds
 ; CHECK: ret
 @G = external global float
@@ -11,7 +11,7 @@ define float @test0() nounwind {
 }
 
 ; This should pop 4 bytes on return.
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: ret $4
 define void @test1({i32, i32, i32, i32}* sret %p) nounwind {
   store {i32, i32, i32, i32} zeroinitializer, {i32, i32, i32, i32}* %p
@@ -19,7 +19,7 @@ define void @test1({i32, i32, i32, i32}* sret %p) nounwind {
 }
 
 ; Properly initialize the pic base.
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK-NOT: HHH
 ; CHECK: call{{.*}}L2$pb
 ; CHECK-NEXT: L2$pb:
@@ -39,7 +39,7 @@ entry:
   %tmp = alloca %struct.a, align 8
   call void @test3sret(%struct.a* sret %tmp)
   ret void
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: subl $44
 ; CHECK: leal 16(%esp)
 ; CHECK: calll _test3sret
@@ -53,7 +53,7 @@ entry:
   %tmp = alloca %struct.a, align 8
   call fastcc void @test4fastccsret(%struct.a* sret %tmp)
   ret void
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: subl $28
 ; CHECK: leal (%esp), %ecx
 ; CHECK: calll _test4fastccsret
diff --git a/llvm/test/CodeGen/X86/fold-load.ll b/llvm/test/CodeGen/X86/fold-load.ll
index d836665..495acd9 100644
--- a/llvm/test/CodeGen/X86/fold-load.ll
+++ b/llvm/test/CodeGen/X86/fold-load.ll
@@ -39,7 +39,7 @@ L:
   store i16 %A, i16* %Q
   ret i32 %D
   
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: 	movl	4(%esp), %eax
 ; CHECK-NEXT:	movzwl	(%eax), %ecx
 
@@ -48,7 +48,7 @@ L:
 ; rdar://10554090
 ; xor in exit block will be CSE'ed and load will be folded to xor in entry.
 define i1 @test3(i32* %P, i32* %Q) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: movl 8(%esp), %eax
 ; CHECK: xorl (%eax),
 ; CHECK: j
diff --git a/llvm/test/CodeGen/X86/iabs.ll b/llvm/test/CodeGen/X86/iabs.ll
index 9196cce..f47bd7b 100644
--- a/llvm/test/CodeGen/X86/iabs.ll
+++ b/llvm/test/CodeGen/X86/iabs.ll
@@ -7,7 +7,7 @@
 ;;       ret
 ; rdar://10695237
 define i32 @test(i32 %a) nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: mov
 ; CHECK-NEXT: neg
 ; CHECK-NEXT: cmov
diff --git a/llvm/test/CodeGen/X86/isel-sink.ll b/llvm/test/CodeGen/X86/isel-sink.ll
index d275533..458f19d 100644
--- a/llvm/test/CodeGen/X86/isel-sink.ll
+++ b/llvm/test/CodeGen/X86/isel-sink.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86 | FileCheck %s
 
 define i32 @test(i32* %X, i32 %B) {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: ret
 ; CHECK-NOT: lea
 ; CHECK: mov{{.}} $4, ({{.*}},{{.*}},4)
diff --git a/llvm/test/CodeGen/X86/jump_sign.ll b/llvm/test/CodeGen/X86/jump_sign.ll
index 0e34222..91ac942 100644
--- a/llvm/test/CodeGen/X86/jump_sign.ll
+++ b/llvm/test/CodeGen/X86/jump_sign.ll
@@ -283,7 +283,7 @@ entry:
 @a = common global i32 0, align 4
 define i32 @test1(i32 %p1) nounwind uwtable {
 entry:
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: testb
 ; CHECK: j
 ; CHECK: ret
diff --git a/llvm/test/CodeGen/X86/lea.ll b/llvm/test/CodeGen/X86/lea.ll
index 87f0b0b..affd6bf 100644
--- a/llvm/test/CodeGen/X86/lea.ll
+++ b/llvm/test/CodeGen/X86/lea.ll
@@ -5,7 +5,7 @@ define i32 @test1(i32 %x) nounwind {
         %tmp1 = shl i32 %x, 3
         %tmp2 = add i32 %tmp1, 7
         ret i32 %tmp2
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK:    leal 7(,%r[[A0:di|cx]],8), %eax
 }
 
@@ -27,7 +27,7 @@ bb.nph:
 
 bb2:
 	ret i32 %x_offs
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movl %e[[A0]], %eax
 ; CHECK: addl $-5, %eax
 ; CHECK:	andl	$-4, %eax
diff --git a/llvm/test/CodeGen/X86/legalize-shift-64.ll b/llvm/test/CodeGen/X86/legalize-shift-64.ll
index 0e6fb13..748cbcb 100644
--- a/llvm/test/CodeGen/X86/legalize-shift-64.ll
+++ b/llvm/test/CodeGen/X86/legalize-shift-64.ll
@@ -6,7 +6,7 @@ define i64 @test1(i32 %xx, i32 %test) nounwind {
   %sh_prom = zext i32 %and to i64
   %shl = shl i64 %conv, %sh_prom
   ret i64 %shl
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: shll	%cl, %eax
 ; CHECK: shrl	%edx
 ; CHECK: xorb	$31
@@ -18,7 +18,7 @@ define i64 @test2(i64 %xx, i32 %test) nounwind {
   %sh_prom = zext i32 %and to i64
   %shl = shl i64 %xx, %sh_prom
   ret i64 %shl
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: shll	%cl, %esi
 ; CHECK: shrl	%edx
 ; CHECK: xorb	$31
@@ -32,7 +32,7 @@ define i64 @test3(i64 %xx, i32 %test) nounwind {
   %sh_prom = zext i32 %and to i64
   %shr = lshr i64 %xx, %sh_prom
   ret i64 %shr
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: shrl	%cl, %esi
 ; CHECK: leal	(%edx,%edx), %eax
 ; CHECK: xorb	$31, %cl
@@ -46,7 +46,7 @@ define i64 @test4(i64 %xx, i32 %test) nounwind {
   %sh_prom = zext i32 %and to i64
   %shr = ashr i64 %xx, %sh_prom
   ret i64 %shr
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: shrl	%cl, %esi
 ; CHECK: leal	(%edx,%edx), %eax
 ; CHECK: xorb	$31, %cl
diff --git a/llvm/test/CodeGen/X86/longlong-deadload.ll b/llvm/test/CodeGen/X86/longlong-deadload.ll
index db91961e0..73e1012 100644
--- a/llvm/test/CodeGen/X86/longlong-deadload.ll
+++ b/llvm/test/CodeGen/X86/longlong-deadload.ll
@@ -2,7 +2,7 @@
 ; This should not load or store the top part of *P.
 
 define void @test(i64* %P) nounwind  {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: movl 4(%esp), %[[REGISTER:.*]]
 ; CHECK-NOT: 4(%[[REGISTER]])
 ; CHECK: ret
diff --git a/llvm/test/CodeGen/X86/lsr-reuse.ll b/llvm/test/CodeGen/X86/lsr-reuse.ll
index 1311a73..a267450 100644
--- a/llvm/test/CodeGen/X86/lsr-reuse.ll
+++ b/llvm/test/CodeGen/X86/lsr-reuse.ll
@@ -447,7 +447,7 @@ bb5:                                              ; preds = %bb3, %entry
 ; we don't want to leave extra induction variables around, or use an
 ; lea to compute an exit condition inside the loop:
 
-; CHECK: test:
+; CHECK-LABEL: test:
 
 ; CHECK:      BB10_4:
 ; CHECK-NEXT:   movaps  %xmm{{.*}}, %xmm{{.*}}
diff --git a/llvm/test/CodeGen/X86/memcpy.ll b/llvm/test/CodeGen/X86/memcpy.ll
index 3372a4a..88b6cfd 100644
--- a/llvm/test/CodeGen/X86/memcpy.ll
+++ b/llvm/test/CodeGen/X86/memcpy.ll
@@ -10,7 +10,7 @@ entry:
 	tail call void @llvm.memcpy.p0i8.p0i8.i64( i8* %a, i8* %b, i64 %n, i32 1, i1 0 )
 	ret i8* %a
         
-; LINUX: test1:
+; LINUX-LABEL: test1:
 ; LINUX: memcpy
 }
 
@@ -22,7 +22,7 @@ entry:
 	tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %tmp14, i8* %tmp25, i64 %n, i32 8, i1 0 )
 	ret i8* %tmp14
         
-; LINUX: test2:
+; LINUX-LABEL: test2:
 ; LINUX: memcpy
 }
 
@@ -36,10 +36,10 @@ define void @test3(i8* nocapture %A, i8* nocapture %B) nounwind optsize noredzon
 entry:
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %A, i8* %B, i64 64, i32 1, i1 false)
   ret void
-; LINUX: test3:
+; LINUX-LABEL: test3:
 ; LINUX: memcpy
 
-; DARWIN: test3:
+; DARWIN-LABEL: test3:
 ; DARWIN-NOT: memcpy
 ; DARWIN: movq
 ; DARWIN: movq
@@ -64,7 +64,7 @@ define void @test4(i8* nocapture %A, i8* nocapture %B) nounwind noredzone {
 entry:
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %A, i8* %B, i64 64, i32 1, i1 false)
   ret void
-; LINUX: test4:
+; LINUX-LABEL: test4:
 ; LINUX: movq
 ; LINUX: movq
 ; LINUX: movq
@@ -87,7 +87,7 @@ entry:
   tail call void @llvm.memcpy.p0i8.p0i8.i64(i8* %C, i8* getelementptr inbounds ([30 x i8]* @.str, i64 0, i64 0), i64 16, i32 1, i1 false)
   ret void
 
-; DARWIN: test5:
+; DARWIN-LABEL: test5:
 ; DARWIN: movabsq	$7016996765293437281
 ; DARWIN: movabsq	$7016996765293437184
 }
diff --git a/llvm/test/CodeGen/X86/memset-sse-stack-realignment.ll b/llvm/test/CodeGen/X86/memset-sse-stack-realignment.ll
index df9de5d..d77a7ed 100644
--- a/llvm/test/CodeGen/X86/memset-sse-stack-realignment.ll
+++ b/llvm/test/CodeGen/X86/memset-sse-stack-realignment.ll
@@ -14,26 +14,26 @@ define void @test1(i32 %t) nounwind {
   call void @dummy(i8* %x)
   ret void
 
-; NOSSE: test1:
+; NOSSE-LABEL: test1:
 ; NOSSE-NOT: and
 ; NOSSE: movl $0
 
-; SSE1: test1:
+; SSE1-LABEL: test1:
 ; SSE1: andl $-16
 ; SSE1: movl %esp, %esi
 ; SSE1: movaps
 
-; SSE2: test1:
+; SSE2-LABEL: test1:
 ; SSE2: andl $-16
 ; SSE2: movl %esp, %esi
 ; SSE2: movaps
 
-; AVX1: test1:
+; AVX1-LABEL: test1:
 ; AVX1: andl $-32
 ; AVX1: movl %esp, %esi
 ; AVX1: vmovaps %ymm
 
-; AVX2: test1:
+; AVX2-LABEL: test1:
 ; AVX2: andl $-32
 ; AVX2: movl %esp, %esi
 ; AVX2: vmovaps %ymm
@@ -47,26 +47,26 @@ define void @test2(i32 %t) nounwind {
   call void @dummy(i8* %x)
   ret void
 
-; NOSSE: test2:
+; NOSSE-LABEL: test2:
 ; NOSSE-NOT: and
 ; NOSSE: movl $0
 
-; SSE1: test2:
+; SSE1-LABEL: test2:
 ; SSE1: andl $-16
 ; SSE1: movl %esp, %esi
 ; SSE1: movaps
 
-; SSE2: test2:
+; SSE2-LABEL: test2:
 ; SSE2: andl $-16
 ; SSE2: movl %esp, %esi
 ; SSE2: movaps
 
-; AVX1: test2:
+; AVX1-LABEL: test2:
 ; AVX1: andl $-16
 ; AVX1: movl %esp, %esi
 ; AVX1: vmovaps %xmm
 
-; AVX2: test2:
+; AVX2-LABEL: test2:
 ; AVX2: andl $-16
 ; AVX2: movl %esp, %esi
 ; AVX2: vmovaps %xmm
diff --git a/llvm/test/CodeGen/X86/movbe.ll b/llvm/test/CodeGen/X86/movbe.ll
index 3d3d8cf..aa58c10 100644
--- a/llvm/test/CodeGen/X86/movbe.ll
+++ b/llvm/test/CodeGen/X86/movbe.ll
@@ -7,7 +7,7 @@ define void @test1(i32* nocapture %x, i32 %y) nounwind {
   %bswap = call i32 @llvm.bswap.i32(i32 %y)
   store i32 %bswap, i32* %x, align 4
   ret void
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: movbel	%esi, (%rdi)
 }
 
@@ -15,7 +15,7 @@ define i32 @test2(i32* %x) nounwind {
   %load = load i32* %x, align 4
   %bswap = call i32 @llvm.bswap.i32(i32 %load)
   ret i32 %bswap
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movbel	(%rdi), %eax
 }
 
@@ -23,7 +23,7 @@ define void @test3(i64* %x, i64 %y) nounwind {
   %bswap = call i64 @llvm.bswap.i64(i64 %y)
   store i64 %bswap, i64* %x, align 8
   ret void
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: movbeq	%rsi, (%rdi)
 }
 
@@ -31,6 +31,6 @@ define i64 @test4(i64* %x) nounwind {
   %load = load i64* %x, align 8
   %bswap = call i64 @llvm.bswap.i64(i64 %load)
   ret i64 %bswap
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: movbeq	(%rdi), %rax
 }
diff --git a/llvm/test/CodeGen/X86/movgs.ll b/llvm/test/CodeGen/X86/movgs.ll
index bb42734..e5afb27 100644
--- a/llvm/test/CodeGen/X86/movgs.ll
+++ b/llvm/test/CodeGen/X86/movgs.ll
@@ -8,12 +8,12 @@ entry:
 	%tmp1 = load i32* %tmp		; <i32> [#uses=1]
 	ret i32 %tmp1
 }
-; X32: test1:
+; X32-LABEL: test1:
 ; X32: 	movl	%gs:196, %eax
 ; X32: 	movl	(%eax), %eax
 ; X32: 	ret
 
-; X64: test1:
+; X64-LABEL: test1:
 ; X64: 	movq	%gs:320, %rax
 ; X64: 	movl	(%rax), %eax
 ; X64: 	ret
@@ -26,11 +26,11 @@ entry:
 }
 
 ; rdar://8453210
-; X32: test2:
+; X32-LABEL: test2:
 ; X32: movl	{{.*}}(%esp), %eax
 ; X32: calll	*%gs:(%eax)
 
-; X64: test2:
+; X64-LABEL: test2:
 ; X64: callq	*%gs:([[A0:%rdi|%rcx]])
 
 
@@ -66,7 +66,7 @@ entry:
 	%tmp4 = add i32 %tmp1, %tmp3
 	ret i32 %tmp4
 }
-; X32: test_no_cse:
+; X32-LABEL: test_no_cse:
 ; X32: 	movl	%gs:196
 ; X32: 	movl	%fs:196
 ; X32: 	ret
diff --git a/llvm/test/CodeGen/X86/narrow-shl-cst.ll b/llvm/test/CodeGen/X86/narrow-shl-cst.ll
index a404f34..40b9760 100644
--- a/llvm/test/CodeGen/X86/narrow-shl-cst.ll
+++ b/llvm/test/CodeGen/X86/narrow-shl-cst.ll
@@ -5,7 +5,7 @@ define i32 @test1(i32 %x) nounwind {
   %and = shl i32 %x, 10
   %shl = and i32 %and, 31744
   ret i32 %shl
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: andl $31
 ; CHECK: shll $10
 }
@@ -14,7 +14,7 @@ define i32 @test2(i32 %x) nounwind {
   %or = shl i32 %x, 10
   %shl = or i32 %or, 31744
   ret i32 %shl
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: orl $31
 ; CHECK: shll $10
 }
@@ -23,7 +23,7 @@ define i32 @test3(i32 %x) nounwind {
   %xor = shl i32 %x, 10
   %shl = xor i32 %xor, 31744
   ret i32 %shl
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: xorl $31
 ; CHECK: shll $10
 }
@@ -32,7 +32,7 @@ define i64 @test4(i64 %x) nounwind {
   %and = shl i64 %x, 40
   %shl = and i64 %and, 264982302294016
   ret i64 %shl
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: andq $241
 ; CHECK: shlq $40
 }
@@ -41,7 +41,7 @@ define i64 @test5(i64 %x) nounwind {
   %and = shl i64 %x, 40
   %shl = and i64 %and, 34084860461056
   ret i64 %shl
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: andq $31
 ; CHECK: shlq $40
 }
@@ -50,7 +50,7 @@ define i64 @test6(i64 %x) nounwind {
   %and = shl i64 %x, 32
   %shl = and i64 %and, -281474976710656
   ret i64 %shl
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: andq $-65536
 ; CHECK: shlq $32
 }
@@ -59,7 +59,7 @@ define i64 @test7(i64 %x) nounwind {
   %or = shl i64 %x, 40
   %shl = or i64 %or, 264982302294016
   ret i64 %shl
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: orq $241
 ; CHECK: shlq $40
 }
@@ -68,7 +68,7 @@ define i64 @test8(i64 %x) nounwind {
   %or = shl i64 %x, 40
   %shl = or i64 %or, 34084860461056
   ret i64 %shl
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: orq $31
 ; CHECK: shlq $40
 }
@@ -77,7 +77,7 @@ define i64 @test9(i64 %x) nounwind {
   %xor = shl i64 %x, 40
   %shl = xor i64 %xor, 264982302294016
   ret i64 %shl
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: orq $241
 ; CHECK: shlq $40
 }
@@ -86,7 +86,7 @@ define i64 @test10(i64 %x) nounwind {
   %xor = shl i64 %x, 40
   %shl = xor i64 %xor, 34084860461056
   ret i64 %shl
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: xorq $31
 ; CHECK: shlq $40
 }
@@ -95,7 +95,7 @@ define i64 @test11(i64 %x) nounwind {
   %xor = shl i64 %x, 33
   %shl = xor i64 %xor, -562949953421312
   ret i64 %shl
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK: xorq $-65536
 ; CHECK: shlq $33
 }
diff --git a/llvm/test/CodeGen/X86/narrow-shl-load.ll b/llvm/test/CodeGen/X86/narrow-shl-load.ll
index 7822453..30387925 100644
--- a/llvm/test/CodeGen/X86/narrow-shl-load.ll
+++ b/llvm/test/CodeGen/X86/narrow-shl-load.ll
@@ -33,7 +33,7 @@ while.end:                                        ; preds = %while.cond
 
 ; DAGCombiner shouldn't fold the sdiv (ashr) away.
 ; rdar://8636812
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK:   sarl
 
 define i32 @test2() nounwind {
diff --git a/llvm/test/CodeGen/X86/no-cmov.ll b/llvm/test/CodeGen/X86/no-cmov.ll
index 62d73b0..e13edf2 100644
--- a/llvm/test/CodeGen/X86/no-cmov.ll
+++ b/llvm/test/CodeGen/X86/no-cmov.ll
@@ -6,6 +6,6 @@ define i32 @test1(i32 %g, i32* %j) {
   %retval.0 = select i1 %tobool, i32 1, i32 %cmp
   ret i32 %retval.0
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NOT: cmov
 }
diff --git a/llvm/test/CodeGen/X86/or-address.ll b/llvm/test/CodeGen/X86/or-address.ll
index f866e41..6bea864 100644
--- a/llvm/test/CodeGen/X86/or-address.ll
+++ b/llvm/test/CodeGen/X86/or-address.ll
@@ -46,7 +46,7 @@ return:                                           ; preds = %bb
   ret void
 }
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: 	movl	%{{.*}},   (%[[RDI:...]],%[[RCX:...]],4)
 ; CHECK:	movl	%{{.*}},  8(%[[RDI]],%[[RCX]],4)
 ; CHECK:	movl	%{{.*}},  4(%[[RDI]],%[[RCX]],4)
diff --git a/llvm/test/CodeGen/X86/palignr.ll b/llvm/test/CodeGen/X86/palignr.ll
index 6875fb3..c76cbbe 100644
--- a/llvm/test/CodeGen/X86/palignr.ll
+++ b/llvm/test/CodeGen/X86/palignr.ll
@@ -2,7 +2,7 @@
 ; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck --check-prefix=YONAH %s
 
 define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: pshufd
 ; CHECK-YONAH: pshufd
   %C = shufflevector <4 x i32> %A, <4 x i32> undef, <4 x i32> < i32 1, i32 2, i32 3, i32 0 >
@@ -10,7 +10,7 @@ define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
 }
 
 define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: palignr
 ; CHECK-YONAH: shufps
   %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 3, i32 4 >
@@ -18,42 +18,42 @@ define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
 }
 
 define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: palignr
   %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 1, i32 2, i32 undef, i32 4 >
 	ret <4 x i32> %C
 }
 
 define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: palignr
   %C = shufflevector <4 x i32> %A, <4 x i32> %B, <4 x i32> < i32 6, i32 7, i32 undef, i32 1 >
 	ret <4 x i32> %C
 }
 
 define <4 x float> @test5(<4 x float> %A, <4 x float> %B) nounwind {
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: palignr
   %C = shufflevector <4 x float> %A, <4 x float> %B, <4 x i32> < i32 6, i32 7, i32 undef, i32 1 >
 	ret <4 x float> %C
 }
 
 define <8 x i16> @test6(<8 x i16> %A, <8 x i16> %B) nounwind {
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: palignr
   %C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 3, i32 4, i32 undef, i32 6, i32 7, i32 8, i32 9, i32 10 >
 	ret <8 x i16> %C
 }
 
 define <8 x i16> @test7(<8 x i16> %A, <8 x i16> %B) nounwind {
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: palignr
   %C = shufflevector <8 x i16> %A, <8 x i16> %B, <8 x i32> < i32 undef, i32 6, i32 undef, i32 8, i32 9, i32 10, i32 11, i32 12 >
 	ret <8 x i16> %C
 }
 
 define <16 x i8> @test8(<16 x i8> %A, <16 x i8> %B) nounwind {
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: palignr
   %C = shufflevector <16 x i8> %A, <16 x i8> %B, <16 x i32> < i32 5, i32 6, i32 7, i32 undef, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15, i32 16, i32 17, i32 18, i32 19, i32 20 >
 	ret <16 x i8> %C
@@ -64,7 +64,7 @@ define <16 x i8> @test8(<16 x i8> %A, <16 x i8> %B) nounwind {
 ; incorrectly.  In particular, one of the operands of the palignr node
 ; was an UNDEF.)
 define <8 x i16> @test9(<8 x i16> %A, <8 x i16> %B) nounwind {
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK-NOT: palignr
 ; CHECK: pshufb
   %C = shufflevector <8 x i16> %B, <8 x i16> %A, <8 x i32> < i32 undef, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 0 >
diff --git a/llvm/test/CodeGen/X86/peep-setb.ll b/llvm/test/CodeGen/X86/peep-setb.ll
index 0bab789..adae8ac 100644
--- a/llvm/test/CodeGen/X86/peep-setb.ll
+++ b/llvm/test/CodeGen/X86/peep-setb.ll
@@ -5,7 +5,7 @@ define i8 @test1(i8 %a, i8 %b) nounwind {
   %cond = zext i1 %cmp to i8
   %add = add i8 %cond, %b
   ret i8 %add
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: adcb $0
 }
 
@@ -14,7 +14,7 @@ define i32 @test2(i32 %a, i32 %b) nounwind {
   %cond = zext i1 %cmp to i32
   %add = add i32 %cond, %b
   ret i32 %add
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: adcl $0
 }
 
@@ -23,7 +23,7 @@ define i64 @test3(i64 %a, i64 %b) nounwind {
   %conv = zext i1 %cmp to i64
   %add = add i64 %conv, %b
   ret i64 %add
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: adcq $0
 }
 
@@ -32,7 +32,7 @@ define i8 @test4(i8 %a, i8 %b) nounwind {
   %cond = zext i1 %cmp to i8
   %sub = sub i8 %b, %cond
   ret i8 %sub
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: sbbb $0
 }
 
@@ -41,7 +41,7 @@ define i32 @test5(i32 %a, i32 %b) nounwind {
   %cond = zext i1 %cmp to i32
   %sub = sub i32 %b, %cond
   ret i32 %sub
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: sbbl $0
 }
 
@@ -50,7 +50,7 @@ define i64 @test6(i64 %a, i64 %b) nounwind {
   %conv = zext i1 %cmp to i64
   %sub = sub i64 %b, %conv
   ret i64 %sub
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: sbbq $0
 }
 
@@ -59,7 +59,7 @@ define i8 @test7(i8 %a, i8 %b) nounwind {
   %cond = sext i1 %cmp to i8
   %sub = sub i8 %b, %cond
   ret i8 %sub
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: adcb $0
 }
 
@@ -68,7 +68,7 @@ define i32 @test8(i32 %a, i32 %b) nounwind {
   %cond = sext i1 %cmp to i32
   %sub = sub i32 %b, %cond
   ret i32 %sub
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: adcl $0
 }
 
@@ -77,6 +77,6 @@ define i64 @test9(i64 %a, i64 %b) nounwind {
   %conv = sext i1 %cmp to i64
   %sub = sub i64 %b, %conv
   ret i64 %sub
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: adcq $0
 }
diff --git a/llvm/test/CodeGen/X86/peep-test-3.ll b/llvm/test/CodeGen/X86/peep-test-3.ll
index a379980..a7c456a 100644
--- a/llvm/test/CodeGen/X86/peep-test-3.ll
+++ b/llvm/test/CodeGen/X86/peep-test-3.ll
@@ -67,7 +67,7 @@ return:                                           ; preds = %entry
 
 ; Just like @and, but without the trunc+store. This should use a testb
 ; instead of an andl.
-; CHECK: test:
+; CHECK-LABEL: test:
 define void @test(float* %A, i32 %IA, i32 %N, i8* %p) nounwind {
 entry:
   store i8 0, i8* %p
diff --git a/llvm/test/CodeGen/X86/pic.ll b/llvm/test/CodeGen/X86/pic.ll
index fc06309..7bb127e 100644
--- a/llvm/test/CodeGen/X86/pic.ll
+++ b/llvm/test/CodeGen/X86/pic.ll
@@ -11,7 +11,7 @@ entry:
     store i32 %tmp.s, i32* @dst
     ret void
     
-; LINUX:    test0:
+; LINUX-LABEL:    test0:
 ; LINUX:	calll	.L0$pb
 ; LINUX-NEXT: .L0$pb:
 ; LINUX-NEXT:	popl
@@ -33,7 +33,7 @@ entry:
     store i32 %tmp.s, i32* @dst2
     ret void
     
-; LINUX: test1:
+; LINUX-LABEL: test1:
 ; LINUX:	calll	.L1$pb
 ; LINUX-NEXT: .L1$pb:
 ; LINUX-NEXT:	popl
@@ -51,7 +51,7 @@ define void @test2() nounwind {
 entry:
     %ptr = call i8* @malloc(i32 40)
     ret void
-; LINUX: test2:
+; LINUX-LABEL: test2:
 ; LINUX: 	pushl	%ebx
 ; LINUX-NEXT: 	subl	$8, %esp
 ; LINUX-NEXT: 	calll	.L2$pb
@@ -74,7 +74,7 @@ entry:
     %tmp1 = load void(...)** @pfoo
     call void(...)* %tmp1()
     ret void
-; LINUX: test3:
+; LINUX-LABEL: test3:
 ; LINUX: 	calll	.L3$pb
 ; LINUX-NEXT: .L3$pb:
 ; LINUX: 	popl
@@ -90,7 +90,7 @@ define void @test4() nounwind {
 entry:
     call void(...)* @foo()
     ret void
-; LINUX: test4:
+; LINUX-LABEL: test4:
 ; LINUX: calll	.L4$pb
 ; LINUX: popl	%ebx
 ; LINUX: addl	$_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L4$pb), %ebx
@@ -111,7 +111,7 @@ entry:
     store i32 %tmp.s, i32* @dst6
     ret void
     
-; LINUX: test5:
+; LINUX-LABEL: test5:
 ; LINUX: 	calll	.L5$pb
 ; LINUX-NEXT: .L5$pb:
 ; LINUX-NEXT: 	popl	%eax
@@ -133,7 +133,7 @@ entry:
 
 ; LINUX: .LCPI6_0:
 
-; LINUX: test6:
+; LINUX-LABEL: test6:
 ; LINUX:    calll .L6$pb
 ; LINUX: .L6$pb:
 ; LINUX:    addl	$_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L6$pb), 
@@ -185,7 +185,7 @@ bb12:
     tail call void(...)* @foo6()
     ret void
     
-; LINUX: test7:
+; LINUX-LABEL: test7:
 ; LINUX:   calll	.L7$pb
 ; LINUX: .L7$pb:
 ; LINUX:   addl	$_GLOBAL_OFFSET_TABLE_+(.L{{.*}}-.L7$pb),
diff --git a/llvm/test/CodeGen/X86/pmovsx-inreg.ll b/llvm/test/CodeGen/X86/pmovsx-inreg.ll
index d8c27f2..d30d7d0 100644
--- a/llvm/test/CodeGen/X86/pmovsx-inreg.ll
+++ b/llvm/test/CodeGen/X86/pmovsx-inreg.ll
@@ -12,13 +12,13 @@ define void @test1(<2 x i8>* %in, <2 x i64>* %out) nounwind {
   store <2 x i64> %sext, <2 x i64>* %out, align 8
   ret void
 
-; SSE41: test1:
+; SSE41-LABEL: test1:
 ; SSE41: pmovsxbq
 
-; AVX1: test1:
+; AVX1-LABEL: test1:
 ; AVX1: vpmovsxbq
 
-; AVX2: test1:
+; AVX2-LABEL: test1:
 ; AVX2: vpmovsxbq
 }
 
@@ -29,7 +29,7 @@ define void @test2(<4 x i8>* %in, <4 x i64>* %out) nounwind {
   store <4 x i64> %sext, <4 x i64>* %out, align 8
   ret void
 
-; AVX2: test2:
+; AVX2-LABEL: test2:
 ; AVX2: vpmovsxbq
 }
 
@@ -40,13 +40,13 @@ define void @test3(<4 x i8>* %in, <4 x i32>* %out) nounwind {
   store <4 x i32> %sext, <4 x i32>* %out, align 8
   ret void
 
-; SSE41: test3:
+; SSE41-LABEL: test3:
 ; SSE41: pmovsxbd
 
-; AVX1: test3:
+; AVX1-LABEL: test3:
 ; AVX1: vpmovsxbd
 
-; AVX2: test3:
+; AVX2-LABEL: test3:
 ; AVX2: vpmovsxbd
 }
 
@@ -57,7 +57,7 @@ define void @test4(<8 x i8>* %in, <8 x i32>* %out) nounwind {
   store <8 x i32> %sext, <8 x i32>* %out, align 8
   ret void
 
-; AVX2: test4:
+; AVX2-LABEL: test4:
 ; AVX2: vpmovsxbd
 }
 
@@ -68,13 +68,13 @@ define void @test5(<8 x i8>* %in, <8 x i16>* %out) nounwind {
   store <8 x i16> %sext, <8 x i16>* %out, align 8
   ret void
 
-; SSE41: test5:
+; SSE41-LABEL: test5:
 ; SSE41: pmovsxbw
 
-; AVX1: test5:
+; AVX1-LABEL: test5:
 ; AVX1: vpmovsxbw
 
-; AVX2: test5:
+; AVX2-LABEL: test5:
 ; AVX2: vpmovsxbw
 }
 
@@ -85,7 +85,7 @@ define void @test6(<16 x i8>* %in, <16 x i16>* %out) nounwind {
   store <16 x i16> %sext, <16 x i16>* %out, align 8
   ret void
 
-; AVX2: test6:
+; AVX2-LABEL: test6:
 ; FIXME: v16i8 -> v16i16 is scalarized.
 ; AVX2-NOT: pmovsx
 }
@@ -98,13 +98,13 @@ define void @test7(<2 x i16>* %in, <2 x i64>* %out) nounwind {
   ret void
 
 
-; SSE41: test7:
+; SSE41-LABEL: test7:
 ; SSE41: pmovsxwq
 
-; AVX1: test7:
+; AVX1-LABEL: test7:
 ; AVX1: vpmovsxwq
 
-; AVX2: test7:
+; AVX2-LABEL: test7:
 ; AVX2: vpmovsxwq
 }
 
@@ -115,7 +115,7 @@ define void @test8(<4 x i16>* %in, <4 x i64>* %out) nounwind {
   store <4 x i64> %sext, <4 x i64>* %out, align 8
   ret void
 
-; AVX2: test8:
+; AVX2-LABEL: test8:
 ; AVX2: vpmovsxwq
 }
 
@@ -126,13 +126,13 @@ define void @test9(<4 x i16>* %in, <4 x i32>* %out) nounwind {
   store <4 x i32> %sext, <4 x i32>* %out, align 8
   ret void
 
-; SSE41: test9:
+; SSE41-LABEL: test9:
 ; SSE41: pmovsxwd
 
-; AVX1: test9:
+; AVX1-LABEL: test9:
 ; AVX1: vpmovsxwd
 
-; AVX2: test9:
+; AVX2-LABEL: test9:
 ; AVX2: vpmovsxwd
 }
 
@@ -143,7 +143,7 @@ define void @test10(<8 x i16>* %in, <8 x i32>* %out) nounwind {
   store <8 x i32> %sext, <8 x i32>* %out, align 8
   ret void
 
-; AVX2: test10:
+; AVX2-LABEL: test10:
 ; AVX2: vpmovsxwd
 }
 
@@ -154,13 +154,13 @@ define void @test11(<2 x i32>* %in, <2 x i64>* %out) nounwind {
   store <2 x i64> %sext, <2 x i64>* %out, align 8
   ret void
 
-; SSE41: test11:
+; SSE41-LABEL: test11:
 ; SSE41: pmovsxdq
 
-; AVX1: test11:
+; AVX1-LABEL: test11:
 ; AVX1: vpmovsxdq
 
-; AVX2: test11:
+; AVX2-LABEL: test11:
 ; AVX2: vpmovsxdq
 }
 
@@ -171,6 +171,6 @@ define void @test12(<4 x i32>* %in, <4 x i64>* %out) nounwind {
   store <4 x i64> %sext, <4 x i64>* %out, align 8
   ret void
 
-; AVX2: test12:
+; AVX2-LABEL: test12:
 ; AVX2: vpmovsxdq
 }
diff --git a/llvm/test/CodeGen/X86/pmulld.ll b/llvm/test/CodeGen/X86/pmulld.ll
index be527ae..4103eab 100644
--- a/llvm/test/CodeGen/X86/pmulld.ll
+++ b/llvm/test/CodeGen/X86/pmulld.ll
@@ -2,10 +2,10 @@
 ; RUN: llc < %s -mtriple=x86_64-win32 -mattr=+sse41 -asm-verbose=0 | FileCheck %s -check-prefix=WIN64
 
 define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NEXT: pmulld
 
-; WIN64: test1:
+; WIN64-LABEL: test1:
 ; WIN64-NEXT: movdqa  (%rcx), %xmm0
 ; WIN64-NEXT: pmulld  (%rdx), %xmm0
   %C = mul <4 x i32> %A, %B
@@ -13,10 +13,10 @@ define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
 }
 
 define <4 x i32> @test1a(<4 x i32> %A, <4 x i32> *%Bp) nounwind {
-; CHECK: test1a:
+; CHECK-LABEL: test1a:
 ; CHECK-NEXT: pmulld
 
-; WIN64: test1a:
+; WIN64-LABEL: test1a:
 ; WIN64-NEXT: movdqa  (%rcx), %xmm0
 ; WIN64-NEXT: pmulld  (%rdx), %xmm0
 
diff --git a/llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll b/llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll
index 0bf601b..5089bd7 100644
--- a/llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll
+++ b/llvm/test/CodeGen/X86/rd-mod-wr-eflags.ll
@@ -179,7 +179,7 @@ return:
 
 define void @test3() nounwind ssp {
 entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: decq 16(%rax)
   %0 = load i64** @foo, align 8
   %arrayidx = getelementptr inbounds i64* %0, i64 2
diff --git a/llvm/test/CodeGen/X86/reverse_branches.ll b/llvm/test/CodeGen/X86/reverse_branches.ll
index 9772125..ee6333e6 100644
--- a/llvm/test/CodeGen/X86/reverse_branches.ll
+++ b/llvm/test/CodeGen/X86/reverse_branches.ll
@@ -7,7 +7,7 @@
 ; Make sure at end of do.cond.i, we jump to do.body.i first to have a tighter
 ; inner loop.
 define i32 @test_branches_order() uwtable ssp {
-; CHECK: test_branches_order:
+; CHECK-LABEL: test_branches_order:
 ; CHECK: [[L0:LBB0_[0-9]+]]: ## %do.body.i
 ; CHECK: je
 ; CHECK: %do.cond.i
diff --git a/llvm/test/CodeGen/X86/sdiv-exact.ll b/llvm/test/CodeGen/X86/sdiv-exact.ll
index 48bb883..4f8d3f0 100644
--- a/llvm/test/CodeGen/X86/sdiv-exact.ll
+++ b/llvm/test/CodeGen/X86/sdiv-exact.ll
@@ -3,7 +3,7 @@
 define i32 @test1(i32 %x) {
   %div = sdiv exact i32 %x, 25
   ret i32 %div
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: imull	$-1030792151, 4(%esp)
 ; CHECK-NEXT: ret
 }
@@ -11,7 +11,7 @@ define i32 @test1(i32 %x) {
 define i32 @test2(i32 %x) {
   %div = sdiv exact i32 %x, 24
   ret i32 %div
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: sarl	$3
 ; CHECK-NEXT: imull	$-1431655765
 ; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll b/llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll
index d68b00b..c2aa617 100644
--- a/llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll
+++ b/llvm/test/CodeGen/X86/segmented-stacks-dynamic.ll
@@ -20,7 +20,7 @@ false:
         %retvalue = call i32 @test_basic(i32 %newlen)
         ret i32 %retvalue
 
-; X32:      test_basic:
+; X32-LABEL:      test_basic:
 
 ; X32:      cmpl %gs:48, %esp
 ; X32-NEXT: ja      .LBB0_2
@@ -41,7 +41,7 @@ false:
 ; X32-NEXT: calll __morestack_allocate_stack_space
 ; X32-NEXT: addl $16, %esp
 
-; X64:      test_basic:
+; X64-LABEL:      test_basic:
 
 ; X64:      cmpq %fs:112, %rsp
 ; X64-NEXT: ja      .LBB0_2
diff --git a/llvm/test/CodeGen/X86/select.ll b/llvm/test/CodeGen/X86/select.ll
index 09ca07b..55da769 100644
--- a/llvm/test/CodeGen/X86/select.ll
+++ b/llvm/test/CodeGen/X86/select.ll
@@ -10,11 +10,11 @@ define i32 @test1(%0* %p, %0* %q, i1 %r) nounwind {
   %t4 = select i1 %r, %0 %t0, %0 %t1
   %t5 = extractvalue %0 %t4, 1
   ret i32 %t5
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: cmovneq %rdi, %rsi
 ; CHECK: movl (%rsi), %eax
 
-; ATOM: test1:
+; ATOM-LABEL: test1:
 ; ATOM: cmovneq %rdi, %rsi
 ; ATOM: movl (%rsi), %eax
 }
@@ -33,11 +33,11 @@ bb90:		; preds = %bb84, %bb72
 	unreachable
 bb91:		; preds = %bb84
 	ret i32 0
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movnew
 ; CHECK: movswl
 
-; ATOM: test2:
+; ATOM-LABEL: test2:
 ; ATOM: movnew
 ; ATOM: movswl
 }
@@ -51,10 +51,10 @@ entry:
 	%0 = icmp eq i32 %x, 0		; <i1> [#uses=1]
 	%iftmp.0.0 = select i1 %0, float 4.200000e+01, float 2.300000e+01		; <float> [#uses=1]
 	ret float %iftmp.0.0
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: movss	{{.*}},4), %xmm0
 
-; ATOM: test3:
+; ATOM-LABEL: test3:
 ; ATOM: movss  {{.*}},4), %xmm0
 }
 
@@ -65,10 +65,10 @@ entry:
 	%1 = getelementptr i8* %P, i32 %iftmp.0.0		; <i8*> [#uses=1]
 	%2 = load i8* %1, align 1		; <i8> [#uses=1]
 	ret i8 %2
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: movsbl	({{.*}},4), %eax
 
-; ATOM: test4:
+; ATOM-LABEL: test4:
 ; ATOM: movsbl ({{.*}},4), %eax
 }
 
@@ -76,9 +76,9 @@ define void @test5(i1 %c, <2 x i16> %a, <2 x i16> %b, <2 x i16>* %p) nounwind {
   %x = select i1 %c, <2 x i16> %a, <2 x i16> %b
   store <2 x i16> %x, <2 x i16>* %p
   ret void
-; CHECK: test5:
+; CHECK-LABEL: test5:
 
-; ATOM: test5:
+; ATOM-LABEL: test5:
 }
 
 define void @test6(i32 %C, <4 x float>* %A, <4 x float>* %B) nounwind {
@@ -91,13 +91,13 @@ define void @test6(i32 %C, <4 x float>* %A, <4 x float>* %B) nounwind {
         ret void
 ; Verify that the fmul gets sunk into the one part of the diamond where it is
 ; needed.
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: je
 ; CHECK: ret
 ; CHECK: mulps
 ; CHECK: ret
 
-; ATOM: test6:
+; ATOM-LABEL: test6:
 ; ATOM: je
 ; ATOM: ret
 ; ATOM: mulps
@@ -109,11 +109,11 @@ define x86_fp80 @test7(i32 %tmp8) nounwind {
         %tmp9 = icmp sgt i32 %tmp8, -1          ; <i1> [#uses=1]
         %retval = select i1 %tmp9, x86_fp80 0xK4005B400000000000000, x86_fp80 0xK40078700000000000000
         ret x86_fp80 %retval
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: leaq
 ; CHECK: fldt (%r{{.}}x,%r{{.}}x)
 
-; ATOM: test7:
+; ATOM-LABEL: test7:
 ; ATOM: leaq
 ; ATOM: fldt (%r{{.}}x,%r{{.}}x)
 }
@@ -125,9 +125,9 @@ define void @test8(i1 %c, <6 x i32>* %dst.addr, <6 x i32> %src1,<6 x i32> %src2)
 	store <6 x i32> %val, <6 x i32>* %dst.addr
 	ret void
 
-; CHECK: test8:
+; CHECK-LABEL: test8:
 
-; ATOM: test8:
+; ATOM-LABEL: test8:
 }
 
 
@@ -137,13 +137,13 @@ define i64 @test9(i64 %x, i64 %y) nounwind readnone ssp noredzone {
   %cmp = icmp ne i64 %x, 0
   %cond = select i1 %cmp, i64 %y, i64 -1
   ret i64 %cond
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: cmpq	$1, %rdi
 ; CHECK: sbbq	%rax, %rax
 ; CHECK: orq	%rsi, %rax
 ; CHECK: ret
 
-; ATOM: test9:
+; ATOM-LABEL: test9:
 ; ATOM: cmpq   $1, %rdi
 ; ATOM: sbbq   %rax, %rax
 ; ATOM: orq    %rsi, %rax
@@ -155,13 +155,13 @@ define i64 @test9a(i64 %x, i64 %y) nounwind readnone ssp noredzone {
   %cmp = icmp eq i64 %x, 0
   %cond = select i1 %cmp, i64 -1, i64 %y
   ret i64 %cond
-; CHECK: test9a:
+; CHECK-LABEL: test9a:
 ; CHECK: cmpq	$1, %rdi
 ; CHECK: sbbq	%rax, %rax
 ; CHECK: orq	%rsi, %rax
 ; CHECK: ret
 
-; ATOM: test9a:
+; ATOM-LABEL: test9a:
 ; ATOM: cmpq   $1, %rdi
 ; ATOM: sbbq   %rax, %rax
 ; ATOM: orq    %rsi, %rax
@@ -173,13 +173,13 @@ define i64 @test9b(i64 %x, i64 %y) nounwind readnone ssp noredzone {
   %A = sext i1 %cmp to i64
   %cond = or i64 %y, %A
   ret i64 %cond
-; CHECK: test9b:
+; CHECK-LABEL: test9b:
 ; CHECK: cmpq	$1, %rdi
 ; CHECK: sbbq	%rax, %rax
 ; CHECK: orq	%rsi, %rax
 ; CHECK: ret
 
-; ATOM: test9b:
+; ATOM-LABEL: test9b:
 ; ATOM: cmpq   $1, %rdi
 ; ATOM: sbbq   %rax, %rax
 ; ATOM: orq    %rsi, %rax
@@ -191,13 +191,13 @@ define i64 @test10(i64 %x, i64 %y) nounwind readnone ssp noredzone {
   %cmp = icmp eq i64 %x, 0
   %cond = select i1 %cmp, i64 -1, i64 1
   ret i64 %cond
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: cmpq	$1, %rdi
 ; CHECK: sbbq	%rax, %rax
 ; CHECK: orq	$1, %rax
 ; CHECK: ret
 
-; ATOM: test10:
+; ATOM-LABEL: test10:
 ; ATOM: cmpq   $1, %rdi
 ; ATOM: sbbq   %rax, %rax
 ; ATOM: orq    $1, %rax
@@ -210,14 +210,14 @@ define i64 @test11(i64 %x, i64 %y) nounwind readnone ssp noredzone {
   %cmp = icmp eq i64 %x, 0
   %cond = select i1 %cmp, i64 %y, i64 -1
   ret i64 %cond
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK: cmpq	$1, %rdi
 ; CHECK: sbbq	%rax, %rax
 ; CHECK: notq %rax
 ; CHECK: orq	%rsi, %rax
 ; CHECK: ret
 
-; ATOM: test11:
+; ATOM-LABEL: test11:
 ; ATOM: cmpq   $1, %rdi
 ; ATOM: sbbq   %rax, %rax
 ; ATOM: notq %rax
@@ -229,14 +229,14 @@ define i64 @test11a(i64 %x, i64 %y) nounwind readnone ssp noredzone {
   %cmp = icmp ne i64 %x, 0
   %cond = select i1 %cmp, i64 -1, i64 %y
   ret i64 %cond
-; CHECK: test11a:
+; CHECK-LABEL: test11a:
 ; CHECK: cmpq	$1, %rdi
 ; CHECK: sbbq	%rax, %rax
 ; CHECK: notq %rax
 ; CHECK: orq	%rsi, %rax
 ; CHECK: ret
 
-; ATOM: test11a:
+; ATOM-LABEL: test11a:
 ; ATOM: cmpq   $1, %rdi
 ; ATOM: sbbq   %rax, %rax
 ; ATOM: notq %rax
@@ -255,13 +255,13 @@ entry:
   %D = select i1 %B, i64 -1, i64 %C
   %call = tail call noalias i8* @_Znam(i64 %D) nounwind noredzone
   ret i8* %call
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK: movq $-1, %rdi
 ; CHECK: mulq
 ; CHECK: cmovnoq	%rax, %rdi
 ; CHECK: jmp	__Znam
 
-; ATOM: test12:
+; ATOM-LABEL: test12:
 ; ATOM: mulq
 ; ATOM: movq $-1, %rdi
 ; ATOM: cmovnoq        %rax, %rdi
@@ -274,12 +274,12 @@ define i32 @test13(i32 %a, i32 %b) nounwind {
   %c = icmp ult i32 %a, %b
   %d = sext i1 %c to i32
   ret i32 %d
-; CHECK: test13:
+; CHECK-LABEL: test13:
 ; CHECK: cmpl
 ; CHECK-NEXT: sbbl
 ; CHECK-NEXT: ret
 
-; ATOM: test13:
+; ATOM-LABEL: test13:
 ; ATOM: cmpl
 ; ATOM-NEXT: sbbl
 ; ATOM: ret
@@ -289,13 +289,13 @@ define i32 @test14(i32 %a, i32 %b) nounwind {
   %c = icmp uge i32 %a, %b
   %d = sext i1 %c to i32
   ret i32 %d
-; CHECK: test14:
+; CHECK-LABEL: test14:
 ; CHECK: cmpl
 ; CHECK-NEXT: sbbl
 ; CHECK-NEXT: notl
 ; CHECK-NEXT: ret
 
-; ATOM: test14:
+; ATOM-LABEL: test14:
 ; ATOM: cmpl
 ; ATOM-NEXT: sbbl
 ; ATOM-NEXT: notl
@@ -308,11 +308,11 @@ entry:
   %cmp = icmp ne i32 %x, 0
   %sub = sext i1 %cmp to i32
   ret i32 %sub
-; CHECK: test15:
+; CHECK-LABEL: test15:
 ; CHECK: negl
 ; CHECK: sbbl
 
-; ATOM: test15:
+; ATOM-LABEL: test15:
 ; ATOM: negl
 ; ATOM: sbbl
 }
@@ -322,11 +322,11 @@ entry:
   %cmp = icmp ne i64 %x, 0
   %conv1 = sext i1 %cmp to i64
   ret i64 %conv1
-; CHECK: test16:
+; CHECK-LABEL: test16:
 ; CHECK: negq
 ; CHECK: sbbq
 
-; ATOM: test16:
+; ATOM-LABEL: test16:
 ; ATOM: negq
 ; ATOM: sbbq
 }
@@ -336,11 +336,11 @@ entry:
   %cmp = icmp ne i16 %x, 0
   %sub = sext i1 %cmp to i16
   ret i16 %sub
-; CHECK: test17:
+; CHECK-LABEL: test17:
 ; CHECK: negw
 ; CHECK: sbbw
 
-; ATOM: test17:
+; ATOM-LABEL: test17:
 ; ATOM: negw
 ; ATOM: sbbw
 }
@@ -349,11 +349,11 @@ define i8 @test18(i32 %x, i8 zeroext %a, i8 zeroext %b) nounwind {
   %cmp = icmp slt i32 %x, 15
   %sel = select i1 %cmp, i8 %a, i8 %b
   ret i8 %sel
-; CHECK: test18:
+; CHECK-LABEL: test18:
 ; CHECK: cmpl $15, %edi
 ; CHECK: cmovgel %edx
 
-; ATOM: test18:
+; ATOM-LABEL: test18:
 ; ATOM: cmpl $15, %edi
 ; ATOM: cmovgel %edx
 }
diff --git a/llvm/test/CodeGen/X86/select_const.ll b/llvm/test/CodeGen/X86/select_const.ll
index 5b2409d..a6c2377 100644
--- a/llvm/test/CodeGen/X86/select_const.ll
+++ b/llvm/test/CodeGen/X86/select_const.ll
@@ -7,7 +7,7 @@ entry:
   %retval.0 = select i1 %cmp, i64 2, i64 %add
   ret i64 %retval.0
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: leaq 1(%rdi), %rax
 ; CHECK: cmpq $2, %rdi
 ; CHECK: cmoveq %rdi, %rax
diff --git a/llvm/test/CodeGen/X86/sext-load.ll b/llvm/test/CodeGen/X86/sext-load.ll
index 58c9322..2753e87 100644
--- a/llvm/test/CodeGen/X86/sext-load.ll
+++ b/llvm/test/CodeGen/X86/sext-load.ll
@@ -3,7 +3,7 @@
 ; When doing sign extension, use the sext-load lowering to take advantage of
 ; x86's sign extension during loads.
 ;
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK:      movsbl {{.*}}, %eax
 ; CHECK-NEXT: ret
 define i32 @test1(i32 %X) nounwind  {
@@ -16,7 +16,7 @@ entry:
 ; When using a sextload representation, ensure that the sign extension is
 ; preserved even when removing shifted-out low bits.
 ;
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK:      movswl {{.*}}, %eax
 ; CHECK-NEXT: ret
 define i32 @test2({i16, [6 x i8]}* %this) {
diff --git a/llvm/test/CodeGen/X86/shift-combine.ll b/llvm/test/CodeGen/X86/shift-combine.ll
index 51f8303..113dedb 100644
--- a/llvm/test/CodeGen/X86/shift-combine.ll
+++ b/llvm/test/CodeGen/X86/shift-combine.ll
@@ -3,7 +3,7 @@
 @array = weak global [4 x i32] zeroinitializer
 
 define i32 @test_lshr_and(i32 %x) {
-; CHECK: test_lshr_and:
+; CHECK-LABEL: test_lshr_and:
 ; CHECK-NOT: shrl
 ; CHECK: andl $12,
 ; CHECK: movl {{.*}}array{{.*}},
diff --git a/llvm/test/CodeGen/X86/shift-folding.ll b/llvm/test/CodeGen/X86/shift-folding.ll
index c518cdd..ea9002c 100644
--- a/llvm/test/CodeGen/X86/shift-folding.ll
+++ b/llvm/test/CodeGen/X86/shift-folding.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=x86 -verify-coalescing | FileCheck %s
 
 define i32* @test1(i32* %P, i32 %X) {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NOT: shrl
 ; CHECK-NOT: shll
 ; CHECK: ret
@@ -14,7 +14,7 @@ entry:
 }
 
 define i32* @test2(i32* %P, i32 %X) {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: shll $4
 ; CHECK-NOT: shll
 ; CHECK: ret
@@ -27,7 +27,7 @@ entry:
 }
 
 define i32* @test3(i32* %P, i32 %X) {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK-NOT: shrl
 ; CHECK-NOT: shll
 ; CHECK: ret
@@ -39,7 +39,7 @@ entry:
 }
 
 define fastcc i32 @test4(i32* %d) {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK-NOT: shrl
 ; CHECK: ret
 
@@ -52,7 +52,7 @@ entry:
 define i64 @test5(i16 %i, i32* %arr) {
 ; Ensure that we don't fold away shifts which have multiple uses, as they are
 ; just re-introduced for the second use.
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK-NOT: shrl
 ; CHECK: shrl $11
 ; CHECK-NOT: shrl
diff --git a/llvm/test/CodeGen/X86/shrink-compare.ll b/llvm/test/CodeGen/X86/shrink-compare.ll
index 30a5b62..bb89201 100644
--- a/llvm/test/CodeGen/X86/shrink-compare.ll
+++ b/llvm/test/CodeGen/X86/shrink-compare.ll
@@ -15,7 +15,7 @@ if.then:
 
 if.end:
   ret void
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: cmpb $47, (%{{rdi|rcx}})
 }
 
@@ -31,7 +31,7 @@ if.then:
 
 if.end:
   ret void
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: cmpb $47, %{{dil|cl}}
 }
 
@@ -47,7 +47,7 @@ if.then:
 
 if.end:
   ret void
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: cmpb $-1, %{{dil|cl}}
 }
 
@@ -85,7 +85,7 @@ if.then:
 if.end:
   ret void
 
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK-NOT: cmpl $1,{{.*}}x+4
 ; CHECK: ret
 }
diff --git a/llvm/test/CodeGen/X86/sibcall-6.ll b/llvm/test/CodeGen/X86/sibcall-6.ll
index 2cdc3c4..c9dff6b 100644
--- a/llvm/test/CodeGen/X86/sibcall-6.ll
+++ b/llvm/test/CodeGen/X86/sibcall-6.ll
@@ -6,7 +6,7 @@ target triple = "i386-unknown-linux-gnu"
 
 declare void @callee1(i32 inreg, i32 inreg, i32 inreg)
 define void @test1(i32 %a, i32 %b) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: calll callee1@PLT
   tail call void @callee1(i32 inreg 0, i32 inreg 0, i32 inreg 0) nounwind
   ret void
diff --git a/llvm/test/CodeGen/X86/sincos-opt.ll b/llvm/test/CodeGen/X86/sincos-opt.ll
index f800c58..2dc8816 100644
--- a/llvm/test/CodeGen/X86/sincos-opt.ll
+++ b/llvm/test/CodeGen/X86/sincos-opt.ll
@@ -8,12 +8,12 @@
 
 define float @test1(float %x) nounwind {
 entry:
-; GNU_SINCOS: test1:
+; GNU_SINCOS-LABEL: test1:
 ; GNU_SINCOS: callq sincosf
 ; GNU_SINCOS: movss 4(%rsp), %xmm0
 ; GNU_SINCOS: addss (%rsp), %xmm0
 
-; OSX_SINCOS: test1:
+; OSX_SINCOS-LABEL: test1:
 ; OSX_SINCOS: callq ___sincosf_stret
 ; OSX_SINCOS: pshufd $1, %xmm0, %xmm1
 ; OSX_SINCOS: addss %xmm0, %xmm1
@@ -29,12 +29,12 @@ entry:
 
 define double @test2(double %x) nounwind {
 entry:
-; GNU_SINCOS: test2:
+; GNU_SINCOS-LABEL: test2:
 ; GNU_SINCOS: callq sincos
 ; GNU_SINCOS: movsd 16(%rsp), %xmm0
 ; GNU_SINCOS: addsd 8(%rsp), %xmm0
 
-; OSX_SINCOS: test2:
+; OSX_SINCOS-LABEL: test2:
 ; OSX_SINCOS: callq ___sincos_stret
 ; OSX_SINCOS: addsd %xmm1, %xmm0
 
@@ -49,7 +49,7 @@ entry:
 
 define x86_fp80 @test3(x86_fp80 %x) nounwind {
 entry:
-; GNU_SINCOS: test3:
+; GNU_SINCOS-LABEL: test3:
 ; GNU_SINCOS: callq sinl
 ; GNU_SINCOS: callq cosl
 ; GNU_SINCOS: ret
diff --git a/llvm/test/CodeGen/X86/sincos.ll b/llvm/test/CodeGen/X86/sincos.ll
index 734f48a..8f0e6f1 100644
--- a/llvm/test/CodeGen/X86/sincos.ll
+++ b/llvm/test/CodeGen/X86/sincos.ll
@@ -9,7 +9,7 @@ declare double @sin(double) readonly
 
 declare x86_fp80 @sinl(x86_fp80) readonly
 
-; SIN: test1:
+; SIN-LABEL: test1:
 define float @test1(float %X) {
         %Y = call float @sinf(float %X) readonly
         ret float %Y
@@ -21,7 +21,7 @@ define float @test1(float %X) {
 ; SAFE: test1
 ; SAFE-NOT: fsin
 
-; SIN: test2:
+; SIN-LABEL: test2:
 define double @test2(double %X) {
         %Y = call double @sin(double %X) readonly
         ret double %Y
@@ -33,7 +33,7 @@ define double @test2(double %X) {
 ; SAFE: test2
 ; SAFE-NOT: fsin
 
-; SIN: test3:
+; SIN-LABEL: test3:
 define x86_fp80 @test3(x86_fp80 %X) {
         %Y = call x86_fp80 @sinl(x86_fp80 %X) readonly
         ret x86_fp80 %Y
@@ -49,8 +49,8 @@ declare double @cos(double) readonly
 declare x86_fp80 @cosl(x86_fp80) readonly
 
 
-; SIN: test4:
-; COS: test3:
+; SIN-LABEL: test4:
+; COS-LABEL: test3:
 define float @test4(float %X) {
         %Y = call float @cosf(float %X) readonly
         ret float %Y
diff --git a/llvm/test/CodeGen/X86/smul-with-overflow.ll b/llvm/test/CodeGen/X86/smul-with-overflow.ll
index 2d0b2f7..cefbda6 100644
--- a/llvm/test/CodeGen/X86/smul-with-overflow.ll
+++ b/llvm/test/CodeGen/X86/smul-with-overflow.ll
@@ -17,7 +17,7 @@ normal:
 overflow:
   %t2 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @no, i32 0, i32 0) ) nounwind
   ret i1 false
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: imull
 ; CHECK-NEXT: jno
 }
@@ -36,7 +36,7 @@ overflow:
 normal:
   %t1 = tail call i32 (i8*, ...)* @printf( i8* getelementptr ([4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind
   ret i1 true
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: imull
 ; CHECK-NEXT: jno
 }
@@ -50,7 +50,7 @@ entry:
 	%tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 2)
 	%tmp2 = extractvalue { i32, i1 } %tmp1, 0
 	ret i32 %tmp2
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: addl
 ; CHECK-NEXT: addl
 ; CHECK-NEXT: ret
@@ -62,7 +62,7 @@ entry:
 	%tmp1 = call { i32, i1 } @llvm.smul.with.overflow.i32(i32 %tmp0, i32 4)
 	%tmp2 = extractvalue { i32, i1 } %tmp1, 0
 	ret i32 %tmp2
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: addl
 ; CHECK: mull
 ; CHECK-NEXT: ret
@@ -78,6 +78,6 @@ entry:
   ret i1 %overflow
 ; Was returning false, should return true (not constant folded yet though).
 ; PR13991
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK-NOT: xorb
 }
diff --git a/llvm/test/CodeGen/X86/sse1.ll b/llvm/test/CodeGen/X86/sse1.ll
index 9b2e05b..47c6429 100644
--- a/llvm/test/CodeGen/X86/sse1.ll
+++ b/llvm/test/CodeGen/X86/sse1.ll
@@ -33,7 +33,7 @@ entry:
   %tmp11 = insertelement <2 x float> undef, float %add.r, i32 0
   %tmp9 = insertelement <2 x float> %tmp11, float %add.i, i32 1
   ret <2 x float> %tmp9
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK-NOT: shufps	$16
 ; CHECK: shufps	$1, 
 ; CHECK-NOT: shufps	$16
diff --git a/llvm/test/CodeGen/X86/sse2-mul.ll b/llvm/test/CodeGen/X86/sse2-mul.ll
index 0466d60..e066368 100644
--- a/llvm/test/CodeGen/X86/sse2-mul.ll
+++ b/llvm/test/CodeGen/X86/sse2-mul.ll
@@ -3,7 +3,7 @@
 define <4 x i32> @test1(<4 x i32> %x, <4 x i32> %y) {
   %m = mul <4 x i32> %x, %y
   ret <4 x i32> %m
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: pshufd $49
 ; CHECK: pmuludq
 ; CHECK: pshufd $49
diff --git a/llvm/test/CodeGen/X86/sse2-vector-shifts.ll b/llvm/test/CodeGen/X86/sse2-vector-shifts.ll
index 312ca95..e2d6125 100644
--- a/llvm/test/CodeGen/X86/sse2-vector-shifts.ll
+++ b/llvm/test/CodeGen/X86/sse2-vector-shifts.ll
@@ -8,7 +8,7 @@ entry:
   ret <8 x i16> %shl
 }
 
-; CHECK: test_sllw_1:
+; CHECK-LABEL: test_sllw_1:
 ; CHECK: psllw   $0, %xmm0
 ; CHECK-NEXT: ret
 
@@ -18,7 +18,7 @@ entry:
   ret <8 x i16> %shl
 }
 
-; CHECK: test_sllw_2:
+; CHECK-LABEL: test_sllw_2:
 ; CHECK: paddw   %xmm0, %xmm0
 ; CHECK-NEXT: ret
 
@@ -28,7 +28,7 @@ entry:
   ret <8 x i16> %shl
 }
 
-; CHECK: test_sllw_3:
+; CHECK-LABEL: test_sllw_3:
 ; CHECK: xorps   %xmm0, %xmm0
 ; CHECK-NEXT: ret
 
@@ -38,7 +38,7 @@ entry:
   ret <4 x i32> %shl
 }
 
-; CHECK: test_slld_1:
+; CHECK-LABEL: test_slld_1:
 ; CHECK: pslld   $0, %xmm0
 ; CHECK-NEXT: ret
 
@@ -48,7 +48,7 @@ entry:
   ret <4 x i32> %shl
 }
 
-; CHECK: test_slld_2:
+; CHECK-LABEL: test_slld_2:
 ; CHECK: paddd   %xmm0, %xmm0
 ; CHECK-NEXT: ret
 
@@ -58,7 +58,7 @@ entry:
   ret <4 x i32> %shl
 }
 
-; CHECK: test_slld_3:
+; CHECK-LABEL: test_slld_3:
 ; CHECK: xorps   %xmm0, %xmm0
 ; CHECK-NEXT: ret
 
@@ -68,7 +68,7 @@ entry:
   ret <2 x i64> %shl
 }
 
-; CHECK: test_sllq_1:
+; CHECK-LABEL: test_sllq_1:
 ; CHECK: psllq   $0, %xmm0
 ; CHECK-NEXT: ret
 
@@ -78,7 +78,7 @@ entry:
   ret <2 x i64> %shl
 }
 
-; CHECK: test_sllq_2:
+; CHECK-LABEL: test_sllq_2:
 ; CHECK: paddq   %xmm0, %xmm0
 ; CHECK-NEXT: ret
 
@@ -88,7 +88,7 @@ entry:
   ret <2 x i64> %shl
 }
 
-; CHECK: test_sllq_3:
+; CHECK-LABEL: test_sllq_3:
 ; CHECK: xorps   %xmm0, %xmm0
 ; CHECK-NEXT: ret
 
@@ -100,7 +100,7 @@ entry:
   ret <8 x i16> %shl
 }
 
-; CHECK: test_sraw_1:
+; CHECK-LABEL: test_sraw_1:
 ; CHECK: psraw   $0, %xmm0
 ; CHECK-NEXT: ret
 
@@ -110,7 +110,7 @@ entry:
   ret <8 x i16> %shl
 }
 
-; CHECK: test_sraw_2:
+; CHECK-LABEL: test_sraw_2:
 ; CHECK: psraw   $1, %xmm0
 ; CHECK-NEXT: ret
 
@@ -120,7 +120,7 @@ entry:
   ret <8 x i16> %shl
 }
 
-; CHECK: test_sraw_3:
+; CHECK-LABEL: test_sraw_3:
 ; CHECK: psraw   $16, %xmm0
 ; CHECK-NEXT: ret
 
@@ -130,7 +130,7 @@ entry:
   ret <4 x i32> %shl
 }
 
-; CHECK: test_srad_1:
+; CHECK-LABEL: test_srad_1:
 ; CHECK: psrad   $0, %xmm0
 ; CHECK-NEXT: ret
 
@@ -140,7 +140,7 @@ entry:
   ret <4 x i32> %shl
 }
 
-; CHECK: test_srad_2:
+; CHECK-LABEL: test_srad_2:
 ; CHECK: psrad   $1, %xmm0
 ; CHECK-NEXT: ret
 
@@ -150,7 +150,7 @@ entry:
   ret <4 x i32> %shl
 }
 
-; CHECK: test_srad_3:
+; CHECK-LABEL: test_srad_3:
 ; CHECK: psrad   $32, %xmm0
 ; CHECK-NEXT: ret
 
@@ -162,7 +162,7 @@ entry:
   ret <8 x i16> %shl
 }
 
-; CHECK: test_srlw_1:
+; CHECK-LABEL: test_srlw_1:
 ; CHECK: psrlw   $0, %xmm0
 ; CHECK-NEXT: ret
 
@@ -172,7 +172,7 @@ entry:
   ret <8 x i16> %shl
 }
 
-; CHECK: test_srlw_2:
+; CHECK-LABEL: test_srlw_2:
 ; CHECK: psrlw   $1, %xmm0
 ; CHECK-NEXT: ret
 
@@ -182,7 +182,7 @@ entry:
   ret <8 x i16> %shl
 }
 
-; CHECK: test_srlw_3:
+; CHECK-LABEL: test_srlw_3:
 ; CHECK: xorps   %xmm0, %xmm0
 ; CHECK-NEXT: ret
 
@@ -192,7 +192,7 @@ entry:
   ret <4 x i32> %shl
 }
 
-; CHECK: test_srld_1:
+; CHECK-LABEL: test_srld_1:
 ; CHECK: psrld   $0, %xmm0
 ; CHECK-NEXT: ret
 
@@ -202,7 +202,7 @@ entry:
   ret <4 x i32> %shl
 }
 
-; CHECK: test_srld_2:
+; CHECK-LABEL: test_srld_2:
 ; CHECK: psrld   $1, %xmm0
 ; CHECK-NEXT: ret
 
@@ -212,7 +212,7 @@ entry:
   ret <4 x i32> %shl
 }
 
-; CHECK: test_srld_3:
+; CHECK-LABEL: test_srld_3:
 ; CHECK: xorps   %xmm0, %xmm0
 ; CHECK-NEXT: ret
 
@@ -222,7 +222,7 @@ entry:
   ret <2 x i64> %shl
 }
 
-; CHECK: test_srlq_1:
+; CHECK-LABEL: test_srlq_1:
 ; CHECK: psrlq   $0, %xmm0
 ; CHECK-NEXT: ret
 
@@ -232,7 +232,7 @@ entry:
   ret <2 x i64> %shl
 }
 
-; CHECK: test_srlq_2:
+; CHECK-LABEL: test_srlq_2:
 ; CHECK: psrlq   $1, %xmm0
 ; CHECK-NEXT: ret
 
@@ -242,6 +242,6 @@ entry:
   ret <2 x i64> %shl
 }
 
-; CHECK: test_srlq_3:
+; CHECK-LABEL: test_srlq_3:
 ; CHECK: xorps   %xmm0, %xmm0
 ; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/X86/sse2.ll b/llvm/test/CodeGen/X86/sse2.ll
index 36a0fd9..217139a 100644
--- a/llvm/test/CodeGen/X86/sse2.ll
+++ b/llvm/test/CodeGen/X86/sse2.ll
@@ -8,7 +8,7 @@ define void @test1(<2 x double>* %r, <2 x double>* %A, double %B) nounwind  {
 	store <2 x double> %tmp9, <2 x double>* %r, align 16
 	ret void
         
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: 	movl	8(%esp), %eax
 ; CHECK-NEXT: 	movapd	(%eax), %xmm0
 ; CHECK-NEXT: 	movlpd	12(%esp), %xmm0
@@ -24,7 +24,7 @@ define void @test2(<2 x double>* %r, <2 x double>* %A, double %B) nounwind  {
 	store <2 x double> %tmp9, <2 x double>* %r, align 16
 	ret void
         
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: 	movl	8(%esp), %eax
 ; CHECK-NEXT: 	movapd	(%eax), %xmm0
 ; CHECK-NEXT: 	movhpd	12(%esp), %xmm0
@@ -60,7 +60,7 @@ define void @test4(<4 x float> %X, <4 x float>* %res) nounwind {
 }
 
 define <4 x i32> @test5(i8** %ptr) nounwind {
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: pxor
 ; CHECK: punpcklbw
 ; CHECK: punpcklwd
@@ -86,7 +86,7 @@ define void @test6(<4 x float>* %res, <4 x float>* %A) nounwind {
         store <4 x float> %tmp2, <4 x float>* %res
         ret void
         
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: 	movaps	(%eax), %xmm0
 ; CHECK:	movaps	%xmm0, (%eax)
 }
@@ -97,7 +97,7 @@ define void @test7() nounwind {
         store <4 x float> %2, <4 x float>* null
         ret void
         
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK:	xorps	%xmm0, %xmm0
 ; CHECK:	movaps	%xmm0, 0
 }
@@ -115,7 +115,7 @@ define <2 x i64> @test8() nounwind {
 	%tmp15 = insertelement <4 x i32> %tmp14, i32 %tmp7, i32 3		; <<4 x i32>> [#uses=1]
 	%tmp16 = bitcast <4 x i32> %tmp15 to <2 x i64>		; <<2 x i64>> [#uses=1]
 	ret <2 x i64> %tmp16
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: movups	(%eax), %xmm0
 }
 
@@ -125,7 +125,7 @@ define <4 x float> @test9(i32 %dummy, float %a, float %b, float %c, float %d) no
 	%tmp12 = insertelement <4 x float> %tmp11, float %c, i32 2		; <<4 x float>> [#uses=1]
 	%tmp13 = insertelement <4 x float> %tmp12, float %d, i32 3		; <<4 x float>> [#uses=1]
 	ret <4 x float> %tmp13
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: movups	8(%esp), %xmm0
 }
 
@@ -135,7 +135,7 @@ define <4 x float> @test10(float %a, float %b, float %c, float %d) nounwind {
 	%tmp12 = insertelement <4 x float> %tmp11, float %c, i32 2		; <<4 x float>> [#uses=1]
 	%tmp13 = insertelement <4 x float> %tmp12, float %d, i32 3		; <<4 x float>> [#uses=1]
 	ret <4 x float> %tmp13
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: movaps	4(%esp), %xmm0
 }
 
@@ -143,7 +143,7 @@ define <2 x double> @test11(double %a, double %b) nounwind {
 	%tmp = insertelement <2 x double> undef, double %a, i32 0		; <<2 x double>> [#uses=1]
 	%tmp7 = insertelement <2 x double> %tmp, double %b, i32 1		; <<2 x double>> [#uses=1]
 	ret <2 x double> %tmp7
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK: movaps	4(%esp), %xmm0
 }
 
@@ -154,7 +154,7 @@ define void @test12() nounwind {
         %tmp4 = fadd <4 x float> %tmp2, %tmp3            ; <<4 x float>> [#uses=1]
         store <4 x float> %tmp4, <4 x float>* null
         ret void
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK: movhlps
 ; CHECK: shufps
 }
@@ -177,7 +177,7 @@ define <4 x float> @test14(<4 x float>* %x, <4 x float>* %y) nounwind {
         %tmp21 = fsub <4 x float> %tmp5, %tmp            ; <<4 x float>> [#uses=1]
         %tmp27 = shufflevector <4 x float> %tmp9, <4 x float> %tmp21, <4 x i32> < i32 0, i32 1, i32 4, i32 5 >                ; <<4 x float>> [#uses=1]
         ret <4 x float> %tmp27
-; CHECK: test14:
+; CHECK-LABEL: test14:
 ; CHECK: 	subps	[[X1:%xmm[0-9]+]], [[X2:%xmm[0-9]+]]
 ; CHECK: 	addps	[[X1]], [[X0:%xmm[0-9]+]]
 ; CHECK: 	movlhps	[[X2]], [[X0]]
@@ -189,12 +189,12 @@ entry:
         %tmp3 = load <4 x float>* %x            ; <<4 x float>> [#uses=1]
         %tmp4 = shufflevector <4 x float> %tmp3, <4 x float> %tmp, <4 x i32> < i32 2, i32 3, i32 6, i32 7 >           ; <<4 x float>> [#uses=1]
         ret <4 x float> %tmp4
-; CHECK: test15:
+; CHECK-LABEL: test15:
 ; CHECK: 	movhlps	%xmm1, %xmm0
 }
 
 ; PR8900
-; CHECK: test16:
+; CHECK-LABEL: test16:
 ; CHECK: unpcklpd
 ; CHECK: ret
 
diff --git a/llvm/test/CodeGen/X86/sse4a.ll b/llvm/test/CodeGen/X86/sse4a.ll
index 076e213..165d476 100644
--- a/llvm/test/CodeGen/X86/sse4a.ll
+++ b/llvm/test/CodeGen/X86/sse4a.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=i686-apple-darwin9 -mattr=sse4a | FileCheck %s
 
 define void @test1(i8* %p, <4 x float> %a) nounwind optsize ssp {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: movntss
   tail call void @llvm.x86.sse4a.movnt.ss(i8* %p, <4 x float> %a) nounwind
   ret void
@@ -10,7 +10,7 @@ define void @test1(i8* %p, <4 x float> %a) nounwind optsize ssp {
 declare void @llvm.x86.sse4a.movnt.ss(i8*, <4 x float>)
 
 define void @test2(i8* %p, <2 x double> %a) nounwind optsize ssp {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movntsd
   tail call void @llvm.x86.sse4a.movnt.sd(i8* %p, <2 x double> %a) nounwind
   ret void
@@ -19,7 +19,7 @@ define void @test2(i8* %p, <2 x double> %a) nounwind optsize ssp {
 declare void @llvm.x86.sse4a.movnt.sd(i8*, <2 x double>)
 
 define <2 x i64> @test3(<2 x i64> %x) nounwind uwtable ssp {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: extrq
   %1 = tail call <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64> %x, i8 3, i8 2)
   ret <2 x i64> %1
@@ -28,7 +28,7 @@ define <2 x i64> @test3(<2 x i64> %x) nounwind uwtable ssp {
 declare <2 x i64> @llvm.x86.sse4a.extrqi(<2 x i64>, i8, i8) nounwind
 
 define <2 x i64> @test4(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: extrq
   %1 = bitcast <2 x i64> %y to <16 x i8>
   %2 = tail call <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64> %x, <16 x i8> %1) nounwind
@@ -38,7 +38,7 @@ define <2 x i64> @test4(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
 declare <2 x i64> @llvm.x86.sse4a.extrq(<2 x i64>, <16 x i8>) nounwind
 
 define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: insertq
   %1 = tail call <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64> %x, <2 x i64> %y, i8 5, i8 6)
   ret <2 x i64> %1
@@ -47,7 +47,7 @@ define <2 x i64> @test5(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
 declare <2 x i64> @llvm.x86.sse4a.insertqi(<2 x i64>, <2 x i64>, i8, i8) nounwind
 
 define <2 x i64> @test6(<2 x i64> %x, <2 x i64> %y) nounwind uwtable ssp {
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: insertq
   %1 = tail call <2 x i64> @llvm.x86.sse4a.insertq(<2 x i64> %x, <2 x i64> %y) nounwind
   ret <2 x i64> %1
diff --git a/llvm/test/CodeGen/X86/stack-align-memcpy.ll b/llvm/test/CodeGen/X86/stack-align-memcpy.ll
index 74945e5..87bb85f 100644
--- a/llvm/test/CodeGen/X86/stack-align-memcpy.ll
+++ b/llvm/test/CodeGen/X86/stack-align-memcpy.ll
@@ -9,7 +9,7 @@ define void @test1(%struct.foo* nocapture %x, i32 %y) nounwind {
   call void @bar(i8* %dynalloc, %struct.foo* align 4 byval %x)
   ret void
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: andl $-16, %esp
 ; CHECK: movl %esp, %esi
 ; CHECK-NOT: rep;movsl
diff --git a/llvm/test/CodeGen/X86/stack-align.ll b/llvm/test/CodeGen/X86/stack-align.ll
index 0ddb237..2918a68 100644
--- a/llvm/test/CodeGen/X86/stack-align.ll
+++ b/llvm/test/CodeGen/X86/stack-align.ll
@@ -45,7 +45,7 @@ entry:
   %0 = ptrtoint [2048 x i8]* %buffer to i32
   %and = and i32 %0, -16
   ret i32 %and
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK-NOT: and
 ; CHECK: ret
 }
diff --git a/llvm/test/CodeGen/X86/store-narrow.ll b/llvm/test/CodeGen/X86/store-narrow.ll
index 0dd228e..fab266f 100644
--- a/llvm/test/CodeGen/X86/store-narrow.ll
+++ b/llvm/test/CodeGen/X86/store-narrow.ll
@@ -13,10 +13,10 @@ entry:
   store i32 %D, i32* %a0, align 4
   ret void
   
-; X64: test1:
+; X64-LABEL: test1:
 ; X64: movb	%sil, (%rdi)
 
-; X32: test1:
+; X32-LABEL: test1:
 ; X32: movb	8(%esp), %al
 ; X32: movb	%al, (%{{.*}})
 }
@@ -30,10 +30,10 @@ entry:
   %D = or i32 %B, %CS
   store i32 %D, i32* %a0, align 4
   ret void
-; X64: test2:
+; X64-LABEL: test2:
 ; X64: movb	%sil, 1(%rdi)
 
-; X32: test2:
+; X32-LABEL: test2:
 ; X32: movb	8(%esp), %al
 ; X32: movb	%al, 1(%{{.*}})
 }
@@ -46,10 +46,10 @@ entry:
   %D = or i32 %B, %C
   store i32 %D, i32* %a0, align 4
   ret void
-; X64: test3:
+; X64-LABEL: test3:
 ; X64: movw	%si, (%rdi)
 
-; X32: test3:
+; X32-LABEL: test3:
 ; X32: movw	8(%esp), %ax
 ; X32: movw	%ax, (%{{.*}})
 }
@@ -63,10 +63,10 @@ entry:
   %D = or i32 %B, %CS
   store i32 %D, i32* %a0, align 4
   ret void
-; X64: test4:
+; X64-LABEL: test4:
 ; X64: movw	%si, 2(%rdi)
 
-; X32: test4:
+; X32-LABEL: test4:
 ; X32: movl	8(%esp), %eax
 ; X32: movw	%ax, 2(%{{.*}})
 }
@@ -80,10 +80,10 @@ entry:
   %D = or i64 %B, %CS
   store i64 %D, i64* %a0, align 4
   ret void
-; X64: test5:
+; X64-LABEL: test5:
 ; X64: movw	%si, 2(%rdi)
 
-; X32: test5:
+; X32-LABEL: test5:
 ; X32: movzwl	8(%esp), %eax
 ; X32: movw	%ax, 2(%{{.*}})
 }
@@ -97,11 +97,11 @@ entry:
   %D = or i64 %B, %CS
   store i64 %D, i64* %a0, align 4
   ret void
-; X64: test6:
+; X64-LABEL: test6:
 ; X64: movb	%sil, 5(%rdi)
 
 
-; X32: test6:
+; X32-LABEL: test6:
 ; X32: movb	8(%esp), %al
 ; X32: movb	%al, 5(%{{.*}})
 }
@@ -116,11 +116,11 @@ entry:
   %D = or i64 %B, %CS
   store i64 %D, i64* %a0, align 4
   ret i32 %OtherLoad
-; X64: test7:
+; X64-LABEL: test7:
 ; X64: movb	%sil, 5(%rdi)
 
 
-; X32: test7:
+; X32-LABEL: test7:
 ; X32: movb	8(%esp), %cl
 ; X32: movb	%cl, 5(%{{.*}})
 }
@@ -129,7 +129,7 @@ entry:
 
 @g_16 = internal global i32 -1
 
-; X64: test8:
+; X64-LABEL: test8:
 ; X64-NEXT: movl _g_16(%rip), %eax
 ; X64-NEXT: movl $0, _g_16(%rip)
 ; X64-NEXT: orl  $1, %eax
@@ -143,7 +143,7 @@ define void @test8() nounwind {
   ret void
 }
 
-; X64: test9:
+; X64-LABEL: test9:
 ; X64-NEXT: orb $1, _g_16(%rip)
 ; X64-NEXT: ret
 define void @test9() nounwind {
@@ -154,7 +154,7 @@ define void @test9() nounwind {
 }
 
 ; rdar://8494845 + PR8244
-; X64: test10:
+; X64-LABEL: test10:
 ; X64-NEXT: movsbl	(%rdi), %eax
 ; X64-NEXT: shrl	$8, %eax
 ; X64-NEXT: ret
diff --git a/llvm/test/CodeGen/X86/store_op_load_fold.ll b/llvm/test/CodeGen/X86/store_op_load_fold.ll
index 070cccd..41b0a9c2 100644
--- a/llvm/test/CodeGen/X86/store_op_load_fold.ll
+++ b/llvm/test/CodeGen/X86/store_op_load_fold.ll
@@ -19,7 +19,7 @@ define void @foo() nounwind {
 %struct.S2 = type { i64, i16, [2 x i8], i8, [3 x i8], [7 x i8], i8, [8 x i8] }
 @s2 = external global %struct.S2, align 16
 define void @test2() nounwind uwtable ssp {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: mov
 ; CHECK-NEXT: and
 ; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/X86/sub.ll b/llvm/test/CodeGen/X86/sub.ll
index ee5ea1d..3cf79a3 100644
--- a/llvm/test/CodeGen/X86/sub.ll
+++ b/llvm/test/CodeGen/X86/sub.ll
@@ -4,7 +4,7 @@ define i32 @test1(i32 %x) {
   %xor = xor i32 %x, 31
   %sub = sub i32 32, %xor
   ret i32 %sub
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK:      xorl $-32
 ; CHECK-NEXT: addl $33
 ; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/X86/switch-bt.ll b/llvm/test/CodeGen/X86/switch-bt.ll
index 58a5c03..a80002b 100644
--- a/llvm/test/CodeGen/X86/switch-bt.ll
+++ b/llvm/test/CodeGen/X86/switch-bt.ll
@@ -53,7 +53,7 @@ declare void @foo(i32)
 ; Don't zero extend the test operands to pointer type if it can be avoided.
 ; rdar://8781238
 define void @test2(i32 %x) nounwind ssp {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: cmpl $6
 ; CHECK: ja
 
@@ -81,7 +81,7 @@ if.end:                                           ; preds = %entry
 declare void @bar()
 
 define void @test3(i32 %x) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: cmpl $5
 ; CHECK: ja
 ; CHECK: cmpl $4
diff --git a/llvm/test/CodeGen/X86/switch-order-weight.ll b/llvm/test/CodeGen/X86/switch-order-weight.ll
index 0fdd56d..207e0b3 100644
--- a/llvm/test/CodeGen/X86/switch-order-weight.ll
+++ b/llvm/test/CodeGen/X86/switch-order-weight.ll
@@ -10,7 +10,7 @@ entry:
     i32 20, label %if.then5
   ]
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NOT: unr
 ; CHECK: cmpl $10
 ; CHECK: bar
diff --git a/llvm/test/CodeGen/X86/tail-call-got.ll b/llvm/test/CodeGen/X86/tail-call-got.ll
index 1d7eb2e..84d561d 100644
--- a/llvm/test/CodeGen/X86/tail-call-got.ll
+++ b/llvm/test/CodeGen/X86/tail-call-got.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3
 target triple = "i386-unknown-freebsd9.0"
 
 define double @test1(double %x) nounwind readnone {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: movl foo@GOT
 ; CHECK-NEXT: jmpl
   %1 = tail call double @foo(double %x) nounwind readnone
@@ -14,7 +14,7 @@ define double @test1(double %x) nounwind readnone {
 declare double @foo(double) readnone
 
 define double @test2(double %x) nounwind readnone {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: movl sin@GOT
 ; CHECK-NEXT: jmpl
   %1 = tail call double @sin(double %x) nounwind readnone
diff --git a/llvm/test/CodeGen/X86/tailcall-disable.ll b/llvm/test/CodeGen/X86/tailcall-disable.ll
index b628f5e..1fd2d72 100644
--- a/llvm/test/CodeGen/X86/tailcall-disable.ll
+++ b/llvm/test/CodeGen/X86/tailcall-disable.ll
@@ -15,12 +15,12 @@ entry:
   ret i32 %call
 }
 
-; CALL: test1:
+; CALL-LABEL: test1:
 ; CALL-NOT: ret
 ; CALL: callq helper
 ; CALL: ret
 
-; JMP: test1:
+; JMP-LABEL: test1:
 ; JMP-NOT: ret
 ; JMP: jmp helper # TAILCALL
 
@@ -30,11 +30,11 @@ entry:
   ret i32 %call
 }
 
-; CALL: test2:
+; CALL-LABEL: test2:
 ; CALL-NOT: ret
 ; CALL: callq test2
 ; CALL: ret
 
-; JMP: test2:
+; JMP-LABEL: test2:
 ; JMP-NOT: ret
 ; JMP: jmp test2 # TAILCALL
diff --git a/llvm/test/CodeGen/X86/testl-commute.ll b/llvm/test/CodeGen/X86/testl-commute.ll
index 0e6f636..bf6debf 100644
--- a/llvm/test/CodeGen/X86/testl-commute.ll
+++ b/llvm/test/CodeGen/X86/testl-commute.ll
@@ -7,7 +7,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-apple-darwin7"
 
 define i32 @test(i32* %P, i32* %G) nounwind {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: ret
 ; CHECK: testl (%{{.*}}), %{{.*}}
 ; CHECK: ret
@@ -28,7 +28,7 @@ bb1:		; preds = %entry
 }
 
 define i32 @test2(i32* %P, i32* %G) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK-NOT: ret
 ; CHECK: testl (%{{.*}}), %{{.*}}
 ; CHECK: ret
@@ -49,7 +49,7 @@ bb1:		; preds = %entry
 }
 
 define i32 @test3(i32* %P, i32* %G) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK-NOT: ret
 ; CHECK: testl (%{{.*}}), %{{.*}}
 ; CHECK: ret
diff --git a/llvm/test/CodeGen/X86/tlv-1.ll b/llvm/test/CodeGen/X86/tlv-1.ll
index 92dac30..f970011 100644
--- a/llvm/test/CodeGen/X86/tlv-1.ll
+++ b/llvm/test/CodeGen/X86/tlv-1.ll
@@ -18,7 +18,7 @@ entry:
 ; rdar://10291355
 define i32 @test() nounwind readonly ssp {
 entry:
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: movq _a@TLVP(%rip),
 ; CHECK: callq *
 ; CHECK: movl (%rax), [[REGISTER:%[a-z]+]]
diff --git a/llvm/test/CodeGen/X86/trap.ll b/llvm/test/CodeGen/X86/trap.ll
index 3f44be0..149c667 100644
--- a/llvm/test/CodeGen/X86/trap.ll
+++ b/llvm/test/CodeGen/X86/trap.ll
@@ -1,6 +1,6 @@
 ; RUN: llc < %s -march=x86 -mcpu=yonah | FileCheck %s
 
-; CHECK: test0:
+; CHECK-LABEL: test0:
 ; CHECK: ud2
 define i32 @test0() noreturn nounwind  {
 entry:
@@ -8,7 +8,7 @@ entry:
 	unreachable
 }
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: int3
 define i32 @test1() noreturn nounwind  {
 entry:
diff --git a/llvm/test/CodeGen/X86/trunc-to-bool.ll b/llvm/test/CodeGen/X86/trunc-to-bool.ll
index 92b6859..3711cf1 100644
--- a/llvm/test/CodeGen/X86/trunc-to-bool.ll
+++ b/llvm/test/CodeGen/X86/trunc-to-bool.ll
@@ -7,7 +7,7 @@ define zeroext i1 @test1(i32 %X)  nounwind {
     %Y = trunc i32 %X to i1
     ret i1 %Y
 }
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: andl $1, %eax
 
 define i1 @test2(i32 %val, i32 %mask) nounwind {
@@ -21,7 +21,7 @@ ret_true:
 ret_false:
     ret i1 false
 }
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: btl %eax
 
 define i32 @test3(i8* %ptr) nounwind {
@@ -33,7 +33,7 @@ cond_true:
 cond_false:
     ret i32 42
 }
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: testb $1, (%eax)
 
 define i32 @test4(i8* %ptr) nounwind {
@@ -44,7 +44,7 @@ cond_true:
 cond_false:
     ret i32 42
 }
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: testb $1, 4(%esp)
 
 define i32 @test5(double %d) nounwind {
@@ -55,5 +55,5 @@ cond_true:
 cond_false:
     ret i32 42
 }
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: testb $1
diff --git a/llvm/test/CodeGen/X86/twoaddr-lea.ll b/llvm/test/CodeGen/X86/twoaddr-lea.ll
index 9d58019..b5ca027 100644
--- a/llvm/test/CodeGen/X86/twoaddr-lea.ll
+++ b/llvm/test/CodeGen/X86/twoaddr-lea.ll
@@ -10,7 +10,7 @@
 @G = external global i32
 
 define i32 @test1(i32 %X) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NOT: mov
 ; CHECK: leal 1(%rdi)
         %Z = add i32 %X, 1
@@ -23,7 +23,7 @@ define i32 @test1(i32 %X) nounwind {
 ; commutted (which would require inserting a copy).
 define i32 @test2(i32 inreg %a, i32 inreg %b, i32 %c, i32 %d) nounwind {
 entry:
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: leal
 ; CHECK-NOT: leal
 ; CHECK-NOT: mov
@@ -38,7 +38,7 @@ entry:
 ; rdar://9002648
 define i64 @test3(i64 %x) nounwind readnone ssp {
 entry:
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: leaq (%rdi,%rdi), %rax
 ; CHECK-NOT: addq
 ; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/X86/umul-with-overflow.ll b/llvm/test/CodeGen/X86/umul-with-overflow.ll
index e5858de..52d1dc2 100644
--- a/llvm/test/CodeGen/X86/umul-with-overflow.ll
+++ b/llvm/test/CodeGen/X86/umul-with-overflow.ll
@@ -19,7 +19,7 @@ entry:
 	%tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 2)
 	%tmp2 = extractvalue { i32, i1 } %tmp1, 0
 	ret i32 %tmp2
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: addl
 ; CHECK-NEXT: addl
 ; CHECK-NEXT: ret
@@ -31,7 +31,7 @@ entry:
 	%tmp1 = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 %tmp0, i32 4)
 	%tmp2 = extractvalue { i32, i1 } %tmp1, 0
 	ret i32 %tmp2
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: addl
 ; CHECK: mull
 ; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/X86/use-add-flags.ll b/llvm/test/CodeGen/X86/use-add-flags.ll
index a0448ec..fd57f5c 100644
--- a/llvm/test/CodeGen/X86/use-add-flags.ll
+++ b/llvm/test/CodeGen/X86/use-add-flags.ll
@@ -6,7 +6,7 @@
 
 ; Use the flags on the add.
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ;     CHECK: addl
 ; CHECK-NOT: test
 ;     CHECK: cmovnsl
@@ -25,7 +25,7 @@ declare void @foo(i32)
 ; Don't use the flags result of the and here, since the and has no
 ; other use. A simple test is better.
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: testb   $16, {{%dil|%cl}}
 
 define void @test2(i32 %x) nounwind {
@@ -41,7 +41,7 @@ false:
 
 ; Do use the flags result of the and here, since the and has another use.
 
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ;      CHECK: andl    $16, %e
 ; CHECK-NEXT: jne
 
diff --git a/llvm/test/CodeGen/X86/v2f32.ll b/llvm/test/CodeGen/X86/v2f32.ll
index ba54833..f2bebf5 100644
--- a/llvm/test/CodeGen/X86/v2f32.ll
+++ b/llvm/test/CodeGen/X86/v2f32.ll
@@ -10,20 +10,20 @@ define void @test1(<2 x float> %Q, float *%P2) nounwind {
 
   store float %c, float* %P2
   ret void
-; X64: test1:
+; X64-LABEL: test1:
 ; X64-NEXT: pshufd	$1, %xmm0, %xmm1
 ; X64-NEXT: addss	%xmm0, %xmm1
 ; X64-NEXT: movss	%xmm1, (%rdi)
 ; X64-NEXT: ret
 
-; W64: test1:
+; W64-LABEL: test1:
 ; W64-NEXT: movdqa  (%rcx), %xmm0
 ; W64-NEXT: pshufd  $1, %xmm0, %xmm1
 ; W64-NEXT: addss   %xmm0, %xmm1
 ; W64-NEXT: movss   %xmm1, (%rdx)
 ; W64-NEXT: ret
 
-; X32: test1:
+; X32-LABEL: test1:
 ; X32-NEXT: pshufd	$1, %xmm0, %xmm1
 ; X32-NEXT: addss	%xmm0, %xmm1
 ; X32-NEXT: movl	4(%esp), %eax
@@ -36,16 +36,16 @@ define <2 x float> @test2(<2 x float> %Q, <2 x float> %R, <2 x float> *%P) nounw
   %Z = fadd <2 x float> %Q, %R
   ret <2 x float> %Z
   
-; X64: test2:
+; X64-LABEL: test2:
 ; X64-NEXT: addps	%xmm1, %xmm0
 ; X64-NEXT: ret
 
-; W64: test2:
+; W64-LABEL: test2:
 ; W64-NEXT: movaps  (%rcx), %xmm0
 ; W64-NEXT: addps   (%rdx), %xmm0
 ; W64-NEXT: ret
 
-; X32: test2:
+; X32-LABEL: test2:
 ; X32:      addps	%xmm1, %xmm0
 }
 
@@ -54,16 +54,16 @@ define <2 x float> @test3(<4 x float> %A) nounwind {
 	%B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
 	%C = fadd <2 x float> %B, %B
 	ret <2 x float> %C
-; X64: test3:
+; X64-LABEL: test3:
 ; X64-NEXT: addps	%xmm0, %xmm0
 ; X64-NEXT: ret
 
-; W64: test3:
+; W64-LABEL: test3:
 ; W64-NEXT: movaps  (%rcx), %xmm0
 ; W64-NEXT: addps   %xmm0, %xmm0
 ; W64-NEXT: ret
 
-; X32: test3:
+; X32-LABEL: test3:
 ; X32-NEXT: addps	%xmm0, %xmm0
 ; X32-NEXT: ret
 }
@@ -71,16 +71,16 @@ define <2 x float> @test3(<4 x float> %A) nounwind {
 define <2 x float> @test4(<2 x float> %A) nounwind {
 	%C = fadd <2 x float> %A, %A
 	ret <2 x float> %C
-; X64: test4:
+; X64-LABEL: test4:
 ; X64-NEXT: addps	%xmm0, %xmm0
 ; X64-NEXT: ret
 
-; W64: test4:
+; W64-LABEL: test4:
 ; W64-NEXT: movaps  (%rcx), %xmm0
 ; W64-NEXT: addps   %xmm0, %xmm0
 ; W64-NEXT: ret
 
-; X32: test4:
+; X32-LABEL: test4:
 ; X32-NEXT: addps	%xmm0, %xmm0
 ; X32-NEXT: ret
 }
@@ -95,18 +95,18 @@ BB:
 	%E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
 	ret <4 x float> %E
         
-; X64: test5:
+; X64-LABEL: test5:
 ; X64-NEXT: addps	%xmm0, %xmm0
 ; X64-NEXT: addps	%xmm0, %xmm0
 ; X64-NEXT: ret
 
-; W64: test5:
+; W64-LABEL: test5:
 ; W64-NEXT: movaps  (%rcx), %xmm0
 ; W64-NEXT: addps   %xmm0, %xmm0
 ; W64-NEXT: addps   %xmm0, %xmm0
 ; W64-NEXT: ret
 
-; X32: test5:
+; X32-LABEL: test5:
 ; X32-NEXT: addps	%xmm0, %xmm0
 ; X32-NEXT: addps	%xmm0, %xmm0
 ; X32-NEXT: ret
diff --git a/llvm/test/CodeGen/X86/vec_compare-sse4.ll b/llvm/test/CodeGen/X86/vec_compare-sse4.ll
index b4a4a4c..a08d9f5 100644
--- a/llvm/test/CodeGen/X86/vec_compare-sse4.ll
+++ b/llvm/test/CodeGen/X86/vec_compare-sse4.ll
@@ -3,13 +3,13 @@
 ; RUN: llc < %s -march=x86 -mattr=+sse42 | FileCheck %s -check-prefix=SSE42
 
 define <2 x i64> @test1(<2 x i64> %A, <2 x i64> %B) nounwind {
-; SSE42: test1:
+; SSE42-LABEL: test1:
 ; SSE42: pcmpgtq
 ; SSE42: ret
-; SSE41: test1:
+; SSE41-LABEL: test1:
 ; SSE41-NOT: pcmpgtq
 ; SSE41: ret
-; SSE2: test1:
+; SSE2-LABEL: test1:
 ; SSE2-NOT: pcmpgtq
 ; SSE2: ret
 
@@ -19,13 +19,13 @@ define <2 x i64> @test1(<2 x i64> %A, <2 x i64> %B) nounwind {
 }
 
 define <2 x i64> @test2(<2 x i64> %A, <2 x i64> %B) nounwind {
-; SSE42: test2:
+; SSE42-LABEL: test2:
 ; SSE42: pcmpeqq
 ; SSE42: ret
-; SSE41: test2:
+; SSE41-LABEL: test2:
 ; SSE41: pcmpeqq
 ; SSE41: ret
-; SSE2: test2:
+; SSE2-LABEL: test2:
 ; SSE2-NOT: pcmpeqq
 ; SSE2: ret
 
diff --git a/llvm/test/CodeGen/X86/vec_compare.ll b/llvm/test/CodeGen/X86/vec_compare.ll
index fd5c234..365fe92 100644
--- a/llvm/test/CodeGen/X86/vec_compare.ll
+++ b/llvm/test/CodeGen/X86/vec_compare.ll
@@ -2,7 +2,7 @@
 
 
 define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: pcmpgtd
 ; CHECK: ret
 
@@ -12,7 +12,7 @@ define <4 x i32> @test1(<4 x i32> %A, <4 x i32> %B) nounwind {
 }
 
 define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: pcmp
 ; CHECK: pcmp
 ; CHECK: pxor
@@ -23,7 +23,7 @@ define <4 x i32> @test2(<4 x i32> %A, <4 x i32> %B) nounwind {
 }
 
 define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: pcmpgtd
 ; CHECK: movdqa
 ; CHECK: ret
@@ -33,7 +33,7 @@ define <4 x i32> @test3(<4 x i32> %A, <4 x i32> %B) nounwind {
 }
 
 define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind {
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: movdqa
 ; CHECK: pcmpgtd
 ; CHECK: ret
@@ -43,7 +43,7 @@ define <4 x i32> @test4(<4 x i32> %A, <4 x i32> %B) nounwind {
 }
 
 define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: pcmpeqd
 ; CHECK: pshufd $-79
 ; CHECK: pand
@@ -54,7 +54,7 @@ define <2 x i64> @test5(<2 x i64> %A, <2 x i64> %B) nounwind {
 }
 
 define <2 x i64> @test6(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: pcmpeqd
 ; CHECK: pshufd $-79
 ; CHECK: pand
@@ -72,7 +72,7 @@ define <2 x i64> @test7(<2 x i64> %A, <2 x i64> %B) nounwind {
 ; CHECK-NEXT: .long	0
 ; CHECK-NEXT: .long	2147483648
 ; CHECK-NEXT: .long	0
-; CHECK: test7:
+; CHECK-LABEL: test7:
 ; CHECK: movdqa [[CONSTSEG]], [[CONSTREG:%xmm[0-9]*]]
 ; CHECK: pxor [[CONSTREG]]
 ; CHECK: pxor [[CONSTREG]]
@@ -90,7 +90,7 @@ define <2 x i64> @test7(<2 x i64> %A, <2 x i64> %B) nounwind {
 }
 
 define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test8:
+; CHECK-LABEL: test8:
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm0
@@ -107,7 +107,7 @@ define <2 x i64> @test8(<2 x i64> %A, <2 x i64> %B) nounwind {
 }
 
 define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm0
@@ -126,7 +126,7 @@ define <2 x i64> @test9(<2 x i64> %A, <2 x i64> %B) nounwind {
 }
 
 define <2 x i64> @test10(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm1
@@ -150,7 +150,7 @@ define <2 x i64> @test11(<2 x i64> %A, <2 x i64> %B) nounwind {
 ; CHECK-NEXT: .long	2147483648
 ; CHECK-NEXT: .long	2147483648
 ; CHECK-NEXT: .long	2147483648
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK: movdqa [[CONSTSEG]], [[CONSTREG:%xmm[0-9]*]]
 ; CHECK: pxor [[CONSTREG]]
 ; CHECK: pxor [[CONSTREG]]
@@ -168,7 +168,7 @@ define <2 x i64> @test11(<2 x i64> %A, <2 x i64> %B) nounwind {
 }
 
 define <2 x i64> @test12(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm0
@@ -185,7 +185,7 @@ define <2 x i64> @test12(<2 x i64> %A, <2 x i64> %B) nounwind {
 }
 
 define <2 x i64> @test13(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test13:
+; CHECK-LABEL: test13:
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm0
@@ -204,7 +204,7 @@ define <2 x i64> @test13(<2 x i64> %A, <2 x i64> %B) nounwind {
 }
 
 define <2 x i64> @test14(<2 x i64> %A, <2 x i64> %B) nounwind {
-; CHECK: test14:
+; CHECK-LABEL: test14:
 ; CHECK: pxor
 ; CHECK: pxor
 ; CHECK: pcmpgtd %xmm1
diff --git a/llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll b/llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll
index 59ceb2e..56855d3 100644
--- a/llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll
+++ b/llvm/test/CodeGen/X86/vec_sdiv_to_shift.ll
@@ -77,4 +77,4 @@ entry:
 define <4 x i32> @sdiv_non_splat(<4 x i32> %x) {
   %y = sdiv <4 x i32> %x, <i32 2, i32 0, i32 0, i32 0>
   ret <4 x i32> %y
-}
\ No newline at end of file
+}
diff --git a/llvm/test/CodeGen/X86/vec_splat-2.ll b/llvm/test/CodeGen/X86/vec_splat-2.ll
index 5c668b7..9d82f97 100644
--- a/llvm/test/CodeGen/X86/vec_splat-2.ll
+++ b/llvm/test/CodeGen/X86/vec_splat-2.ll
@@ -24,7 +24,7 @@ define void @test(<2 x i64>* %P, i8 %x) nounwind {
 	store <2 x i64> %tmp73.upgrd.1, <2 x i64>* %P
 	ret void
 
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK-NOT: pshufd
 ; CHECK: punpcklbw
 ; CHECK: punpcklbw
diff --git a/llvm/test/CodeGen/X86/vec_splat.ll b/llvm/test/CodeGen/X86/vec_splat.ll
index deedee8..543c96e 100644
--- a/llvm/test/CodeGen/X86/vec_splat.ll
+++ b/llvm/test/CodeGen/X86/vec_splat.ll
@@ -11,10 +11,10 @@ define void @test_v4sf(<4 x float>* %P, <4 x float>* %Q, float %X) nounwind {
 	store <4 x float> %tmp10, <4 x float>* %P
 	ret void
 
-; SSE2: test_v4sf:
+; SSE2-LABEL: test_v4sf:
 ; SSE2: pshufd $0
 
-; SSE3: test_v4sf:
+; SSE3-LABEL: test_v4sf:
 ; SSE3: pshufd $0
 }
 
@@ -26,9 +26,9 @@ define void @test_v2sd(<2 x double>* %P, <2 x double>* %Q, double %X) nounwind {
 	store <2 x double> %tmp6, <2 x double>* %P
 	ret void
 
-; SSE2: test_v2sd:
+; SSE2-LABEL: test_v2sd:
 ; SSE2: shufpd $0
 
-; SSE3: test_v2sd:
+; SSE3-LABEL: test_v2sd:
 ; SSE3: movddup
 }
diff --git a/llvm/test/CodeGen/X86/vec_ss_load_fold.ll b/llvm/test/CodeGen/X86/vec_ss_load_fold.ll
index c294df5..2eb911f 100644
--- a/llvm/test/CodeGen/X86/vec_ss_load_fold.ll
+++ b/llvm/test/CodeGen/X86/vec_ss_load_fold.ll
@@ -15,7 +15,7 @@ define i16 @test1(float %f) nounwind {
 	%tmp.upgrd.1 = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 )		; <i32> [#uses=1]
 	%tmp69 = trunc i32 %tmp.upgrd.1 to i16		; <i16> [#uses=1]
 	ret i16 %tmp69
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: subss	LCPI0_
 ; CHECK: mulss	LCPI0_
 ; CHECK: minss	LCPI0_
@@ -30,7 +30,7 @@ define i16 @test2(float %f) nounwind {
 	%tmp = tail call i32 @llvm.x86.sse.cvttss2si( <4 x float> %tmp59 )		; <i32> [#uses=1]
 	%tmp69 = trunc i32 %tmp to i16		; <i16> [#uses=1]
 	ret i16 %tmp69
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: addss	LCPI1_
 ; CHECK: mulss	LCPI1_
 ; CHECK: minss	LCPI1_
@@ -55,7 +55,7 @@ define <4 x float> @test3(<4 x float> %A, float *%b, i32 %C) nounwind {
   %B = insertelement <4 x float> undef, float %a, i32 0
   %X = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %A, <4 x float> %B, i32 4)
   ret <4 x float> %X
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK: roundss	$4, (%eax), %xmm0
 }
 
@@ -65,7 +65,7 @@ define <4 x float> @test4(<4 x float> %A, float *%b, i32 %C) nounwind {
   %q = call <4 x float> @f()
   %X = call <4 x float> @llvm.x86.sse41.round.ss(<4 x float> %q, <4 x float> %B, i32 4)
   ret <4 x float> %X
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK: movss	(%eax), %xmm
 ; CHECK: call
 ; CHECK: roundss $4, %xmm{{.*}}, %xmm0
@@ -77,7 +77,7 @@ entry:
   %0 = tail call <2 x double> @llvm.x86.sse2.cvtsi2sd(<2 x double> <double
 4.569870e+02, double 1.233210e+02>, i32 128) nounwind readnone
   ret <2 x double> %0
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: mov
 ; CHECK: mov
 ; CHECK: cvtsi2sd
diff --git a/llvm/test/CodeGen/X86/vec_uint_to_fp.ll b/llvm/test/CodeGen/X86/vec_uint_to_fp.ll
index fe7fa2f..ee20f1f 100644
--- a/llvm/test/CodeGen/X86/vec_uint_to_fp.ll
+++ b/llvm/test/CodeGen/X86/vec_uint_to_fp.ll
@@ -2,7 +2,7 @@
 
 ; Test that we are not lowering uinttofp to scalars
 define <4 x float> @test1(<4 x i32> %A) nounwind {
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NOT: cvtsd2ss
 ; CHECK: ret
   %C = uitofp <4 x i32> %A to <4 x float>
diff --git a/llvm/test/CodeGen/X86/viabs.ll b/llvm/test/CodeGen/X86/viabs.ll
index f748a14..0be00da 100644
--- a/llvm/test/CodeGen/X86/viabs.ll
+++ b/llvm/test/CodeGen/X86/viabs.ll
@@ -3,18 +3,18 @@
 ; RUN: llc < %s -march=x86-64 -mcpu=core-avx2 | FileCheck %s -check-prefix=AVX2
 
 define <4 x i32> @test1(<4 x i32> %a) nounwind {
-; SSE2: test1:
+; SSE2-LABEL: test1:
 ; SSE2: movdqa
 ; SSE2: psrad $31
 ; SSE2-NEXT: padd
 ; SSE2-NEXT: pxor
 ; SSE2-NEXT: ret
 
-; SSSE3: test1:
+; SSSE3-LABEL: test1:
 ; SSSE3: pabsd
 ; SSSE3-NEXT: ret
 
-; AVX2: test1:
+; AVX2-LABEL: test1:
 ; AVX2: vpabsd
 ; AVX2-NEXT: ret
         %tmp1neg = sub <4 x i32> zeroinitializer, %a
@@ -24,18 +24,18 @@ define <4 x i32> @test1(<4 x i32> %a) nounwind {
 }
 
 define <4 x i32> @test2(<4 x i32> %a) nounwind {
-; SSE2: test2:
+; SSE2-LABEL: test2:
 ; SSE2: movdqa
 ; SSE2: psrad $31
 ; SSE2-NEXT: padd
 ; SSE2-NEXT: pxor
 ; SSE2-NEXT: ret
 
-; SSSE3: test2:
+; SSSE3-LABEL: test2:
 ; SSSE3: pabsd
 ; SSSE3-NEXT: ret
 
-; AVX2: test2:
+; AVX2-LABEL: test2:
 ; AVX2: vpabsd
 ; AVX2-NEXT: ret
         %tmp1neg = sub <4 x i32> zeroinitializer, %a
@@ -45,18 +45,18 @@ define <4 x i32> @test2(<4 x i32> %a) nounwind {
 }
 
 define <8 x i16> @test3(<8 x i16> %a) nounwind {
-; SSE2: test3:
+; SSE2-LABEL: test3:
 ; SSE2: movdqa
 ; SSE2: psraw $15
 ; SSE2-NEXT: padd
 ; SSE2-NEXT: pxor
 ; SSE2-NEXT: ret
 
-; SSSE3: test3:
+; SSSE3-LABEL: test3:
 ; SSSE3: pabsw
 ; SSSE3-NEXT: ret
 
-; AVX2: test3:
+; AVX2-LABEL: test3:
 ; AVX2: vpabsw
 ; AVX2-NEXT: ret
         %tmp1neg = sub <8 x i16> zeroinitializer, %a
@@ -66,18 +66,18 @@ define <8 x i16> @test3(<8 x i16> %a) nounwind {
 }
 
 define <16 x i8> @test4(<16 x i8> %a) nounwind {
-; SSE2: test4:
+; SSE2-LABEL: test4:
 ; SSE2: pxor
 ; SSE2: pcmpgtb
 ; SSE2-NEXT: padd
 ; SSE2-NEXT: pxor
 ; SSE2-NEXT: ret
 
-; SSSE3: test4:
+; SSSE3-LABEL: test4:
 ; SSSE3: pabsb
 ; SSSE3-NEXT: ret
 
-; AVX2: test4:
+; AVX2-LABEL: test4:
 ; AVX2: vpabsb
 ; AVX2-NEXT: ret
         %tmp1neg = sub <16 x i8> zeroinitializer, %a
@@ -87,18 +87,18 @@ define <16 x i8> @test4(<16 x i8> %a) nounwind {
 }
 
 define <4 x i32> @test5(<4 x i32> %a) nounwind {
-; SSE2: test5:
+; SSE2-LABEL: test5:
 ; SSE2: movdqa
 ; SSE2: psrad $31
 ; SSE2-NEXT: padd
 ; SSE2-NEXT: pxor
 ; SSE2-NEXT: ret
 
-; SSSE3: test5:
+; SSSE3-LABEL: test5:
 ; SSSE3: pabsd
 ; SSSE3-NEXT: ret
 
-; AVX2: test5:
+; AVX2-LABEL: test5:
 ; AVX2: vpabsd
 ; AVX2-NEXT: ret
         %tmp1neg = sub <4 x i32> zeroinitializer, %a
@@ -108,12 +108,12 @@ define <4 x i32> @test5(<4 x i32> %a) nounwind {
 }
 
 define <8 x i32> @test6(<8 x i32> %a) nounwind {
-; SSSE3: test6:
+; SSSE3-LABEL: test6:
 ; SSSE3: pabsd
 ; SSSE3: pabsd
 ; SSSE3-NEXT: ret
 
-; AVX2: test6:
+; AVX2-LABEL: test6:
 ; AVX2: vpabsd {{.*}}%ymm
 ; AVX2-NEXT: ret
         %tmp1neg = sub <8 x i32> zeroinitializer, %a
@@ -123,12 +123,12 @@ define <8 x i32> @test6(<8 x i32> %a) nounwind {
 }
 
 define <8 x i32> @test7(<8 x i32> %a) nounwind {
-; SSSE3: test7:
+; SSSE3-LABEL: test7:
 ; SSSE3: pabsd
 ; SSSE3: pabsd
 ; SSSE3-NEXT: ret
 
-; AVX2: test7:
+; AVX2-LABEL: test7:
 ; AVX2: vpabsd {{.*}}%ymm
 ; AVX2-NEXT: ret
         %tmp1neg = sub <8 x i32> zeroinitializer, %a
@@ -138,12 +138,12 @@ define <8 x i32> @test7(<8 x i32> %a) nounwind {
 }
 
 define <16 x i16> @test8(<16 x i16> %a) nounwind {
-; SSSE3: test8:
+; SSSE3-LABEL: test8:
 ; SSSE3: pabsw
 ; SSSE3: pabsw
 ; SSSE3-NEXT: ret
 
-; AVX2: test8:
+; AVX2-LABEL: test8:
 ; AVX2: vpabsw {{.*}}%ymm
 ; AVX2-NEXT: ret
         %tmp1neg = sub <16 x i16> zeroinitializer, %a
@@ -153,12 +153,12 @@ define <16 x i16> @test8(<16 x i16> %a) nounwind {
 }
 
 define <32 x i8> @test9(<32 x i8> %a) nounwind {
-; SSSE3: test9:
+; SSSE3-LABEL: test9:
 ; SSSE3: pabsb
 ; SSSE3: pabsb
 ; SSSE3-NEXT: ret
 
-; AVX2: test9:
+; AVX2-LABEL: test9:
 ; AVX2: vpabsb {{.*}}%ymm
 ; AVX2-NEXT: ret
         %tmp1neg = sub <32 x i8> zeroinitializer, %a
@@ -168,12 +168,12 @@ define <32 x i8> @test9(<32 x i8> %a) nounwind {
 }
 
 define <8 x i32> @test10(<8 x i32> %a) nounwind {
-; SSSE3: test10:
+; SSSE3-LABEL: test10:
 ; SSSE3: pabsd
 ; SSSE3: pabsd
 ; SSSE3-NEXT: ret
 
-; AVX2: test10:
+; AVX2-LABEL: test10:
 ; AVX2: vpabsd {{.*}}%ymm
 ; AVX2-NEXT: ret
         %tmp1neg = sub <8 x i32> zeroinitializer, %a
diff --git a/llvm/test/CodeGen/X86/vselect-minmax.ll b/llvm/test/CodeGen/X86/vselect-minmax.ll
index cf654b6..25189f2 100644
--- a/llvm/test/CodeGen/X86/vselect-minmax.ll
+++ b/llvm/test/CodeGen/X86/vselect-minmax.ll
@@ -25,13 +25,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test1:
+; SSE4-LABEL: test1:
 ; SSE4: pminsb
 
-; AVX1: test1:
+; AVX1-LABEL: test1:
 ; AVX1: vpminsb
 
-; AVX2: test1:
+; AVX2-LABEL: test1:
 ; AVX2: vpminsb
 }
 
@@ -57,13 +57,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test2:
+; SSE4-LABEL: test2:
 ; SSE4: pminsb
 
-; AVX1: test2:
+; AVX1-LABEL: test2:
 ; AVX1: vpminsb
 
-; AVX2: test2:
+; AVX2-LABEL: test2:
 ; AVX2: vpminsb
 }
 
@@ -89,13 +89,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test3:
+; SSE4-LABEL: test3:
 ; SSE4: pmaxsb
 
-; AVX1: test3:
+; AVX1-LABEL: test3:
 ; AVX1: vpmaxsb
 
-; AVX2: test3:
+; AVX2-LABEL: test3:
 ; AVX2: vpmaxsb
 }
 
@@ -121,13 +121,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test4:
+; SSE4-LABEL: test4:
 ; SSE4: pmaxsb
 
-; AVX1: test4:
+; AVX1-LABEL: test4:
 ; AVX1: vpmaxsb
 
-; AVX2: test4:
+; AVX2-LABEL: test4:
 ; AVX2: vpmaxsb
 }
 
@@ -153,13 +153,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test5:
+; SSE2-LABEL: test5:
 ; SSE2: pminub
 
-; AVX1: test5:
+; AVX1-LABEL: test5:
 ; AVX1: vpminub
 
-; AVX2: test5:
+; AVX2-LABEL: test5:
 ; AVX2: vpminub
 }
 
@@ -185,13 +185,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test6:
+; SSE2-LABEL: test6:
 ; SSE2: pminub
 
-; AVX1: test6:
+; AVX1-LABEL: test6:
 ; AVX1: vpminub
 
-; AVX2: test6:
+; AVX2-LABEL: test6:
 ; AVX2: vpminub
 }
 
@@ -217,13 +217,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test7:
+; SSE2-LABEL: test7:
 ; SSE2: pmaxub
 
-; AVX1: test7:
+; AVX1-LABEL: test7:
 ; AVX1: vpmaxub
 
-; AVX2: test7:
+; AVX2-LABEL: test7:
 ; AVX2: vpmaxub
 }
 
@@ -249,13 +249,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test8:
+; SSE2-LABEL: test8:
 ; SSE2: pmaxub
 
-; AVX1: test8:
+; AVX1-LABEL: test8:
 ; AVX1: vpmaxub
 
-; AVX2: test8:
+; AVX2-LABEL: test8:
 ; AVX2: vpmaxub
 }
 
@@ -281,13 +281,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test9:
+; SSE2-LABEL: test9:
 ; SSE2: pminsw
 
-; AVX1: test9:
+; AVX1-LABEL: test9:
 ; AVX1: vpminsw
 
-; AVX2: test9:
+; AVX2-LABEL: test9:
 ; AVX2: vpminsw
 }
 
@@ -313,13 +313,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test10:
+; SSE2-LABEL: test10:
 ; SSE2: pminsw
 
-; AVX1: test10:
+; AVX1-LABEL: test10:
 ; AVX1: vpminsw
 
-; AVX2: test10:
+; AVX2-LABEL: test10:
 ; AVX2: vpminsw
 }
 
@@ -345,13 +345,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test11:
+; SSE2-LABEL: test11:
 ; SSE2: pmaxsw
 
-; AVX1: test11:
+; AVX1-LABEL: test11:
 ; AVX1: vpmaxsw
 
-; AVX2: test11:
+; AVX2-LABEL: test11:
 ; AVX2: vpmaxsw
 }
 
@@ -377,13 +377,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test12:
+; SSE2-LABEL: test12:
 ; SSE2: pmaxsw
 
-; AVX1: test12:
+; AVX1-LABEL: test12:
 ; AVX1: vpmaxsw
 
-; AVX2: test12:
+; AVX2-LABEL: test12:
 ; AVX2: vpmaxsw
 }
 
@@ -409,13 +409,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test13:
+; SSE4-LABEL: test13:
 ; SSE4: pminuw
 
-; AVX1: test13:
+; AVX1-LABEL: test13:
 ; AVX1: vpminuw
 
-; AVX2: test13:
+; AVX2-LABEL: test13:
 ; AVX2: vpminuw
 }
 
@@ -441,13 +441,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test14:
+; SSE4-LABEL: test14:
 ; SSE4: pminuw
 
-; AVX1: test14:
+; AVX1-LABEL: test14:
 ; AVX1: vpminuw
 
-; AVX2: test14:
+; AVX2-LABEL: test14:
 ; AVX2: vpminuw
 }
 
@@ -473,13 +473,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test15:
+; SSE4-LABEL: test15:
 ; SSE4: pmaxuw
 
-; AVX1: test15:
+; AVX1-LABEL: test15:
 ; AVX1: vpmaxuw
 
-; AVX2: test15:
+; AVX2-LABEL: test15:
 ; AVX2: vpmaxuw
 }
 
@@ -505,13 +505,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test16:
+; SSE4-LABEL: test16:
 ; SSE4: pmaxuw
 
-; AVX1: test16:
+; AVX1-LABEL: test16:
 ; AVX1: vpmaxuw
 
-; AVX2: test16:
+; AVX2-LABEL: test16:
 ; AVX2: vpmaxuw
 }
 
@@ -537,13 +537,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test17:
+; SSE4-LABEL: test17:
 ; SSE4: pminsd
 
-; AVX1: test17:
+; AVX1-LABEL: test17:
 ; AVX1: vpminsd
 
-; AVX2: test17:
+; AVX2-LABEL: test17:
 ; AVX2: vpminsd
 }
 
@@ -569,13 +569,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test18:
+; SSE4-LABEL: test18:
 ; SSE4: pminsd
 
-; AVX1: test18:
+; AVX1-LABEL: test18:
 ; AVX1: vpminsd
 
-; AVX2: test18:
+; AVX2-LABEL: test18:
 ; AVX2: vpminsd
 }
 
@@ -601,13 +601,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test19:
+; SSE4-LABEL: test19:
 ; SSE4: pmaxsd
 
-; AVX1: test19:
+; AVX1-LABEL: test19:
 ; AVX1: vpmaxsd
 
-; AVX2: test19:
+; AVX2-LABEL: test19:
 ; AVX2: vpmaxsd
 }
 
@@ -633,13 +633,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test20:
+; SSE4-LABEL: test20:
 ; SSE4: pmaxsd
 
-; AVX1: test20:
+; AVX1-LABEL: test20:
 ; AVX1: vpmaxsd
 
-; AVX2: test20:
+; AVX2-LABEL: test20:
 ; AVX2: vpmaxsd
 }
 
@@ -665,13 +665,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test21:
+; SSE4-LABEL: test21:
 ; SSE4: pminud
 
-; AVX1: test21:
+; AVX1-LABEL: test21:
 ; AVX1: vpminud
 
-; AVX2: test21:
+; AVX2-LABEL: test21:
 ; AVX2: vpminud
 }
 
@@ -697,13 +697,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test22:
+; SSE4-LABEL: test22:
 ; SSE4: pminud
 
-; AVX1: test22:
+; AVX1-LABEL: test22:
 ; AVX1: vpminud
 
-; AVX2: test22:
+; AVX2-LABEL: test22:
 ; AVX2: vpminud
 }
 
@@ -729,13 +729,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test23:
+; SSE4-LABEL: test23:
 ; SSE4: pmaxud
 
-; AVX1: test23:
+; AVX1-LABEL: test23:
 ; AVX1: vpmaxud
 
-; AVX2: test23:
+; AVX2-LABEL: test23:
 ; AVX2: vpmaxud
 }
 
@@ -761,13 +761,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test24:
+; SSE4-LABEL: test24:
 ; SSE4: pmaxud
 
-; AVX1: test24:
+; AVX1-LABEL: test24:
 ; AVX1: vpmaxud
 
-; AVX2: test24:
+; AVX2-LABEL: test24:
 ; AVX2: vpmaxud
 }
 
@@ -793,7 +793,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test25:
+; AVX2-LABEL: test25:
 ; AVX2: vpminsb
 }
 
@@ -819,7 +819,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test26:
+; AVX2-LABEL: test26:
 ; AVX2: vpminsb
 }
 
@@ -845,7 +845,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test27:
+; AVX2-LABEL: test27:
 ; AVX2: vpmaxsb
 }
 
@@ -871,7 +871,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test28:
+; AVX2-LABEL: test28:
 ; AVX2: vpmaxsb
 }
 
@@ -897,7 +897,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test29:
+; AVX2-LABEL: test29:
 ; AVX2: vpminub
 }
 
@@ -923,7 +923,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test30:
+; AVX2-LABEL: test30:
 ; AVX2: vpminub
 }
 
@@ -949,7 +949,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test31:
+; AVX2-LABEL: test31:
 ; AVX2: vpmaxub
 }
 
@@ -975,7 +975,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test32:
+; AVX2-LABEL: test32:
 ; AVX2: vpmaxub
 }
 
@@ -1001,7 +1001,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test33:
+; AVX2-LABEL: test33:
 ; AVX2: vpminsw
 }
 
@@ -1027,7 +1027,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test34:
+; AVX2-LABEL: test34:
 ; AVX2: vpminsw
 }
 
@@ -1053,7 +1053,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test35:
+; AVX2-LABEL: test35:
 ; AVX2: vpmaxsw
 }
 
@@ -1079,7 +1079,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test36:
+; AVX2-LABEL: test36:
 ; AVX2: vpmaxsw
 }
 
@@ -1105,7 +1105,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test37:
+; AVX2-LABEL: test37:
 ; AVX2: vpminuw
 }
 
@@ -1131,7 +1131,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test38:
+; AVX2-LABEL: test38:
 ; AVX2: vpminuw
 }
 
@@ -1157,7 +1157,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test39:
+; AVX2-LABEL: test39:
 ; AVX2: vpmaxuw
 }
 
@@ -1183,7 +1183,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test40:
+; AVX2-LABEL: test40:
 ; AVX2: vpmaxuw
 }
 
@@ -1209,7 +1209,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test41:
+; AVX2-LABEL: test41:
 ; AVX2: vpminsd
 }
 
@@ -1235,7 +1235,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test42:
+; AVX2-LABEL: test42:
 ; AVX2: vpminsd
 }
 
@@ -1261,7 +1261,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test43:
+; AVX2-LABEL: test43:
 ; AVX2: vpmaxsd
 }
 
@@ -1287,7 +1287,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test44:
+; AVX2-LABEL: test44:
 ; AVX2: vpmaxsd
 }
 
@@ -1313,7 +1313,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test45:
+; AVX2-LABEL: test45:
 ; AVX2: vpminud
 }
 
@@ -1339,7 +1339,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test46:
+; AVX2-LABEL: test46:
 ; AVX2: vpminud
 }
 
@@ -1365,7 +1365,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test47:
+; AVX2-LABEL: test47:
 ; AVX2: vpmaxud
 }
 
@@ -1391,7 +1391,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test48:
+; AVX2-LABEL: test48:
 ; AVX2: vpmaxud
 }
 
@@ -1417,13 +1417,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test49:
+; SSE4-LABEL: test49:
 ; SSE4: pmaxsb
 
-; AVX1: test49:
+; AVX1-LABEL: test49:
 ; AVX1: vpmaxsb
 
-; AVX2: test49:
+; AVX2-LABEL: test49:
 ; AVX2: vpmaxsb
 }
 
@@ -1449,13 +1449,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test50:
+; SSE4-LABEL: test50:
 ; SSE4: pmaxsb
 
-; AVX1: test50:
+; AVX1-LABEL: test50:
 ; AVX1: vpmaxsb
 
-; AVX2: test50:
+; AVX2-LABEL: test50:
 ; AVX2: vpmaxsb
 }
 
@@ -1481,13 +1481,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test51:
+; SSE4-LABEL: test51:
 ; SSE4: pminsb
 
-; AVX1: test51:
+; AVX1-LABEL: test51:
 ; AVX1: vpminsb
 
-; AVX2: test51:
+; AVX2-LABEL: test51:
 ; AVX2: vpminsb
 }
 
@@ -1513,13 +1513,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test52:
+; SSE4-LABEL: test52:
 ; SSE4: pminsb
 
-; AVX1: test52:
+; AVX1-LABEL: test52:
 ; AVX1: vpminsb
 
-; AVX2: test52:
+; AVX2-LABEL: test52:
 ; AVX2: vpminsb
 }
 
@@ -1545,13 +1545,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test53:
+; SSE2-LABEL: test53:
 ; SSE2: pmaxub
 
-; AVX1: test53:
+; AVX1-LABEL: test53:
 ; AVX1: vpmaxub
 
-; AVX2: test53:
+; AVX2-LABEL: test53:
 ; AVX2: vpmaxub
 }
 
@@ -1577,13 +1577,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test54:
+; SSE2-LABEL: test54:
 ; SSE2: pmaxub
 
-; AVX1: test54:
+; AVX1-LABEL: test54:
 ; AVX1: vpmaxub
 
-; AVX2: test54:
+; AVX2-LABEL: test54:
 ; AVX2: vpmaxub
 }
 
@@ -1609,13 +1609,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test55:
+; SSE2-LABEL: test55:
 ; SSE2: pminub
 
-; AVX1: test55:
+; AVX1-LABEL: test55:
 ; AVX1: vpminub
 
-; AVX2: test55:
+; AVX2-LABEL: test55:
 ; AVX2: vpminub
 }
 
@@ -1641,13 +1641,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test56:
+; SSE2-LABEL: test56:
 ; SSE2: pminub
 
-; AVX1: test56:
+; AVX1-LABEL: test56:
 ; AVX1: vpminub
 
-; AVX2: test56:
+; AVX2-LABEL: test56:
 ; AVX2: vpminub
 }
 
@@ -1673,13 +1673,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test57:
+; SSE2-LABEL: test57:
 ; SSE2: pmaxsw
 
-; AVX1: test57:
+; AVX1-LABEL: test57:
 ; AVX1: vpmaxsw
 
-; AVX2: test57:
+; AVX2-LABEL: test57:
 ; AVX2: vpmaxsw
 }
 
@@ -1705,13 +1705,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test58:
+; SSE2-LABEL: test58:
 ; SSE2: pmaxsw
 
-; AVX1: test58:
+; AVX1-LABEL: test58:
 ; AVX1: vpmaxsw
 
-; AVX2: test58:
+; AVX2-LABEL: test58:
 ; AVX2: vpmaxsw
 }
 
@@ -1737,13 +1737,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test59:
+; SSE2-LABEL: test59:
 ; SSE2: pminsw
 
-; AVX1: test59:
+; AVX1-LABEL: test59:
 ; AVX1: vpminsw
 
-; AVX2: test59:
+; AVX2-LABEL: test59:
 ; AVX2: vpminsw
 }
 
@@ -1769,13 +1769,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE2: test60:
+; SSE2-LABEL: test60:
 ; SSE2: pminsw
 
-; AVX1: test60:
+; AVX1-LABEL: test60:
 ; AVX1: vpminsw
 
-; AVX2: test60:
+; AVX2-LABEL: test60:
 ; AVX2: vpminsw
 }
 
@@ -1801,13 +1801,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test61:
+; SSE4-LABEL: test61:
 ; SSE4: pmaxuw
 
-; AVX1: test61:
+; AVX1-LABEL: test61:
 ; AVX1: vpmaxuw
 
-; AVX2: test61:
+; AVX2-LABEL: test61:
 ; AVX2: vpmaxuw
 }
 
@@ -1833,13 +1833,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test62:
+; SSE4-LABEL: test62:
 ; SSE4: pmaxuw
 
-; AVX1: test62:
+; AVX1-LABEL: test62:
 ; AVX1: vpmaxuw
 
-; AVX2: test62:
+; AVX2-LABEL: test62:
 ; AVX2: vpmaxuw
 }
 
@@ -1865,13 +1865,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test63:
+; SSE4-LABEL: test63:
 ; SSE4: pminuw
 
-; AVX1: test63:
+; AVX1-LABEL: test63:
 ; AVX1: vpminuw
 
-; AVX2: test63:
+; AVX2-LABEL: test63:
 ; AVX2: vpminuw
 }
 
@@ -1897,13 +1897,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test64:
+; SSE4-LABEL: test64:
 ; SSE4: pminuw
 
-; AVX1: test64:
+; AVX1-LABEL: test64:
 ; AVX1: vpminuw
 
-; AVX2: test64:
+; AVX2-LABEL: test64:
 ; AVX2: vpminuw
 }
 
@@ -1929,13 +1929,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test65:
+; SSE4-LABEL: test65:
 ; SSE4: pmaxsd
 
-; AVX1: test65:
+; AVX1-LABEL: test65:
 ; AVX1: vpmaxsd
 
-; AVX2: test65:
+; AVX2-LABEL: test65:
 ; AVX2: vpmaxsd
 }
 
@@ -1961,13 +1961,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test66:
+; SSE4-LABEL: test66:
 ; SSE4: pmaxsd
 
-; AVX1: test66:
+; AVX1-LABEL: test66:
 ; AVX1: vpmaxsd
 
-; AVX2: test66:
+; AVX2-LABEL: test66:
 ; AVX2: vpmaxsd
 }
 
@@ -1993,13 +1993,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test67:
+; SSE4-LABEL: test67:
 ; SSE4: pminsd
 
-; AVX1: test67:
+; AVX1-LABEL: test67:
 ; AVX1: vpminsd
 
-; AVX2: test67:
+; AVX2-LABEL: test67:
 ; AVX2: vpminsd
 }
 
@@ -2025,13 +2025,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test68:
+; SSE4-LABEL: test68:
 ; SSE4: pminsd
 
-; AVX1: test68:
+; AVX1-LABEL: test68:
 ; AVX1: vpminsd
 
-; AVX2: test68:
+; AVX2-LABEL: test68:
 ; AVX2: vpminsd
 }
 
@@ -2057,13 +2057,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test69:
+; SSE4-LABEL: test69:
 ; SSE4: pmaxud
 
-; AVX1: test69:
+; AVX1-LABEL: test69:
 ; AVX1: vpmaxud
 
-; AVX2: test69:
+; AVX2-LABEL: test69:
 ; AVX2: vpmaxud
 }
 
@@ -2089,13 +2089,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test70:
+; SSE4-LABEL: test70:
 ; SSE4: pmaxud
 
-; AVX1: test70:
+; AVX1-LABEL: test70:
 ; AVX1: vpmaxud
 
-; AVX2: test70:
+; AVX2-LABEL: test70:
 ; AVX2: vpmaxud
 }
 
@@ -2121,13 +2121,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test71:
+; SSE4-LABEL: test71:
 ; SSE4: pminud
 
-; AVX1: test71:
+; AVX1-LABEL: test71:
 ; AVX1: vpminud
 
-; AVX2: test71:
+; AVX2-LABEL: test71:
 ; AVX2: vpminud
 }
 
@@ -2153,13 +2153,13 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; SSE4: test72:
+; SSE4-LABEL: test72:
 ; SSE4: pminud
 
-; AVX1: test72:
+; AVX1-LABEL: test72:
 ; AVX1: vpminud
 
-; AVX2: test72:
+; AVX2-LABEL: test72:
 ; AVX2: vpminud
 }
 
@@ -2185,7 +2185,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test73:
+; AVX2-LABEL: test73:
 ; AVX2: vpmaxsb
 }
 
@@ -2211,7 +2211,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test74:
+; AVX2-LABEL: test74:
 ; AVX2: vpmaxsb
 }
 
@@ -2237,7 +2237,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test75:
+; AVX2-LABEL: test75:
 ; AVX2: vpminsb
 }
 
@@ -2263,7 +2263,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test76:
+; AVX2-LABEL: test76:
 ; AVX2: vpminsb
 }
 
@@ -2289,7 +2289,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test77:
+; AVX2-LABEL: test77:
 ; AVX2: vpmaxub
 }
 
@@ -2315,7 +2315,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test78:
+; AVX2-LABEL: test78:
 ; AVX2: vpmaxub
 }
 
@@ -2341,7 +2341,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test79:
+; AVX2-LABEL: test79:
 ; AVX2: vpminub
 }
 
@@ -2367,7 +2367,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test80:
+; AVX2-LABEL: test80:
 ; AVX2: vpminub
 }
 
@@ -2393,7 +2393,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test81:
+; AVX2-LABEL: test81:
 ; AVX2: vpmaxsw
 }
 
@@ -2419,7 +2419,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test82:
+; AVX2-LABEL: test82:
 ; AVX2: vpmaxsw
 }
 
@@ -2445,7 +2445,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test83:
+; AVX2-LABEL: test83:
 ; AVX2: vpminsw
 }
 
@@ -2471,7 +2471,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test84:
+; AVX2-LABEL: test84:
 ; AVX2: vpminsw
 }
 
@@ -2497,7 +2497,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test85:
+; AVX2-LABEL: test85:
 ; AVX2: vpmaxuw
 }
 
@@ -2523,7 +2523,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test86:
+; AVX2-LABEL: test86:
 ; AVX2: vpmaxuw
 }
 
@@ -2549,7 +2549,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test87:
+; AVX2-LABEL: test87:
 ; AVX2: vpminuw
 }
 
@@ -2575,7 +2575,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test88:
+; AVX2-LABEL: test88:
 ; AVX2: vpminuw
 }
 
@@ -2601,7 +2601,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test89:
+; AVX2-LABEL: test89:
 ; AVX2: vpmaxsd
 }
 
@@ -2627,7 +2627,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test90:
+; AVX2-LABEL: test90:
 ; AVX2: vpmaxsd
 }
 
@@ -2653,7 +2653,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test91:
+; AVX2-LABEL: test91:
 ; AVX2: vpminsd
 }
 
@@ -2679,7 +2679,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test92:
+; AVX2-LABEL: test92:
 ; AVX2: vpminsd
 }
 
@@ -2705,7 +2705,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test93:
+; AVX2-LABEL: test93:
 ; AVX2: vpmaxud
 }
 
@@ -2731,7 +2731,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test94:
+; AVX2-LABEL: test94:
 ; AVX2: vpmaxud
 }
 
@@ -2757,7 +2757,7 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test95:
+; AVX2-LABEL: test95:
 ; AVX2: vpminud
 }
 
@@ -2783,6 +2783,6 @@ vector.body:                                      ; preds = %vector.body, %vecto
 for.end:                                          ; preds = %vector.body
   ret void
 
-; AVX2: test96:
+; AVX2-LABEL: test96:
 ; AVX2: vpminud
 }
diff --git a/llvm/test/CodeGen/X86/x86-64-and-mask.ll b/llvm/test/CodeGen/X86/x86-64-and-mask.ll
index 8e8f670..1de406c 100644
--- a/llvm/test/CodeGen/X86/x86-64-and-mask.ll
+++ b/llvm/test/CodeGen/X86/x86-64-and-mask.ll
@@ -4,7 +4,7 @@ target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f3
 target triple = "x86_64-apple-darwin8"
 
 ; This should be a single mov, not a load of immediate + andq.
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: movl %edi, %eax
 
 define i64 @test(i64 %x) nounwind {
diff --git a/llvm/test/CodeGen/X86/x86-64-psub.ll b/llvm/test/CodeGen/X86/x86-64-psub.ll
index 7869a80..be09a4f 100644
--- a/llvm/test/CodeGen/X86/x86-64-psub.ll
+++ b/llvm/test/CodeGen/X86/x86-64-psub.ll
@@ -26,7 +26,7 @@ entry:
   ret i64 %retval.0.extract.i15
 }
 
-; CHECK: test_psubb:
+; CHECK-LABEL: test_psubb:
 ; CHECK:   callq getFirstParam
 ; CHECK:   callq getSecondParam
 ; CHECK:   movd %rax, [[PARAM2:%[a-z0-9]+]]
@@ -53,7 +53,7 @@ entry:
   ret i64 %retval.0.extract.i15
 }
 
-; CHECK: test_psubw:
+; CHECK-LABEL: test_psubw:
 ; CHECK:   callq getFirstParam
 ; CHECK:   callq getSecondParam
 ; CHECK:   movd %rax, [[PARAM2:%[a-z0-9]+]]
@@ -81,7 +81,7 @@ entry:
   ret i64 %retval.0.extract.i15
 }
 
-; CHECK: test_psubd:
+; CHECK-LABEL: test_psubd:
 ; CHECK:   callq getFirstParam
 ; CHECK:   callq getSecondParam
 ; CHECK:   movd %rax, [[PARAM2:%[a-z0-9]+]]
@@ -108,7 +108,7 @@ entry:
   ret i64 %retval.0.extract.i15
 }
 
-; CHECK: test_psubsb:
+; CHECK-LABEL: test_psubsb:
 ; CHECK:   callq getFirstParam
 ; CHECK:   callq getSecondParam
 ; CHECK:   movd %rax, [[PARAM2:%[a-z0-9]+]]
@@ -135,7 +135,7 @@ entry:
   ret i64 %retval.0.extract.i15
 }
 
-; CHECK: test_psubswv:
+; CHECK-LABEL: test_psubswv:
 ; CHECK:   callq getFirstParam
 ; CHECK:   callq getSecondParam
 ; CHECK:   movd %rax, [[PARAM2:%[a-z0-9]+]]
@@ -162,7 +162,7 @@ entry:
   ret i64 %retval.0.extract.i15
 }
 
-; CHECK: test_psubusbv:
+; CHECK-LABEL: test_psubusbv:
 ; CHECK:   callq getFirstParam
 ; CHECK:   callq getSecondParam
 ; CHECK:   movd %rax, [[PARAM2:%[a-z0-9]+]]
@@ -189,7 +189,7 @@ entry:
   ret i64 %retval.0.extract.i15
 }
 
-; CHECK: test_psubuswv:
+; CHECK-LABEL: test_psubuswv:
 ; CHECK:   callq getFirstParam
 ; CHECK:   callq getSecondParam
 ; CHECK:   movd %rax, [[PARAM2:%[a-z0-9]+]]
diff --git a/llvm/test/CodeGen/X86/xor.ll b/llvm/test/CodeGen/X86/xor.ll
index 574bb78..b56ce0f 100644
--- a/llvm/test/CodeGen/X86/xor.ll
+++ b/llvm/test/CodeGen/X86/xor.ll
@@ -7,7 +7,7 @@ define <4 x i32> @test1() nounwind {
 	%tmp = xor <4 x i32> undef, undef
 	ret <4 x i32> %tmp
         
-; X32: test1:
+; X32-LABEL: test1:
 ; X32:	xorps	%xmm0, %xmm0
 ; X32:	ret
 }
@@ -16,7 +16,7 @@ define <4 x i32> @test1() nounwind {
 define i32 @test2() nounwind{
 	%tmp = xor i32 undef, undef
 	ret i32 %tmp
-; X32: test2:
+; X32-LABEL: test2:
 ; X32:	xorl	%eax, %eax
 ; X32:	ret
 }
@@ -28,13 +28,13 @@ entry:
         %tmp4 = lshr i32 %tmp3, 1
         ret i32 %tmp4
         
-; X64: test3:
+; X64-LABEL: test3:
 ; X64:	notl
 ; X64:	andl
 ; X64:	shrl
 ; X64:	ret
 
-; X32: test3:
+; X32-LABEL: test3:
 ; X32: 	movl	8(%esp), %eax
 ; X32: 	notl	%eax
 ; X32: 	andl	4(%esp), %eax
@@ -57,10 +57,10 @@ bb:
 bb12:
 	ret i32 %tmp3
         
-; X64: test4:
+; X64-LABEL: test4:
 ; X64:    notl	[[REG:%[a-z]+]]
 ; X64:    andl	{{.*}}[[REG]]
-; X32: test4:
+; X32-LABEL: test4:
 ; X32:    notl	[[REG:%[a-z]+]]
 ; X32:    andl	{{.*}}[[REG]]
 }
@@ -79,10 +79,10 @@ bb:
 	br i1 %tmp10, label %bb12, label %bb
 bb12:
 	ret i16 %tmp3
-; X64: test5:
+; X64-LABEL: test5:
 ; X64:    notl	[[REG:%[a-z]+]]
 ; X64:    andl	{{.*}}[[REG]]
-; X32: test5:
+; X32-LABEL: test5:
 ; X32:    notl	[[REG:%[a-z]+]]
 ; X32:    andl	{{.*}}[[REG]]
 }
@@ -101,10 +101,10 @@ bb:
 	br i1 %tmp10, label %bb12, label %bb
 bb12:
 	ret i8 %tmp3
-; X64: test6:
+; X64-LABEL: test6:
 ; X64:    notb	[[REG:%[a-z]+]]
 ; X64:    andb	{{.*}}[[REG]]
-; X32: test6:
+; X32-LABEL: test6:
 ; X32:    notb	[[REG:%[a-z]+]]
 ; X32:    andb	{{.*}}[[REG]]
 }
@@ -123,10 +123,10 @@ bb:
 	br i1 %tmp10, label %bb12, label %bb
 bb12:
 	ret i32 %tmp3
-; X64: test7:
+; X64-LABEL: test7:
 ; X64:    xorl	$2147483646, [[REG:%[a-z]+]]
 ; X64:    andl	{{.*}}[[REG]]
-; X32: test7:
+; X32-LABEL: test7:
 ; X32:    xorl	$2147483646, [[REG:%[a-z]+]]
 ; X32:    andl	{{.*}}[[REG]]
 }
@@ -137,9 +137,9 @@ entry:
   %t1 = sub i32 0, %a
   %t2 = add i32 %t1, -1
   ret i32 %t2
-; X64: test8:
+; X64-LABEL: test8:
 ; X64:   notl {{%eax|%edi|%ecx}}
-; X32: test8:
+; X32-LABEL: test8:
 ; X32:   notl %eax
 }
 
@@ -147,10 +147,10 @@ define i32 @test9(i32 %a) nounwind {
   %1 = and i32 %a, 4096
   %2 = xor i32 %1, 4096
   ret i32 %2
-; X64: test9:
+; X64-LABEL: test9:
 ; X64:    notl	[[REG:%[a-z]+]]
 ; X64:    andl	{{.*}}[[REG:%[a-z]+]]
-; X32: test9:
+; X32-LABEL: test9:
 ; X32:    notl	[[REG:%[a-z]+]]
 ; X32:    andl	{{.*}}[[REG:%[a-z]+]]
 }
@@ -160,8 +160,8 @@ define <4 x i32> @test10(<4 x i32> %a) nounwind {
   %1 = and <4 x i32> %a, <i32 4096, i32 4096, i32 4096, i32 4096>
   %2 = xor <4 x i32> %1, <i32 4096, i32 4096, i32 4096, i32 4096>
   ret <4 x i32> %2
-; X64: test10:
+; X64-LABEL: test10:
 ; X64:    andnps
-; X32: test10:
+; X32-LABEL: test10:
 ; X32:    andnps
 }
diff --git a/llvm/test/CodeGen/XCore/fneg.ll b/llvm/test/CodeGen/XCore/fneg.ll
index d442a19..67ab619 100644
--- a/llvm/test/CodeGen/XCore/fneg.ll
+++ b/llvm/test/CodeGen/XCore/fneg.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=xcore | FileCheck %s
 define i1 @test(double %F) nounwind {
 entry:
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: xor
 	%0 = fsub double -0.000000e+00, %F
 	%1 = fcmp olt double 0.000000e+00, %0
diff --git a/llvm/test/CodeGen/XCore/getid.ll b/llvm/test/CodeGen/XCore/getid.ll
index ec46071..da80e10 100644
--- a/llvm/test/CodeGen/XCore/getid.ll
+++ b/llvm/test/CodeGen/XCore/getid.ll
@@ -2,7 +2,7 @@
 declare i32 @llvm.xcore.getid()
 
 define i32 @test() {
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: get r11, id
 ; CHECK-NEXT: mov r0, r11
 	%result = call i32 @llvm.xcore.getid()
diff --git a/llvm/test/CodeGen/XCore/resources.ll b/llvm/test/CodeGen/XCore/resources.ll
index 8f00fed..74511ad 100644
--- a/llvm/test/CodeGen/XCore/resources.ll
+++ b/llvm/test/CodeGen/XCore/resources.ll
@@ -227,14 +227,14 @@ define i32 @endin(i8 addrspace(1)* %r) {
 }
 
 define i32 @testct(i8 addrspace(1)* %r) {
-; CHECK: testct:
+; CHECK-LABEL: testct:
 ; CHECK: testct r0, res[r0]
 	%result = call i32 @llvm.xcore.testct.p1i8(i8 addrspace(1)* %r)
 	ret i32 %result
 }
 
 define i32 @testwct(i8 addrspace(1)* %r) {
-; CHECK: testwct:
+; CHECK-LABEL: testwct:
 ; CHECK: testwct r0, res[r0]
 	%result = call i32 @llvm.xcore.testwct.p1i8(i8 addrspace(1)* %r)
 	ret i32 %result
diff --git a/llvm/test/CodeGen/XCore/trap.ll b/llvm/test/CodeGen/XCore/trap.ll
index eb71cb6..ef0dfd6 100644
--- a/llvm/test/CodeGen/XCore/trap.ll
+++ b/llvm/test/CodeGen/XCore/trap.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=xcore | FileCheck %s
 define i32 @test() noreturn nounwind  {
 entry:
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: ldc
 ; CHECK: ecallf
 	tail call void @llvm.trap( )
-- 
2.7.4