From f777aa3f4c21ca96aa06a1a1b1eac0c900013c32 Mon Sep 17 00:00:00 2001 From: Geng Xiujun Date: Mon, 14 May 2012 16:02:49 +0800 Subject: [PATCH] gfx-display: optimize gfx late resume code for DVx BZ: 33421 remove redundant code in mipi encoder mode set, and make some optimiaztions to make gfx late resume faster for DVx. with this patch, time consumption of gfx_late_resume is almost the same with PRx. Change-Id: Ied6e1ade9874139bd69d8dbab1728f5516632151 Signed-off-by: Geng Xiujun Reviewed-on: http://android.intel.com:8080/48654 Reviewed-by: Xu, Randy Tested-by: Tong, BoX Tested-by: Xu, Randy Reviewed-by: Imberton, Guilhem Reviewed-by: buildbot Tested-by: buildbot --- drivers/staging/mrst/drv/mdfld_dsi_dpi.c | 91 ++++++++++++++---------- drivers/staging/mrst/drv/mdfld_dsi_lvds_bridge.c | 14 ++-- drivers/staging/mrst/drv/psb_intel_display2.c | 5 ++ drivers/staging/mrst/drv/psb_powermgmt.c | 5 ++ 4 files changed, 74 insertions(+), 41 deletions(-) diff --git a/drivers/staging/mrst/drv/mdfld_dsi_dpi.c b/drivers/staging/mrst/drv/mdfld_dsi_dpi.c index c0dbce8..128d138 100644 --- a/drivers/staging/mrst/drv/mdfld_dsi_dpi.c +++ b/drivers/staging/mrst/drv/mdfld_dsi_dpi.c @@ -1332,17 +1332,13 @@ void mdfld_dsi_dpi_controller_init(struct mdfld_dsi_config * dsi_config, int pip /*TODO: figure out how to setup these registers*/ #ifdef CONFIG_SUPPORT_TOSHIBA_MIPI_LVDS_BRIDGE - REG_WRITE((MIPIA_DPHY_PARAM_REG + reg_offset), 0x2A0c6008); + REG_WRITE((MIPIA_DPHY_PARAM_REG + reg_offset), 0x150C340F); #else REG_WRITE((MIPIA_DPHY_PARAM_REG + reg_offset), 0x150c3408); #endif REG_WRITE((MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG + reg_offset), (0xa << 16) | 0x14); #endif -#ifdef CONFIG_SUPPORT_TOSHIBA_MIPI_LVDS_BRIDGE - dsi_lvds_set_bridge_reset_state(0); /* Pull High Reset */ -#endif - /*set device ready*/ REG_FLD_MOD((DEVICE_READY_REG + reg_offset), 1, 0, 0); } @@ -2305,7 +2301,6 @@ static void mdfld_mipi_config(struct mdfld_dsi_config *dsi_config, int pipe) REG_WRITE((MIPIA_DPHY_PARAM_REG + reg_offset), 0x150A600F); /*0xB080 */ - REG_WRITE((MIPIA_VIDEO_MODE_FORMAT_REG + reg_offset), 0x0000000F); /*0xB058 */ @@ -2409,6 +2404,12 @@ void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder, u32 pipeconf = dev_priv->pipeconf; u32 dspcntr = dev_priv->dspcntr; u32 mipi = MIPI_PORT_EN | PASS_FROM_SPHY_TO_AFE; + int retry = 0; + +#ifdef CONFIG_SUPPORT_TOSHIBA_MIPI_LVDS_BRIDGE + struct mdfld_dsi_hw_context *ctx = NULL; + ctx = &dsi_config->dsi_hw_context; +#endif /* The bit defination changed from PNW_A0 -> B0 and forward, * Only for PNW_A0 that we need to set FLOPPED_HSTX @@ -2442,33 +2443,44 @@ void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder, /* The following logic is required to do reset the bridge and configure. */ /* This also start DSI clock at 200MHz */ { - int timeout = 0; - - dsi_lvds_set_bridge_reset_state(0); /*Pull High Reset */ - dsi_lvds_toshiba_bridge_panel_on(dev); - udelay(100); - /* Now start the DSI clock */ - REG_WRITE(MRST_DPLL_A, 0x00); /*0xF014 */ - REG_WRITE(MRST_FPA0, 0xC1); /*0xF040 */ - REG_WRITE(MRST_DPLL_A, 0x00800000); /*0xF014 */ - udelay(500); - REG_WRITE(MRST_DPLL_A, 0x80800000); /*0xF014 */ - /*Wait for DSI PLL to lock */ - while ((timeout < 20000) && !(REG_READ(pipeconf_reg) & PIPECONF_DSIPLL_LOCK)) { - udelay(150); - timeout++; - } - if (timeout == 20000) - printk(KERN_ALERT "[DISPLAY] DSI PLL Locked timeout\n"); - REG_WRITE((MIPIA_DPHY_PARAM_REG + reg_offset), 0x2A0c6008); /*0xB080 */ + int timeout = 0; + u32 val = 0; + + if (ctx == NULL) { + pr_err("%s: hw contex is NULL!!\n", __func__); + goto mode_set_err; + } - mipi_set_properties(dsi_config, pipe); - mdfld_mipi_config(dsi_config, pipe); - mdfld_set_pipe_timing(dsi_config, pipe); + dsi_lvds_set_bridge_reset_state(0); /*Pull High Reset */ + dsi_lvds_toshiba_bridge_panel_on(dev); - REG_WRITE(VGACNTRL, 0x80000000); /*0x71400 */ - REG_WRITE(DEVICE_READY_REG, 0x00000001); /*0xB000 */ - REG_WRITE(mipi_reg, 0x80010000); /*0x61190 */ + /* Now start the DSI clock */ + REG_WRITE(MRST_DPLL_A, 0x0); + REG_WRITE(MRST_FPA0, 0x0); + REG_WRITE(MRST_FPA0, ctx->fp); + REG_WRITE(MRST_DPLL_A, ((ctx->dpll) & ~BIT30)); + + /* per spec of display controller, before enable VCO, need wait + * 0.5us, here wait 1us */ + udelay(1); + val = REG_READ(MRST_DPLL_A); + REG_WRITE(MRST_DPLL_A, (val | BIT31)); + + /*Wait for DSI PLL to lock */ + while ((timeout < 20000) && + !(REG_READ(pipeconf_reg) & PIPECONF_DSIPLL_LOCK)) { + udelay(3); + timeout++; + } + + if (timeout == 20000) + pr_warn("%s: DSI PLL Locked timeout\n", __func__); + + mipi_set_properties(dsi_config, pipe); + mdfld_set_pipe_timing(dsi_config, pipe); + + /* enable mipi port */ + REG_WRITE(mipi_reg, 0x80010000); } #else /*set up mipi port FIXME: do at init time */ @@ -2499,16 +2511,20 @@ void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder, REG_WRITE(pipeconf_reg, pipeconf); REG_READ(pipeconf_reg); + /*Wait for pipe enabling*/ + retry = 10000; + while (--retry && !(REG_READ(pipeconf_reg) & BIT30)) + udelay(3); + + if (!retry) { + pr_err("%s: failed to enable pipe!!\n", __func__); + goto mode_set_err; + } + /*set up display plane*/ REG_WRITE(dspcntr_reg, dspcntr); REG_READ(dspcntr_reg); - msleep(20); /* FIXME: this should wait for vblank */ - - PSB_DEBUG_ENTRY("State %x, power %d\n", - REG_READ(MIPIA_INTR_STAT_REG + reg_offset), - dpi_output->panel_on); - if (get_panel_type(dev, pipe) == TMD_VID) { #ifdef CONFIG_SUPPORT_TOSHIBA_MIPI_LVDS_BRIDGE mdfld_dsi_dpi_turn_on(dpi_output, pipe); @@ -2525,6 +2541,7 @@ void mdfld_dsi_dpi_mode_set(struct drm_encoder *encoder, dsi_debug_MIPI_reg(dev); #endif +mode_set_err: ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND); #else /** diff --git a/drivers/staging/mrst/drv/mdfld_dsi_lvds_bridge.c b/drivers/staging/mrst/drv/mdfld_dsi_lvds_bridge.c index 121795b..6abb375 100644 --- a/drivers/staging/mrst/drv/mdfld_dsi_lvds_bridge.c +++ b/drivers/staging/mrst/drv/mdfld_dsi_lvds_bridge.c @@ -413,15 +413,19 @@ void dsi_lvds_set_bridge_reset_state(int state) if (state) { if (gpio_direction_output(GPIO_MIPI_BRIDGE_RESET, 0)) gpio_set_value_cansleep(GPIO_MIPI_BRIDGE_RESET, 0); - msleep(10); + /* FIXME: + * per spec, the min period of reset signal is 50 nano secs, + * but no detailed description. Here delay 1ms for safe. + */ + mdelay(1); } else { if (gpio_direction_output(GPIO_MIPI_BRIDGE_RESET, 0)) gpio_set_value_cansleep(GPIO_MIPI_BRIDGE_RESET, 0); /*Pull MIPI Bridge reset pin to Low */ - msleep(20); + mdelay(1); if (gpio_direction_output(GPIO_MIPI_BRIDGE_RESET, 1)) gpio_set_value_cansleep(GPIO_MIPI_BRIDGE_RESET, 1); /*Pull MIPI Bridge reset pin to High */ - msleep(40); + mdelay(1); } } @@ -677,7 +681,9 @@ void dsi_lvds_bridge_get_display_params(struct drm_display_mode *mode) mode->vsync_start = mode->vdisplay + 14; mode->vsync_end = mode->vsync_start + 10; mode->vtotal = mode->vsync_end + 14; - mode->clock = 33324; + mode->vrefresh = 60; + mode->clock = mode->vrefresh * mode->htotal * mode->vtotal / 1000; + printk(KERN_INFO "[DISPLAY]: hdisplay(w) is %d\n", mode->hdisplay); printk(KERN_INFO "[DISPLAY]: vdisplay(h) is %d\n", mode->vdisplay); printk(KERN_INFO "[DISPLAY]: HSS is %d\n", mode->hsync_start); diff --git a/drivers/staging/mrst/drv/psb_intel_display2.c b/drivers/staging/mrst/drv/psb_intel_display2.c index db35347..d50acff 100755 --- a/drivers/staging/mrst/drv/psb_intel_display2.c +++ b/drivers/staging/mrst/drv/psb_intel_display2.c @@ -2303,6 +2303,11 @@ static int mdfld_crtc_mode_set(struct drm_crtc *crtc, timeout ++; } +#ifdef CONFIG_SUPPORT_TOSHIBA_MIPI_LVDS_BRIDGE + ctx->dpll = dpll; + ctx->fp = fp; +#endif + if (is_mipi) { if (get_panel_type(dev, pipe) == GI_SONY_CMD) mdfld_gi_sony_power_on(mipi_encoder); diff --git a/drivers/staging/mrst/drv/psb_powermgmt.c b/drivers/staging/mrst/drv/psb_powermgmt.c index bf25ad3..3007660 100644 --- a/drivers/staging/mrst/drv/psb_powermgmt.c +++ b/drivers/staging/mrst/drv/psb_powermgmt.c @@ -1220,6 +1220,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) /*make sure VGA plane is off. it initializes to on after reset!*/ PSB_WVDC32(0x80000000, VGACNTRL); +#ifndef CONFIG_SUPPORT_TOSHIBA_MIPI_LVDS_BRIDGE dpll = PSB_RVDC32(dpll_reg); if (!(dpll & DPLL_VCO_ENABLE)) { @@ -1261,6 +1262,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) return -EINVAL; } } +#endif /* Restore mode */ PSB_WVDC32(htot_val, htot_reg); @@ -1288,6 +1290,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) PSB_WVDC32(dev_priv->saveHDMIB_CONTROL, HDMIB_CONTROL); } else { +#ifndef CONFIG_SUPPORT_TOSHIBA_MIPI_LVDS_BRIDGE /*set up pipe related registers*/ PSB_WVDC32(mipi_val, mipi_reg); @@ -1296,6 +1299,7 @@ static int mdfld_restore_display_registers(struct drm_device *dev, int pipe) else msleep(20); +#endif /*TODO: remove MIPI restore code later*/ /*dsi_config->dvr_ic_inited = 0;*/ /*mdfld_dsi_tmd_drv_ic_init(dsi_config, pipe);*/ @@ -1941,6 +1945,7 @@ static void gfx_late_resume(struct early_suspend *h) struct drm_encoder_helper_funcs *enc_funcs; struct drm_crtc *crtc = NULL; u32 dspcntr_val; + #ifdef OSPM_GFX_DPK printk(KERN_ALERT "\ngfx_late_resume\n"); #endif -- 2.7.4