From f724f95542b2f7029608e9689a6d8cd386b5b42c Mon Sep 17 00:00:00 2001 From: Nanley Chery Date: Tue, 1 Feb 2022 14:02:16 -0500 Subject: [PATCH] intel/isl: Add more PRM text for HiZ/STC requirement Add text describing why HierarchicalDepthBufferEnable must be set along with SeparateStencilBufferEnable. Reviewed-by: Lionel Landwerlin Reviewed-by: Kenneth Graunke Part-of: --- src/intel/isl/isl_emit_depth_stencil.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/src/intel/isl/isl_emit_depth_stencil.c b/src/intel/isl/isl_emit_depth_stencil.c index 887d5e1..7bd6375c 100644 --- a/src/intel/isl/isl_emit_depth_stencil.c +++ b/src/intel/isl/isl_emit_depth_stencil.c @@ -152,14 +152,17 @@ isl_genX(emit_depth_stencil_hiz_s)(const struct isl_device *dev, void *batch, info->stencil_surf && info->stencil_surf->format == ISL_FORMAT_R8_UINT; if (separate_stencil || info->hiz_usage == ISL_AUX_USAGE_HIZ) { assert(ISL_DEV_USE_SEPARATE_STENCIL(dev)); - db.SeparateStencilBufferEnable = true; - db.HierarchicalDepthBufferEnable = true; - - /* From the IronLake PRM, Vol 2 Part 1, - * 3DSTATE_DEPTH_BUFFER::Tiled Surface, + /* From the IronLake PRM, Vol 2 Part 1: * + * 3DSTATE_DEPTH_BUFFER::Separate Stencil Buffer Enable + * If this field is enabled, Hierarchical Depth Buffer Enable must + * also be enabled. + * + * 3DSTATE_DEPTH_BUFFER::Tiled Surface * When Hierarchical Depth Buffer is enabled, this bit must be set. */ + db.SeparateStencilBufferEnable = true; + db.HierarchicalDepthBufferEnable = true; db.TiledSurface = true; } #endif -- 2.7.4