From f693b94d2fac4590475a4ff95deab3c639cc14b4 Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 28 Jul 2021 14:26:32 +0200 Subject: [PATCH] radv: reduce number of emitted DWORDS for contiguous context registers radeon_set_context_reg() emits 3 DWORDS, while radeon_set_context_reg_seq() + 2 values only needs 4 DWORDS. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_cmd_buffer.c | 5 +++-- src/amd/vulkan/radv_pipeline.c | 18 +++++++++++------- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index fa39572..3e9f128 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1465,8 +1465,9 @@ radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer) { struct radv_dynamic_state *d = &cmd_buffer->state.dynamic; - radeon_set_context_reg(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, fui(d->depth_bounds.min)); - radeon_set_context_reg(cmd_buffer->cs, R_028024_DB_DEPTH_BOUNDS_MAX, fui(d->depth_bounds.max)); + radeon_set_context_reg_seq(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, 2); + radeon_emit(cmd_buffer->cs, fui(d->depth_bounds.min)); + radeon_emit(cmd_buffer->cs, fui(d->depth_bounds.max)); } static void diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index a756d89..0c1ddc1 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -4204,8 +4204,10 @@ radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs, } radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control); - radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override); - radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2); + + radeon_set_context_reg_seq(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, 2); + radeon_emit(ctx_cs, db_render_override); + radeon_emit(ctx_cs, db_render_override2); } static void @@ -4275,10 +4277,12 @@ radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs, radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]); radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa); - radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0); - radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1); radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config); + radeon_set_context_reg_seq(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, 2); + radeon_emit(ctx_cs, ms->pa_sc_mode_cntl_0); + radeon_emit(ctx_cs, ms->pa_sc_mode_cntl_1); + /* The exclusion bits can be set to improve rasterization efficiency * if no sample lies on the pixel boundary (-8 sample offset). It's * currently always TRUE because the driver doesn't support 16 samples. @@ -4974,9 +4978,9 @@ radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs, struct rade radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL, radv_compute_db_shader_control(pipeline->device, pipeline, ps)); - radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA, ps->config.spi_ps_input_ena); - - radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR, ps->config.spi_ps_input_addr); + radeon_set_context_reg_seq(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA, 2); + radeon_emit(ctx_cs, ps->config.spi_ps_input_ena); + radeon_emit(ctx_cs, ps->config.spi_ps_input_addr); radeon_set_context_reg( ctx_cs, R_0286D8_SPI_PS_IN_CONTROL, -- 2.7.4