From f66281c7fb7a9e85dbef36f2661bd08254fcfe34 Mon Sep 17 00:00:00 2001 From: =?utf8?q?Timur=20Krist=C3=B3f?= Date: Wed, 26 Apr 2023 14:27:10 +0200 Subject: [PATCH] amd: Add and implement gs_wave_id sysval. MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Contains a global wave ID of legacy GS waves. Signed-off-by: Timur Kristóf Reviewed-by: Qiang Yu Reviewed-by: Rhys Perry Reviewed-by: Marek Olšák Part-of: --- src/amd/compiler/aco_instruction_selection.cpp | 12 ++++++++++++ src/amd/llvm/ac_nir_to_llvm.c | 9 +++++++++ src/compiler/nir/nir_divergence_analysis.c | 1 + src/compiler/nir/nir_intrinsics.py | 2 ++ 4 files changed, 24 insertions(+) diff --git a/src/amd/compiler/aco_instruction_selection.cpp b/src/amd/compiler/aco_instruction_selection.cpp index 328b565..aafd51a 100644 --- a/src/amd/compiler/aco_instruction_selection.cpp +++ b/src/amd/compiler/aco_instruction_selection.cpp @@ -9018,6 +9018,18 @@ visit_intrinsic(isel_context* ctx, nir_intrinsic_instr* instr) bld.sopp(aco_opcode::s_sendmsg, bld.m0(m0_content), -1, imm); break; } + case nir_intrinsic_load_gs_wave_id_amd: { + Temp dst = get_ssa_temp(ctx, &instr->dest.ssa); + if (ctx->args->merged_wave_info.used) + bld.pseudo(aco_opcode::p_extract, Definition(dst), bld.def(s1, scc), + get_arg(ctx, ctx->args->merged_wave_info), Operand::c32(2u), + Operand::c32(8u), Operand::zero()); + else if (ctx->args->gs_wave_id.used) + bld.copy(Definition(dst), get_arg(ctx, ctx->args->gs_wave_id)); + else + unreachable("Shader doesn't have GS wave ID."); + break; + } case nir_intrinsic_is_subgroup_invocation_lt_amd: { Temp src = bld.as_uniform(get_ssa_temp(ctx, instr->src[0].ssa)); bld.copy(Definition(get_ssa_temp(ctx, &instr->dest.ssa)), lanecount_to_mask(ctx, src)); diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c index 92e7795..ce6a97e 100644 --- a/src/amd/llvm/ac_nir_to_llvm.c +++ b/src/amd/llvm/ac_nir_to_llvm.c @@ -3848,6 +3848,15 @@ static bool visit_intrinsic(struct ac_nir_context *ctx, nir_intrinsic_instr *ins ac_build_sendmsg(&ctx->ac, imm, m0_content); break; } + case nir_intrinsic_load_gs_wave_id_amd: { + if (ctx->args->merged_wave_info.used) + result = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 16, 8); + else if (ctx->args->gs_wave_id.used) + result = ac_get_arg(&ctx->ac, ctx->args->gs_wave_id); + else + unreachable("Shader doesn't have GS wave ID."); + break; + } case nir_intrinsic_load_tess_coord: { LLVMValueRef coord[] = { ctx->abi->tes_u_replaced ? ctx->abi->tes_u_replaced : ac_get_arg(&ctx->ac, ctx->args->tes_u), diff --git a/src/compiler/nir/nir_divergence_analysis.c b/src/compiler/nir/nir_divergence_analysis.c index ebc7ae0..2197d16 100644 --- a/src/compiler/nir/nir_divergence_analysis.c +++ b/src/compiler/nir/nir_divergence_analysis.c @@ -199,6 +199,7 @@ visit_intrinsic(nir_shader *shader, nir_intrinsic_instr *instr) case nir_intrinsic_load_num_vertices_per_primitive_amd: case nir_intrinsic_load_streamout_buffer_amd: case nir_intrinsic_load_ordered_id_amd: + case nir_intrinsic_load_gs_wave_id_amd: case nir_intrinsic_load_provoking_vtx_in_prim_amd: case nir_intrinsic_load_lds_ngg_scratch_base_amd: case nir_intrinsic_load_lds_ngg_gs_out_vertex_base_amd: diff --git a/src/compiler/nir/nir_intrinsics.py b/src/compiler/nir/nir_intrinsics.py index 68e1a58..f7dc238 100644 --- a/src/compiler/nir/nir_intrinsics.py +++ b/src/compiler/nir/nir_intrinsics.py @@ -1460,6 +1460,8 @@ system_value("prim_xfb_query_enabled_amd", dest_comp=1, bit_sizes=[1]) # Merged wave info. Bits 0-7 are the ES thread count, 8-15 are the GS thread count, 16-24 is the # GS Wave ID, 24-27 is the wave index in the workgroup, and 28-31 is the workgroup size in waves. system_value("merged_wave_info_amd", dest_comp=1) +# Global ID for GS waves on GCN/RDNA legacy GS. +system_value("gs_wave_id_amd", dest_comp=1) # Whether the shader should clamp vertex color outputs to [0, 1]. system_value("clamp_vertex_color_amd", dest_comp=1, bit_sizes=[1]) # Whether the shader should cull front facing triangles. -- 2.7.4