From f6406ac5d65c7f0da127a4c08401278e9c18a1bf Mon Sep 17 00:00:00 2001 From: Chandler Carruth Date: Sat, 26 Jul 2014 02:14:54 +0000 Subject: [PATCH] [x86] Revert r214007: Fix PR20355 ... The clever way to implement signed multiplication with unsigned *is already implemented* and tested and working correctly. The bug is somewhere else. Re-investigating. This will teach me to not scroll far enough to read the code that did what I thought needed to be done. llvm-svn: 214009 --- llvm/lib/Target/X86/X86ISelLowering.cpp | 8 +++----- llvm/test/CodeGen/X86/pmul.ll | 8 ++++---- llvm/test/CodeGen/X86/vector-idiv.ll | 16 +++++++++++----- 3 files changed, 18 insertions(+), 14 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index c961d22..ce06eb9 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -970,6 +970,7 @@ void X86TargetLowering::resetOperationActions() { setOperationAction(ISD::MUL, MVT::v4i32, Custom); setOperationAction(ISD::MUL, MVT::v2i64, Custom); setOperationAction(ISD::UMUL_LOHI, MVT::v4i32, Custom); + setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom); setOperationAction(ISD::MULHU, MVT::v8i16, Legal); setOperationAction(ISD::MULHS, MVT::v8i16, Legal); setOperationAction(ISD::SUB, MVT::v16i8, Legal); @@ -1112,8 +1113,6 @@ void X86TargetLowering::resetOperationActions() { // FIXME: Do we need to handle scalar-to-vector here? setOperationAction(ISD::MUL, MVT::v4i32, Legal); - setOperationAction(ISD::SMUL_LOHI, MVT::v4i32, Custom); - setOperationAction(ISD::VSELECT, MVT::v2f64, Custom); setOperationAction(ISD::VSELECT, MVT::v2i64, Custom); setOperationAction(ISD::VSELECT, MVT::v4i32, Custom); @@ -15433,9 +15432,8 @@ static SDValue LowerMUL_LOHI(SDValue Op, const X86Subtarget *Subtarget, // ints. MVT MulVT = VT == MVT::v4i32 ? MVT::v2i64 : MVT::v4i64; bool IsSigned = Op->getOpcode() == ISD::SMUL_LOHI; - assert((!IsSigned || Subtarget->hasSSE41()) && - "We need PMULDQ for signed multiplies!"); - unsigned Opcode = IsSigned ? X86ISD::PMULDQ : X86ISD::PMULUDQ; + unsigned Opcode = + (!IsSigned || !Subtarget->hasSSE41()) ? X86ISD::PMULUDQ : X86ISD::PMULDQ; // PMULUDQ <4 x i32> , <4 x i32> // => <2 x i64> SDValue Mul1 = DAG.getNode(ISD::BITCAST, dl, VT, diff --git a/llvm/test/CodeGen/X86/pmul.ll b/llvm/test/CodeGen/X86/pmul.ll index e129d56..4944d6b 100644 --- a/llvm/test/CodeGen/X86/pmul.ll +++ b/llvm/test/CodeGen/X86/pmul.ll @@ -84,10 +84,10 @@ entry: } define <2 x i64> @f(<2 x i64> %i, <2 x i64> %j) nounwind { -; ALL-LABEL: f: -; ALL: pmuludq -; ALL: pmuludq -; ALL: pmuludq +; CHECK-LABEL: f: +; CHECK: pmuludq +; CHECK: pmuludq +; CHECK: pmuludq entry: ; Use a call to force spills. call void @foo() diff --git a/llvm/test/CodeGen/X86/vector-idiv.ll b/llvm/test/CodeGen/X86/vector-idiv.ll index 0214a47..ec1ce3d 100644 --- a/llvm/test/CodeGen/X86/vector-idiv.ll +++ b/llvm/test/CodeGen/X86/vector-idiv.ll @@ -131,12 +131,18 @@ define <4 x i32> @test8(<4 x i32> %a) { ; SSE41: psrad $2 ; SSE41: padd -; FIXME: scalarized -- there is no signed multiply in SSE. ; SSE-LABEL: test8: -; SSE: imulq -; SSE: imulq -; SSE: imulq -; SSE: imulq +; SSE: pmuludq +; SSE: pshufd $49 +; SSE: pshufd $49 +; SSE: pmuludq +; SSE: shufps $-35 +; SSE: pshufd $-40 +; SSE: psubd +; SSE: padd +; SSE: psrld $31 +; SSE: psrad $2 +; SSE: padd ; AVX-LABEL: test8: ; AVX: vpmuldq -- 2.7.4