From f5b9865c003932c51e974db30037c33b32127dcb Mon Sep 17 00:00:00 2001 From: Ivan Maidanski Date: Wed, 3 Oct 2012 00:08:23 +0400 Subject: [PATCH] Do not include standard_ao_double_t.h where double-CAS is unimplemented * src/atomic_ops/sysdeps/gcc/mips.h: Comment out include standard_ao_double_t.h (since double-CAS is not implemented). * src/atomic_ops/sysdeps/msftc/arm.h: Likewise. * src/atomic_ops/sysdeps/gcc/mips.h: Add TODO item for AO_compare_double_and_swap_double. * src/atomic_ops/sysdeps/gcc/x86_64.h: Include standard_ao_double_t.h only if AO_compare_double_and_swap_double_full defined. * src/atomic_ops/sysdeps/msftc/x86_64.h: Likewise. * src/atomic_ops/sysdeps/sunc/x86.h: Likewise. --- src/atomic_ops/sysdeps/gcc/mips.h | 4 +++- src/atomic_ops/sysdeps/gcc/x86_64.h | 6 ++++-- src/atomic_ops/sysdeps/msftc/arm.h | 3 +-- src/atomic_ops/sysdeps/msftc/x86_64.h | 11 +++++++---- src/atomic_ops/sysdeps/sunc/x86.h | 6 ++++-- 5 files changed, 19 insertions(+), 11 deletions(-) diff --git a/src/atomic_ops/sysdeps/gcc/mips.h b/src/atomic_ops/sysdeps/gcc/mips.h index 525a54a..c658a37 100644 --- a/src/atomic_ops/sysdeps/gcc/mips.h +++ b/src/atomic_ops/sysdeps/gcc/mips.h @@ -21,7 +21,6 @@ #include "../all_aligned_atomic_load_store.h" #include "../acquire_release_volatile.h" #include "../test_and_set_t_is_ao_t.h" -#include "../standard_ao_double_t.h" /* Data dependence does not imply read ordering. */ #define AO_NO_DD_ORDERING @@ -161,6 +160,9 @@ AO_fetch_compare_and_swap(volatile AO_t *addr, AO_t old, AO_t new_val) } #define AO_HAVE_fetch_compare_and_swap +/* #include "../standard_ao_double_t.h" */ +/* TODO: implement AO_compare_double_and_swap_double if available. */ + /* CAS primitives with acquire, release and full semantics are */ /* generated automatically (and AO_int_... primitives are */ /* defined properly after the first generalization pass). */ diff --git a/src/atomic_ops/sysdeps/gcc/x86_64.h b/src/atomic_ops/sysdeps/gcc/x86_64.h index a2d4346..0999068 100644 --- a/src/atomic_ops/sysdeps/gcc/x86_64.h +++ b/src/atomic_ops/sysdeps/gcc/x86_64.h @@ -29,8 +29,6 @@ #include "../test_and_set_t_is_char.h" -#include "../standard_ao_double_t.h" - AO_INLINE void AO_nop_full(void) { @@ -170,6 +168,8 @@ AO_fetch_compare_and_swap_full(volatile AO_t *addr, AO_t old_val, #ifdef AO_CMPXCHG16B_AVAILABLE +# include "../standard_ao_double_t.h" + /* NEC LE-IT: older AMD Opterons are missing this instruction. * On these machines SIGILL will be thrown. * Define AO_WEAK_DOUBLE_CAS_EMULATION to have an emulated @@ -199,6 +199,8 @@ AO_compare_double_and_swap_double_full(volatile AO_double_t *addr, /* not atomic with respect to other kinds of updates of *addr. On the */ /* other hand, this may be a useful facility on occasion. */ #ifdef AO_WEAK_DOUBLE_CAS_EMULATION +# include "../standard_ao_double_t.h" + int AO_compare_double_and_swap_double_emulation(volatile AO_double_t *addr, AO_t old_val1, AO_t old_val2, AO_t new_val1, AO_t new_val2); diff --git a/src/atomic_ops/sysdeps/msftc/arm.h b/src/atomic_ops/sysdeps/msftc/arm.h index 36e45f0..a4fd565 100644 --- a/src/atomic_ops/sysdeps/msftc/arm.h +++ b/src/atomic_ops/sysdeps/msftc/arm.h @@ -33,8 +33,6 @@ #if _M_ARM >= 6 /* ARMv6 is the first architecture providing support for simple LL/SC. */ -#include "../standard_ao_double_t.h" - /* If only a single processor is used, we can define AO_UNIPROCESSOR */ /* and do not need to access CP15 for ensuring a DMB at all. */ #ifdef AO_UNIPROCESSOR @@ -75,6 +73,7 @@ AO_store_full(volatile AO_t *addr, AO_t value) } #define AO_HAVE_store_full +/* #include "../standard_ao_double_t.h" */ /* FIXME: implement AO_compare_double_and_swap_double() */ #else /* _M_ARM < 6 */ diff --git a/src/atomic_ops/sysdeps/msftc/x86_64.h b/src/atomic_ops/sysdeps/msftc/x86_64.h index 254eec4..e7f9c32 100644 --- a/src/atomic_ops/sysdeps/msftc/x86_64.h +++ b/src/atomic_ops/sysdeps/msftc/x86_64.h @@ -37,8 +37,6 @@ # include "../test_and_set_t_is_ao_t.h" #endif -#include "../standard_ao_double_t.h" - #include /* Seems like over-kill, but that's what MSDN recommends. */ /* And apparently winbase.h is not always self-contained. */ @@ -119,7 +117,9 @@ AO_test_and_set_full(volatile AO_TS_t *addr) # if _MSC_VER >= 1500 -#pragma intrinsic (_InterlockedCompareExchange128) +# include "../standard_ao_double_t.h" + +# pragma intrinsic (_InterlockedCompareExchange128) AO_INLINE int AO_compare_double_and_swap_double_full(volatile AO_double_t *addr, @@ -135,6 +135,9 @@ AO_compare_double_and_swap_double_full(volatile AO_double_t *addr, # define AO_HAVE_compare_double_and_swap_double_full # elif defined(AO_ASM_X64_AVAILABLE) + +# include "../standard_ao_double_t.h" + /* If there is no intrinsic _InterlockedCompareExchange128 then we */ /* need basically what's given below. */ AO_INLINE int @@ -153,6 +156,6 @@ AO_compare_double_and_swap_double_full(volatile AO_double_t *addr, } } # define AO_HAVE_compare_double_and_swap_double_full -# endif /* _MSC_VER >= 1500 || AO_ASM_X64_AVAILABLE */ +# endif /* AO_ASM_X64_AVAILABLE && (_MSC_VER < 1500) */ #endif /* AO_CMPXCHG16B_AVAILABLE */ diff --git a/src/atomic_ops/sysdeps/sunc/x86.h b/src/atomic_ops/sysdeps/sunc/x86.h index 7d2e8d2..12b2e21 100644 --- a/src/atomic_ops/sysdeps/sunc/x86.h +++ b/src/atomic_ops/sysdeps/sunc/x86.h @@ -31,8 +31,6 @@ #include "../test_and_set_t_is_char.h" -#include "../standard_ao_double_t.h" - #if !defined(AO_USE_PENTIUM4_INSTRS) && !defined(__i386) /* "mfence" (SSE2) is supported on all x86_64/amd64 chips. */ # define AO_USE_PENTIUM4_INSTRS @@ -168,6 +166,8 @@ AO_fetch_compare_and_swap_full(volatile AO_t *addr, AO_t old_val, #if defined(__i386) # ifndef AO_NO_CMPXCHG8B +# include "../standard_ao_double_t.h" + /* Returns nonzero if the comparison succeeded. */ /* Really requires at least a Pentium. */ AO_INLINE int @@ -205,6 +205,8 @@ AO_fetch_compare_and_swap_full(volatile AO_t *addr, AO_t old_val, # define AO_HAVE_int_fetch_and_add_full # ifdef AO_CMPXCHG16B_AVAILABLE +# include "../standard_ao_double_t.h" + /* Older AMD Opterons are missing this instruction (SIGILL should */ /* be thrown in this case). */ AO_INLINE int -- 2.7.4