From f59d0715b1581d627eab52e03f81dcb6c4f9c008 Mon Sep 17 00:00:00 2001 From: Tony Tye Date: Fri, 10 Nov 2017 20:51:43 +0000 Subject: [PATCH] [AMDGPU] AMDGPUUsage.rst minor corrections Differential Revision: https://reviews.llvm.org/D39887 llvm-svn: 317924 --- llvm/docs/AMDGPUUsage.rst | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/llvm/docs/AMDGPUUsage.rst b/llvm/docs/AMDGPUUsage.rst index 9ff266e..8d40202 100644 --- a/llvm/docs/AMDGPUUsage.rst +++ b/llvm/docs/AMDGPUUsage.rst @@ -2099,7 +2099,9 @@ SGPR register initial state is defined in instructions. Having CP load it once avoids loading it at the beginning of every - wavefront. GFX9 This is the + wavefront. + GFX9 + This is the 64 bit base address of the per SPI scratch backing memory managed by SPI for @@ -2116,18 +2118,17 @@ SGPR register initial state is defined in SGPR which is SGPRn-6 and SGPRn-5. It is used as the FLAT SCRATCH BASE in flat - memory instructions. then - Private Segment Size 1 The - 32 bit byte size of a - (enable_sgpr_private single - work-item's - scratch_segment_size) memory - allocation. This is the - value from the kernel - dispatch packet Private - Segment Byte Size rounded up - by CP to a multiple of - DWORD. + memory instructions. + then Private Segment Size 1 The 32 bit byte size of a + (enable_sgpr_private single + work-item's + scratch_segment_size) memory + allocation. This is the + value from the kernel + dispatch packet Private + Segment Byte Size rounded up + by CP to a multiple of + DWORD. Having CP load it once avoids loading it at the beginning of @@ -2300,6 +2301,7 @@ GFX7-GFX8 DWORD. Having CP load it once avoids loading it at the beginning of every wavefront. The prolog must move it to FLAT_SCRATCH_LO for use as FLAT SCRATCH SIZE. + GFX9 The Flat Scratch Init is the 64 bit address of the base of scratch backing memory being managed by SPI for the queue executing the kernel dispatch. The @@ -3800,7 +3802,7 @@ Assembler --------- AMDGPU backend has LLVM-MC based assembler which is currently in development. -It supports AMDGCN GFX6-GFX8. +It supports AMDGCN GFX6-GFX9. This section describes general syntax for instructions and operands. For more information about instructions, their semantics and supported combinations of -- 2.7.4