From f56af5f9c20ca8cf4ee916bbfc06d8c1584868cb Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Mon, 10 May 2021 12:51:45 +0000 Subject: [PATCH] arm: MVE: Cleanup vcmpne/vcmpeq builtins After the previous patch, we no longer need to emit the unsigned variants of vcmpneq/vcmpeqq. This patch removes them as well as the corresponding iterator entries. 2021-05-10 Christophe Lyon gcc/ * config/arm/arm_mve_builtins.def (vcmpneq_u): Remove. (vcmpneq_n_u): Likewise. (vcmpeqq_u,): Likewise. (vcmpeqq_n_u): Likewise. * config/arm/iterators.md (supf): Remove VCMPNEQ_U, VCMPEQQ_U, VCMPEQQ_N_U and VCMPNEQ_N_U. * config/arm/mve.md (mve_vcmpneq): Remove iteration. (mve_vcmpeqq_n): Likewise. (mve_vcmpeqq): Likewise. (mve_vcmpneq_n): Likewise. --- gcc/config/arm/arm_mve_builtins.def | 4 ---- gcc/config/arm/iterators.md | 15 +++++++-------- gcc/config/arm/mve.md | 16 ++++++++-------- 3 files changed, 15 insertions(+), 20 deletions(-) diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_builtins.def index 460f6ba..ee34fd1 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -90,7 +90,6 @@ VAR3 (BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si) VAR1 (BINOP_NONE_NONE_UNONE, vaddlvq_p_s, v4si) VAR1 (BINOP_UNONE_UNONE_UNONE, vaddlvq_p_u, v4si) VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_s, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpneq_u, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vshlq_s, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vsubq_u, v16qi, v8hi, v4si) @@ -118,11 +117,8 @@ VAR3 (BINOP_UNONE_UNONE_UNONE, vhsubq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, veorq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpneq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_n_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpeqq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpeqq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si) diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 8fb723e..0aba93f 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -1279,13 +1279,12 @@ (VCREATEQ_U "u") (VCREATEQ_S "s") (VSHRQ_N_S "s") (VSHRQ_N_U "u") (VCVTQ_N_FROM_F_S "s") (VSHLQ_U "u") (VCVTQ_N_FROM_F_U "u") (VADDLVQ_P_S "s") (VSHLQ_S "s") - (VADDLVQ_P_U "u") (VCMPNEQ_U "u") (VCMPNEQ_S "s") + (VADDLVQ_P_U "u") (VCMPNEQ_S "s") (VABDQ_M_S "s") (VABDQ_M_U "u") (VABDQ_S "s") (VABDQ_U "u") (VADDQ_N_S "s") (VADDQ_N_U "u") (VADDVQ_P_S "s") (VADDVQ_P_U "u") (VBRSRQ_N_S "s") - (VBRSRQ_N_U "u") (VCMPEQQ_S "s") (VCMPEQQ_U "u") - (VCMPEQQ_N_S "s") (VCMPEQQ_N_U "u") (VCMPNEQ_N_S "s") - (VCMPNEQ_N_U "u") + (VBRSRQ_N_U "u") (VCMPEQQ_S "s") + (VCMPEQQ_N_S "s") (VCMPNEQ_N_S "s") (VHADDQ_N_S "s") (VHADDQ_N_U "u") (VHADDQ_S "s") (VHADDQ_U "u") (VHSUBQ_N_S "s") (VHSUBQ_N_U "u") (VHSUBQ_S "s") (VMAXQ_S "s") (VMAXQ_U "u") (VHSUBQ_U "u") @@ -1541,16 +1540,16 @@ (define_int_iterator VSHRQ_N [VSHRQ_N_S VSHRQ_N_U]) (define_int_iterator VCVTQ_N_FROM_F [VCVTQ_N_FROM_F_S VCVTQ_N_FROM_F_U]) (define_int_iterator VADDLVQ_P [VADDLVQ_P_S VADDLVQ_P_U]) -(define_int_iterator VCMPNEQ [VCMPNEQ_U VCMPNEQ_S]) +(define_int_iterator VCMPNEQ [VCMPNEQ_S]) (define_int_iterator VSHLQ [VSHLQ_S VSHLQ_U]) (define_int_iterator VABDQ [VABDQ_S VABDQ_U]) (define_int_iterator VADDQ_N [VADDQ_N_S VADDQ_N_U]) (define_int_iterator VADDVAQ [VADDVAQ_S VADDVAQ_U]) (define_int_iterator VADDVQ_P [VADDVQ_P_U VADDVQ_P_S]) (define_int_iterator VBRSRQ_N [VBRSRQ_N_U VBRSRQ_N_S]) -(define_int_iterator VCMPEQQ [VCMPEQQ_U VCMPEQQ_S]) -(define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S VCMPEQQ_N_U]) -(define_int_iterator VCMPNEQ_N [VCMPNEQ_N_U VCMPNEQ_N_S]) +(define_int_iterator VCMPEQQ [VCMPEQQ_S]) +(define_int_iterator VCMPEQQ_N [VCMPEQQ_N_S]) +(define_int_iterator VCMPNEQ_N [VCMPNEQ_N_S]) (define_int_iterator VHADDQ [VHADDQ_S VHADDQ_U]) (define_int_iterator VHADDQ_N [VHADDQ_N_U VHADDQ_N_S]) (define_int_iterator VHSUBQ [VHSUBQ_S VHSUBQ_U]) diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 5c11885..9712bc0 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -811,9 +811,9 @@ (set_attr "length""8")]) ;; -;; [vcmpneq_u, vcmpneq_s]) +;; [vcmpneq_s]) ;; -(define_insn "mve_vcmpneq_" +(define_insn "mve_vcmpneq_s" [ (set (match_operand:HI 0 "vpr_register_operand" "=Up") (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") @@ -1010,9 +1010,9 @@ ]) ;; -;; [vcmpeqq_n_s, vcmpeqq_n_u]) +;; [vcmpeqq_n_s]) ;; -(define_insn "mve_vcmpeqq_n_" +(define_insn "mve_vcmpeqq_n_s" [ (set (match_operand:HI 0 "vpr_register_operand" "=Up") (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") @@ -1025,9 +1025,9 @@ ]) ;; -;; [vcmpeqq_u, vcmpeqq_s]) +;; [vcmpeqq_s]) ;; -(define_insn "mve_vcmpeqq_" +(define_insn "mve_vcmpeqq_s" [ (set (match_operand:HI 0 "vpr_register_operand" "=Up") (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") @@ -1190,9 +1190,9 @@ ]) ;; -;; [vcmpneq_n_u, vcmpneq_n_s]) +;; [vcmpneq_n_s]) ;; -(define_insn "mve_vcmpneq_n_" +(define_insn "mve_vcmpneq_n_s" [ (set (match_operand:HI 0 "vpr_register_operand" "=Up") (unspec:HI [(match_operand:MVE_2 1 "s_register_operand" "w") -- 2.7.4