From f5540209abc69381b0c3a2983c1fb9b657a1be3c Mon Sep 17 00:00:00 2001 From: Samuel Pitoiset Date: Wed, 10 Mar 2021 16:21:34 +0100 Subject: [PATCH] radv: enable VRS 2x2 coarse shading for flat shading on GFX10.3+ This should safe to enable and shouldn't degrade the quality. It decreases the number of PS invocations by 4 when used. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen Part-of: --- src/amd/vulkan/radv_pipeline.c | 20 ++++++++++++++++++-- src/amd/vulkan/si_cmd_buffer.c | 9 --------- 2 files changed, 18 insertions(+), 11 deletions(-) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index acac2d3..c4176cc4 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -5321,16 +5321,32 @@ gfx103_pipeline_vrs_coarse_shading(const struct radv_pipeline *pipeline) static void gfx103_pipeline_generate_vrs_state(struct radeon_cmdbuf *ctx_cs, + const struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo) { + uint32_t mode = V_028064_VRS_COMB_MODE_PASSTHRU; + uint8_t rate_x = 0, rate_y = 0; bool enable_vrs = false; if (vk_find_struct_const(pCreateInfo->pNext, PIPELINE_FRAGMENT_SHADING_RATE_STATE_CREATE_INFO_KHR) || - radv_is_state_dynamic(pCreateInfo, VK_DYNAMIC_STATE_FRAGMENT_SHADING_RATE_KHR)) + radv_is_state_dynamic(pCreateInfo, VK_DYNAMIC_STATE_FRAGMENT_SHADING_RATE_KHR)) { + /* Enable draw call VRS because it's explicitly requested. */ enable_vrs = true; + } else if (gfx103_pipeline_vrs_coarse_shading(pipeline)) { + /* Enable VRS coarse shading 2x2 if the driver determined that + * it's safe to enable. + */ + mode = V_028064_VRS_COMB_MODE_OVERRIDE; + rate_x = rate_y = 1; + } radeon_set_context_reg(ctx_cs, R_028A98_VGT_DRAW_PAYLOAD_CNTL, S_028A98_EN_VRS_RATE(enable_vrs)); + + radeon_set_context_reg(ctx_cs, R_028064_DB_VRS_OVERRIDE_CNTL, + S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(mode) | + S_028064_VRS_OVERRIDE_RATE_X(rate_x) | + S_028064_VRS_OVERRIDE_RATE_Y(rate_y)); } static void @@ -5371,7 +5387,7 @@ radv_pipeline_generate_pm4(struct radv_pipeline *pipeline, gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline); if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) - gfx103_pipeline_generate_vrs_state(ctx_cs, pCreateInfo); + gfx103_pipeline_generate_vrs_state(ctx_cs, pipeline, pCreateInfo); pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4); diff --git a/src/amd/vulkan/si_cmd_buffer.c b/src/amd/vulkan/si_cmd_buffer.c index 39ac7ab..2449f9a 100644 --- a/src/amd/vulkan/si_cmd_buffer.c +++ b/src/amd/vulkan/si_cmd_buffer.c @@ -506,15 +506,6 @@ si_emit_graphics(struct radv_device *device, /* This allows sample shading. */ radeon_set_context_reg(cs, R_028848_PA_CL_VRS_CNTL, S_028848_SAMPLE_ITER_COMBINER_MODE(1)); - - /* This is the main VRS register and also the last - * combiner, set it to passthrough mode because other - * combiners are configured with PA_CL_VRS_CNTL. - */ - radeon_set_context_reg(cs, R_028064_DB_VRS_OVERRIDE_CNTL, - S_028064_VRS_OVERRIDE_RATE_COMBINER_MODE(V_028064_VRS_COMB_MODE_PASSTHRU) | - S_028064_VRS_OVERRIDE_RATE_X(0) | - S_028064_VRS_OVERRIDE_RATE_Y(0)); } if (physical_device->rad_info.chip_class == GFX10) { -- 2.7.4