From f4bfe4cd178e09d3ceafb613fb61a70ba845cab8 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Mon, 25 Feb 2019 21:32:48 +0000 Subject: [PATCH] AMDGPU/GlobalISel: Fix bit ops for non-power-of-2 sizes llvm-svn: 354825 --- llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 2 + .../CodeGen/AMDGPU/GlobalISel/legalize-and.mir | 23 +++++++++++ .../AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir | 6 ++- .../CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir | 6 ++- .../CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir | 6 ++- .../AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir | 6 ++- .../CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir | 6 ++- .../test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir | 23 +++++++++++ .../AMDGPU/GlobalISel/legalize-unmerge-values.mir | 47 +++++++++++++--------- .../CodeGen/AMDGPU/GlobalISel/legalize-xor.mir | 23 +++++++++++ 10 files changed, 120 insertions(+), 28 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index d073e43..3b66b31 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -174,6 +174,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST, .clampScalar(0, S32, S64) .moreElementsIf(isSmallOddVector(0), oneMoreElement(0)) .fewerElementsIf(vectorWiderThan(0, 32), fewerEltsToSize64Vector(0)) + .widenScalarToNextPow2(0) .scalarize(0); getActionDefinitionsBuilder({G_UADDO, G_SADDO, G_USUBO, G_SSUBO, @@ -270,6 +271,7 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST, .legalFor({{S64, S32}, {S32, S16}, {S64, S16}, {S32, S1}, {S64, S1}, {S16, S1}, // FIXME: Hack + {S64, LLT::scalar(33)}, {S32, S8}, {S128, S32}, {S128, S64}, {S32, LLT::scalar(24)}}) .scalarize(0); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir index 93b30ee..232dbf4 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-and.mir @@ -148,6 +148,29 @@ body: | ... --- +name: test_and_s48 +body: | + bb.0: + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + + ; CHECK-LABEL: name: test_and_s48 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 + ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 + ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) + ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) + ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]] + ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND]](s64) + ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64) + %0:_(s64) = COPY $vgpr0_vgpr1 + %1:_(s64) = COPY $vgpr2_vgpr3 + %2:_(s48) = G_TRUNC %0 + %3:_(s48) = G_TRUNC %1 + %4:_(s48) = G_AND %2, %3 + %5:_(s64) = G_ANYEXT %4 + $vgpr0_vgpr1 = COPY %5 +... + +--- name: test_and_v2s32 body: | bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir index a1322c9..211d06d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz-zero-undef.mir @@ -205,8 +205,10 @@ body: | ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32) ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64) - ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C2]] - ; CHECK: $vgpr0_vgpr1 = COPY [[AND1]](s64) + ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C2]](s64) + ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]] + ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64) + ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64) %0:_(s64) = COPY $vgpr0_vgpr1 %1:_(s33) = G_TRUNC %0 %2:_(s33) = G_CTLZ_ZERO_UNDEF %1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir index 41a5daa..fe505f0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctlz.mir @@ -205,8 +205,10 @@ body: | ; CHECK: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[USUBO]](s32), [[USUBE]](s32) ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[MV]](s64) - ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C2]] - ; CHECK: $vgpr0_vgpr1 = COPY [[AND1]](s64) + ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C2]](s64) + ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]] + ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64) + ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64) %0:_(s64) = COPY $vgpr0_vgpr1 %1:_(s33) = G_TRUNC %0 %2:_(s33) = G_CTLZ %1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir index 7166235..7dde74c 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ctpop.mir @@ -191,8 +191,10 @@ body: | ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTPOP]](s32) ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ZEXT]](s64) - ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]] - ; CHECK: $vgpr0_vgpr1 = COPY [[AND1]](s64) + ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C1]](s64) + ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]] + ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64) + ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64) %0:_(s64) = COPY $vgpr0_vgpr1 %1:_(s33) = G_TRUNC %0 %2:_(s33) = G_CTPOP %1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir index 800a64e..20eadce 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz-zero-undef.mir @@ -191,8 +191,10 @@ body: | ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ_ZERO_UNDEF]](s32) ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ZEXT]](s64) - ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C1]] - ; CHECK: $vgpr0_vgpr1 = COPY [[AND1]](s64) + ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C1]](s64) + ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]] + ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64) + ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64) %0:_(s64) = COPY $vgpr0_vgpr1 %1:_(s33) = G_TRUNC %0 %2:_(s33) = G_CTTZ_ZERO_UNDEF %1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir index 2e9a40a..1b921ab 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-cttz.mir @@ -201,8 +201,10 @@ body: | ; CHECK: [[ZEXT:%[0-9]+]]:_(s64) = G_ZEXT [[CTTZ]](s32) ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 4294967295 ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[ZEXT]](s64) - ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[C2]] - ; CHECK: $vgpr0_vgpr1 = COPY [[AND1]](s64) + ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[C2]](s64) + ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[COPY2]], [[COPY3]] + ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[AND1]](s64) + ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64) %0:_(s64) = COPY $vgpr0_vgpr1 %1:_(s33) = G_TRUNC %0 %2:_(s33) = G_CTTZ %1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir index 424256e..9da7bad 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-or.mir @@ -148,6 +148,29 @@ body: | ... --- +name: test_or_s48 +body: | + bb.0: + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + + ; CHECK-LABEL: name: test_or_s48 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 + ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 + ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) + ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) + ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY2]], [[COPY3]] + ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[OR]](s64) + ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64) + %0:_(s64) = COPY $vgpr0_vgpr1 + %1:_(s64) = COPY $vgpr2_vgpr3 + %2:_(s48) = G_TRUNC %0 + %3:_(s48) = G_TRUNC %1 + %4:_(s48) = G_OR %2, %3 + %5:_(s64) = G_ANYEXT %4 + $vgpr0_vgpr1 = COPY %5 +... + +--- name: test_or_v2s32 body: | bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir index fbd9717..f7adb87 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-unmerge-values.mir @@ -199,24 +199,35 @@ body: | liveins: $vgpr0 ; CHECK-LABEL: name: test_unmerge_s1_s3 ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 - ; CHECK: [[TRUNC:%[0-9]+]]:_(s3) = G_TRUNC [[COPY]](s32) - ; CHECK: [[ZEXT:%[0-9]+]]:_(s48) = G_ZEXT [[TRUNC]](s3) - ; CHECK: [[C:%[0-9]+]]:_(s48) = G_CONSTANT i48 15 - ; CHECK: [[SHL:%[0-9]+]]:_(s48) = G_SHL [[ZEXT]], [[C]](s48) - ; CHECK: [[OR:%[0-9]+]]:_(s48) = G_OR [[ZEXT]], [[SHL]] - ; CHECK: [[C1:%[0-9]+]]:_(s48) = G_CONSTANT i48 30 - ; CHECK: [[SHL1:%[0-9]+]]:_(s48) = G_SHL [[OR]], [[C1]](s48) - ; CHECK: [[OR1:%[0-9]+]]:_(s48) = G_OR [[OR]], [[SHL1]] - ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[OR1]](s48) - ; CHECK: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[UV]](s16) - ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC1]](s1) - ; CHECK: [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[UV1]](s16) - ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC2]](s1) - ; CHECK: [[TRUNC3:%[0-9]+]]:_(s1) = G_TRUNC [[UV2]](s16) - ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[TRUNC3]](s1) - ; CHECK: $vgpr0 = COPY [[ANYEXT]](s32) - ; CHECK: $vgpr1 = COPY [[ANYEXT1]](s32) - ; CHECK: $vgpr2 = COPY [[ANYEXT2]](s32) + ; CHECK: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 15 + ; CHECK: [[TRUNC:%[0-9]+]]:_(s48) = G_TRUNC [[C]](s64) + ; CHECK: [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC]](s48) + ; CHECK: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 + ; CHECK: [[ANYEXT:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32) + ; CHECK: [[AND:%[0-9]+]]:_(s64) = G_AND [[ANYEXT]], [[C1]] + ; CHECK: [[SHL:%[0-9]+]]:_(s64) = G_SHL [[AND]], [[TRUNC1]](s32) + ; CHECK: [[C2:%[0-9]+]]:_(s64) = G_CONSTANT i64 7 + ; CHECK: [[ANYEXT1:%[0-9]+]]:_(s64) = G_ANYEXT [[COPY]](s32) + ; CHECK: [[AND1:%[0-9]+]]:_(s64) = G_AND [[ANYEXT1]], [[C2]] + ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY [[SHL]](s64) + ; CHECK: [[OR:%[0-9]+]]:_(s64) = G_OR [[AND1]], [[COPY1]] + ; CHECK: [[TRUNC2:%[0-9]+]]:_(s48) = G_TRUNC [[OR]](s64) + ; CHECK: [[C3:%[0-9]+]]:_(s64) = G_CONSTANT i64 30 + ; CHECK: [[TRUNC3:%[0-9]+]]:_(s48) = G_TRUNC [[C3]](s64) + ; CHECK: [[TRUNC4:%[0-9]+]]:_(s32) = G_TRUNC [[TRUNC3]](s48) + ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[OR]](s64) + ; CHECK: [[SHL1:%[0-9]+]]:_(s64) = G_SHL [[COPY2]], [[TRUNC4]](s32) + ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[OR]](s64) + ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[SHL1]](s64) + ; CHECK: [[OR1:%[0-9]+]]:_(s64) = G_OR [[COPY3]], [[COPY4]] + ; CHECK: [[TRUNC5:%[0-9]+]]:_(s48) = G_TRUNC [[OR1]](s64) + ; CHECK: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[TRUNC5]](s48) + ; CHECK: [[ANYEXT2:%[0-9]+]]:_(s32) = G_ANYEXT [[UV]](s16) + ; CHECK: [[ANYEXT3:%[0-9]+]]:_(s32) = G_ANYEXT [[UV1]](s16) + ; CHECK: [[ANYEXT4:%[0-9]+]]:_(s32) = G_ANYEXT [[UV2]](s16) + ; CHECK: $vgpr0 = COPY [[ANYEXT2]](s32) + ; CHECK: $vgpr1 = COPY [[ANYEXT3]](s32) + ; CHECK: $vgpr2 = COPY [[ANYEXT4]](s32) %0:_(s32) = COPY $vgpr0 %1:_(s3) = G_TRUNC %0 %2:_(s1), %3:_(s1), %4:_(s1) = G_UNMERGE_VALUES %1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir index de7bbfa..4d50e08 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-xor.mir @@ -148,6 +148,29 @@ body: | ... --- +name: test_xor_s48 +body: | + bb.0: + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + + ; CHECK-LABEL: name: test_xor_s48 + ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 + ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $vgpr2_vgpr3 + ; CHECK: [[COPY2:%[0-9]+]]:_(s64) = COPY [[COPY]](s64) + ; CHECK: [[COPY3:%[0-9]+]]:_(s64) = COPY [[COPY1]](s64) + ; CHECK: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY2]], [[COPY3]] + ; CHECK: [[COPY4:%[0-9]+]]:_(s64) = COPY [[XOR]](s64) + ; CHECK: $vgpr0_vgpr1 = COPY [[COPY4]](s64) + %0:_(s64) = COPY $vgpr0_vgpr1 + %1:_(s64) = COPY $vgpr2_vgpr3 + %2:_(s48) = G_TRUNC %0 + %3:_(s48) = G_TRUNC %1 + %4:_(s48) = G_XOR %2, %3 + %5:_(s64) = G_ANYEXT %4 + $vgpr0_vgpr1 = COPY %5 +... + +--- name: test_xor_v2s32 body: | bb.0: -- 2.7.4