From f408971deb7821cc140f1d373a104c2e1cb24eeb Mon Sep 17 00:00:00 2001 From: Jason Ekstrand Date: Mon, 20 Feb 2017 10:37:34 -0800 Subject: [PATCH] anv: Pull all clflushing into a clflush_range helper All this cache line address calculation stuff is tricky. Let's not duplicate it more places than we have to. Reviewed-by: Lionel Landwerlin --- src/intel/vulkan/anv_device.c | 15 ++++----------- src/intel/vulkan/anv_private.h | 18 +++++++++--------- 2 files changed, 13 insertions(+), 20 deletions(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index f14c1ab..f52b42a 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -1486,18 +1486,11 @@ clflush_mapped_ranges(struct anv_device *device, { for (uint32_t i = 0; i < count; i++) { ANV_FROM_HANDLE(anv_device_memory, mem, ranges[i].memory); - void *p = mem->map + (ranges[i].offset & ~CACHELINE_MASK); - void *end; + if (ranges[i].offset >= mem->map_size) + continue; - if (ranges[i].offset + ranges[i].size > mem->map_size) - end = mem->map + mem->map_size; - else - end = mem->map + ranges[i].offset + ranges[i].size; - - while (p < end) { - __builtin_ia32_clflush(p); - p += CACHELINE_SIZE; - } + anv_clflush_range(mem->map + ranges[i].offset, + MIN2(ranges[i].size, mem->map_size - ranges[i].offset)); } } diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index dd8ba32..7bf340b 100644 --- a/src/intel/vulkan/anv_private.h +++ b/src/intel/vulkan/anv_private.h @@ -436,12 +436,11 @@ struct anv_state_stream { #define CACHELINE_MASK 63 static inline void -anv_flush_range(void *start, size_t size) +anv_clflush_range(void *start, size_t size) { void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK); void *end = start + size; - __builtin_ia32_mfence(); while (p < end) { __builtin_ia32_clflush(p); p += CACHELINE_SIZE; @@ -449,15 +448,16 @@ anv_flush_range(void *start, size_t size) } static inline void -anv_invalidate_range(void *start, size_t size) +anv_flush_range(void *start, size_t size) { - void *p = (void *) (((uintptr_t) start) & ~CACHELINE_MASK); - void *end = start + size; + __builtin_ia32_mfence(); + anv_clflush_range(start, size); +} - while (p < end) { - __builtin_ia32_clflush(p); - p += CACHELINE_SIZE; - } +static inline void +anv_invalidate_range(void *start, size_t size) +{ + anv_clflush_range(start, size); __builtin_ia32_mfence(); } -- 2.7.4