From f3e73e88fdd63e3342977873a5f2c3f870a2497a Mon Sep 17 00:00:00 2001 From: Simon Tatham Date: Mon, 20 Jan 2020 13:25:50 +0000 Subject: [PATCH] [ARM,MVE] Fix confusing MC names for MVE VMINA/VMAXA insns. Summary: A recent commit accidentally defined names like `MVE_VMAXAs8` as instances of the multiclass `MVE_VMINA`, and vice versa. This has no effect on the test suite, because nothing directly refers to those instruction names (the isel patterns are generated in Tablegen using `!cast(NAME)` inside a lower-level multiclass). But it means that `llvm-mc -show-inst` was listing VMAXA as VMINA, and it would also affect any further draft code gen patches that use those instruction ids. Reviewers: MarkMurrayARM, dmgreen, miyuki, ostannard Reviewed By: dmgreen Subscribers: kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D73034 --- llvm/lib/Target/ARM/ARMInstrMVE.td | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Target/ARM/ARMInstrMVE.td b/llvm/lib/Target/ARM/ARMInstrMVE.td index c26af8b..70f1d75 100644 --- a/llvm/lib/Target/ARM/ARMInstrMVE.td +++ b/llvm/lib/Target/ARM/ARMInstrMVE.td @@ -2312,16 +2312,16 @@ multiclass MVE_VMINMAXA_m : MVE_VMINMAXA_m<"vmina", VTI, umin, int_arm_mve_vmina_predicated, 0b1>; -defm MVE_VMAXAs8 : MVE_VMINA; -defm MVE_VMAXAs16 : MVE_VMINA; -defm MVE_VMAXAs32 : MVE_VMINA; +defm MVE_VMINAs8 : MVE_VMINA; +defm MVE_VMINAs16 : MVE_VMINA; +defm MVE_VMINAs32 : MVE_VMINA; multiclass MVE_VMAXA : MVE_VMINMAXA_m<"vmaxa", VTI, umax, int_arm_mve_vmaxa_predicated, 0b0>; -defm MVE_VMINAs8 : MVE_VMAXA; -defm MVE_VMINAs16 : MVE_VMAXA; -defm MVE_VMINAs32 : MVE_VMAXA; +defm MVE_VMAXAs8 : MVE_VMAXA; +defm MVE_VMAXAs16 : MVE_VMAXA; +defm MVE_VMAXAs32 : MVE_VMAXA; // end of MVE Integer instructions -- 2.7.4