From f337b93018fa596ef1878588c5efd4dd16caab73 Mon Sep 17 00:00:00 2001 From: Adrian Straetling Date: Mon, 9 May 2005 17:21:03 +0000 Subject: [PATCH] s390.md: ("SHIFT"): New mode macro. 2005-05-09 Adrian Straetling * config/s390/s390.md: ("SHIFT"): New mode macro. ("lr", "shift"): New mode attributes. ("ashldi3", "lshrdi3"): Merge. ("*ashldi3_31", "*lshrdi3"_31): Merge. ("*ashldi3_64", "*lshrdi3"_64): Merge. ("ashlsi3", "lshrsi3"): Merge. From-SVN: r99455 --- gcc/ChangeLog | 9 +++++ gcc/config/s390/s390.md | 95 ++++++++++++++++--------------------------------- 2 files changed, 39 insertions(+), 65 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 319c022..c0d57d6 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,5 +1,14 @@ 2005-05-09 Adrian Straetling + * config/s390/s390.md: ("SHIFT"): New mode macro. + ("lr", "shift"): New mode attributes. + ("ashldi3", "lshrdi3"): Merge. + ("*ashldi3_31", "*lshrdi3"_31): Merge. + ("*ashldi3_64", "*lshrdi3"_64): Merge. + ("ashlsi3", "lshrsi3"): Merge. + +2005-05-09 Adrian Straetling + * config/s390/s390.md: ("DSI", "SCOND"): New mode macros. ("E", "g"): New mode attributes. diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index 6557721..39e9aba 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -259,6 +259,18 @@ ;; This macro allows to unify all 'sCOND' patterns. (define_code_macro SCOND [ltu gtu leu geu]) +;; This macro allows some 'ashift' and 'lshiftrt' pattern to be defined from +;; the same template. +(define_code_macro SHIFT [ashift lshiftrt]) + + +;; In SHIFT templates, a string like "sdl" will expand to "sldl" in +;; 'ashift' and "srdl" in 'lshiftrt'. +(define_code_attr lr [(ashift "l") (lshiftrt "r")]) + +;; In SHIFT templates, this attribute holds the correct standard name for the +;; pattern itself and the corresponding function calls. +(define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) ;; This attribute handles differences in the instruction 'type' and will result ;; in "RRE" for DImode and "RR" for SImode. @@ -6329,35 +6341,35 @@ ;; -;;- Arithmetic shift instructions. +;;- Shift instructions. ;; ; -; ashldi3 instruction pattern(s). +; (ashl|lshr)di3 instruction pattern(s). ; -(define_expand "ashldi3" +(define_expand "di3" [(set (match_operand:DI 0 "register_operand" "") - (ashift:DI (match_operand:DI 1 "register_operand" "") - (match_operand:SI 2 "shift_count_operand" "")))] + (SHIFT:DI (match_operand:DI 1 "register_operand" "") + (match_operand:SI 2 "shift_count_operand" "")))] "" "") -(define_insn "*ashldi3_31" +(define_insn "*di3_31" [(set (match_operand:DI 0 "register_operand" "=d") - (ashift:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_operand" "Y")))] + (SHIFT:DI (match_operand:DI 1 "register_operand" "0") + (match_operand:SI 2 "shift_count_operand" "Y")))] "!TARGET_64BIT" - "sldl\t%0,%Y2" + "sdl\t%0,%Y2" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) -(define_insn "*ashldi3_64" +(define_insn "*di3_64" [(set (match_operand:DI 0 "register_operand" "=d") - (ashift:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:SI 2 "shift_count_operand" "Y")))] + (SHIFT:DI (match_operand:DI 1 "register_operand" "d") + (match_operand:SI 2 "shift_count_operand" "Y")))] "TARGET_64BIT" - "sllg\t%0,%1,%Y2" + "slg\t%0,%1,%Y2" [(set_attr "op_type" "RSE") (set_attr "atype" "reg")]) @@ -6442,15 +6454,15 @@ ; -; ashlsi3 instruction pattern(s). +; (ashl|lshr)si3 instruction pattern(s). ; -(define_insn "ashlsi3" +(define_insn "si3" [(set (match_operand:SI 0 "register_operand" "=d") - (ashift:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_operand" "Y")))] + (SHIFT:SI (match_operand:SI 1 "register_operand" "0") + (match_operand:SI 2 "shift_count_operand" "Y")))] "" - "sll\t%0,%Y2" + "sl\t%0,%Y2" [(set_attr "op_type" "RS") (set_attr "atype" "reg")]) @@ -6494,53 +6506,6 @@ ;; -;;- logical shift instructions. -;; - -; -; lshrdi3 instruction pattern(s). -; - -(define_expand "lshrdi3" - [(set (match_operand:DI 0 "register_operand" "") - (lshiftrt:DI (match_operand:DI 1 "register_operand" "") - (match_operand:SI 2 "shift_count_operand" "")))] - "" - "") - -(define_insn "*lshrdi3_31" - [(set (match_operand:DI 0 "register_operand" "=d") - (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_operand" "Y")))] - "!TARGET_64BIT" - "srdl\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - -(define_insn "*lshrdi3_64" - [(set (match_operand:DI 0 "register_operand" "=d") - (lshiftrt:DI (match_operand:DI 1 "register_operand" "d") - (match_operand:SI 2 "shift_count_operand" "Y")))] - "TARGET_64BIT" - "srlg\t%0,%1,%Y2" - [(set_attr "op_type" "RSE") - (set_attr "atype" "reg")]) - -; -; lshrsi3 instruction pattern(s). -; - -(define_insn "lshrsi3" - [(set (match_operand:SI 0 "register_operand" "=d") - (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") - (match_operand:SI 2 "shift_count_operand" "Y")))] - "" - "srl\t%0,%Y2" - [(set_attr "op_type" "RS") - (set_attr "atype" "reg")]) - - -;; ;; Branch instruction patterns. ;; -- 2.7.4