From f2d9fbb6f4a7175ce41afe292d46685ef7752a67 Mon Sep 17 00:00:00 2001 From: Sergey Organov Date: Wed, 1 Feb 2023 17:16:03 +0300 Subject: [PATCH] serial: imx: get rid of registers shadowing Neither registers shadowing is functionally needed as all the registers are read-write, nor the shadowing makes much sense for speed-up, as most speed critical reads/writes (of data Rx/Tx registers) are not shadowed anyway. Moreover, the shadowing code is obviously pure overhead on the write path. Get rid of the shadowing code and variables due to above considerations. Signed-off-by: Sergey Organov Link: https://lore.kernel.org/r/20230201141603.4205-1-sorganov@gmail.com Signed-off-by: Greg Kroah-Hartman --- drivers/tty/serial/imx.c | 67 +++--------------------------------------------- 1 file changed, 4 insertions(+), 63 deletions(-) diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index e2a89b9..363c77a 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c @@ -213,13 +213,6 @@ struct imx_port { /* counter to stop 0xff flood */ int idle_counter; - /* shadow registers */ - unsigned int ucr1; - unsigned int ucr2; - unsigned int ucr3; - unsigned int ucr4; - unsigned int ufcr; - /* DMA fields */ unsigned int dma_is_enabled:1; unsigned int dma_is_rxing:1; @@ -276,59 +269,14 @@ static const struct of_device_id imx_uart_dt_ids[] = { }; MODULE_DEVICE_TABLE(of, imx_uart_dt_ids); -static void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) -{ - switch (offset) { - case UCR1: - sport->ucr1 = val; - break; - case UCR2: - sport->ucr2 = val; - break; - case UCR3: - sport->ucr3 = val; - break; - case UCR4: - sport->ucr4 = val; - break; - case UFCR: - sport->ufcr = val; - break; - default: - break; - } +static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset) +{ writel(val, sport->port.membase + offset); } -static u32 imx_uart_readl(struct imx_port *sport, u32 offset) +static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset) { - switch (offset) { - case UCR1: - return sport->ucr1; - break; - case UCR2: - /* - * UCR2_SRST is the only bit in the cached registers that might - * differ from the value that was last written. As it only - * automatically becomes one after being cleared, reread - * conditionally. - */ - if (!(sport->ucr2 & UCR2_SRST)) - sport->ucr2 = readl(sport->port.membase + offset); - return sport->ucr2; - break; - case UCR3: - return sport->ucr3; - break; - case UCR4: - return sport->ucr4; - break; - case UFCR: - return sport->ufcr; - break; - default: - return readl(sport->port.membase + offset); - } + return readl(sport->port.membase + offset); } static inline unsigned imx_uart_uts_reg(struct imx_port *sport) @@ -2402,13 +2350,6 @@ static int imx_uart_probe(struct platform_device *pdev) return ret; } - /* initialize shadow register values */ - sport->ucr1 = readl(sport->port.membase + UCR1); - sport->ucr2 = readl(sport->port.membase + UCR2); - sport->ucr3 = readl(sport->port.membase + UCR3); - sport->ucr4 = readl(sport->port.membase + UCR4); - sport->ufcr = readl(sport->port.membase + UFCR); - ret = uart_get_rs485_mode(&sport->port); if (ret) { clk_disable_unprepare(sport->clk_ipg); -- 2.7.4