From f2d3c02aa02309b6bd102066f4961451fbcfc1bb Mon Sep 17 00:00:00 2001 From: Hartmut Penner Date: Fri, 21 Sep 2001 11:41:43 +0000 Subject: [PATCH] s390.md: Changed attributes for scheduling. 2001-09-21 Hartmut Penner * s390.md: Changed attributes for scheduling. * s390.c: (s390_adjust_cost, s390_adjust_priority) Changed scheduling From-SVN: r45725 --- gcc/ChangeLog | 6 + gcc/config/s390/s390.c | 59 ++++-- gcc/config/s390/s390.md | 524 ++++++++++++++++++++---------------------------- 3 files changed, 271 insertions(+), 318 deletions(-) diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 00a5217..4fed3f7 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,9 @@ +2001-09-21 Hartmut Penner + + * s390.md: Changed attributes for scheduling. + * s390.c: (s390_adjust_cost, s390_adjust_priority) + Changed scheduling + 2001-09-21 Joseph S. Myers Table-driven attributes. diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 425c98e..e4bc735 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -46,6 +46,7 @@ Boston, MA 02111-1307, USA. */ static int s390_adjust_cost PARAMS ((rtx, rtx, rtx, int)); +static int s390_adjust_priority PARAMS ((rtx, int)); #undef TARGET_ASM_FUNCTION_PROLOGUE #define TARGET_ASM_FUNCTION_PROLOGUE s390_function_prologue @@ -62,6 +63,9 @@ static int s390_adjust_cost PARAMS ((rtx, rtx, rtx, int)); #undef TARGET_SCHED_ADJUST_COST #define TARGET_SCHED_ADJUST_COST s390_adjust_cost +#undef TARGET_SCHED_ADJUST_PRIORITY +#define TARGET_SCHED_ADJUST_PRIORITY s390_adjust_priority + struct gcc_target targetm = TARGET_INITIALIZER; extern int reload_completed; @@ -1587,7 +1591,9 @@ addr_generation_dependency_p (dep_rtx, insn) Data dependencies are all handled without delay. However, if a register is modified and subsequently used as base or index register of a memory reference, at least 4 cycles need to pass - between setting and using the register to avoid pipeline stalls. */ + between setting and using the register to avoid pipeline stalls. + A exception is the LA instruction. A address generated by LA can + be used by introducing only a one cycle stall on the pipeline. */ static int s390_adjust_cost (insn, link, dep_insn, cost) @@ -1610,19 +1616,13 @@ s390_adjust_cost (insn, link, dep_insn, cost) if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) return cost; - /* If cost equal 1 nothing needs to be checked. */ - - if (cost == 1) - { - return cost; - } - dep_rtx = PATTERN (dep_insn); if (GET_CODE (dep_rtx) == SET) { if (addr_generation_dependency_p (dep_rtx, insn)) { + cost += (get_attr_type (dep_insn) == TYPE_LA) ? 1 : 4; if (DEBUG_SCHED) { fprintf (stderr, "\n\nAddress dependency detected: cost %d\n", @@ -1630,10 +1630,8 @@ s390_adjust_cost (insn, link, dep_insn, cost) debug_rtx (dep_insn); debug_rtx (insn); } - return cost; } } - else if (GET_CODE (dep_rtx) == PARALLEL) { for (i = 0; i < XVECLEN (dep_rtx, 0); i++) @@ -1641,6 +1639,7 @@ s390_adjust_cost (insn, link, dep_insn, cost) if (addr_generation_dependency_p (XVECEXP (dep_rtx, 0, i), insn)) { + cost += (get_attr_type (dep_insn) == TYPE_LA) ? 1 : 4; if (DEBUG_SCHED) { fprintf (stderr, "\n\nAddress dependency detected: cost %d\n" @@ -1648,15 +1647,49 @@ s390_adjust_cost (insn, link, dep_insn, cost) debug_rtx (dep_insn); debug_rtx (insn); } - return cost; } } } - /* default cost. */ - return 1; + return cost; +} + + +/* A C statement (sans semicolon) to update the integer scheduling priority + INSN_PRIORITY (INSN). Reduce the priority to execute the INSN earlier, + increase the priority to execute INSN later. Do not define this macro if + you do not need to adjust the scheduling priorities of insns. + + A LA instruction maybe scheduled later, since the pipeline bypasses the + calculated value. */ + +static int +s390_adjust_priority (insn, priority) + rtx insn ATTRIBUTE_UNUSED; + int priority; +{ + if (! INSN_P (insn)) + return priority; + + if (GET_CODE (PATTERN (insn)) == USE + || GET_CODE (PATTERN (insn)) == CLOBBER) + return priority; + + switch (get_attr_type (insn)) + { + default: + break; + + case TYPE_LA: + if (priority >= 0 && priority < 0x01000000) + priority <<= 3; + break; + } + + return priority; } + /* Pool concept for Linux 390: - Function prologue saves used register - literal pool is dumped in prologue and jump across with bras diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index f17bf5c..853ac9b 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -49,80 +49,62 @@ ;; Insn type. Used to default other attribute values. -; -; Insn are devide in two classes: -; mem: Use of base and/or index register for address generation -; reg: Use of second and third register not for address generation -; -(define_attr "atype" "mem,reg" (const_string "reg")) +;; Define an insn type attribute. This is used in function unit delay +;; computations. -; -; Insn may take 1,2,3 or many cycles -; For the scheduling it does not matter, if a instruction has -; a issue_delay from 4 or more cycles, since the address dependency -; between two insns needs at least 4 cycles. -; +(define_attr "type" "integer,load,lr,la,store,imul,lmul,fmul,idiv,ldiv,fdiv,branch,jsr,other,o2,o3" + (const_string "integer")) -(define_attr "cycle" "1,2,3,n" (const_string "1")) +;; Insn are devide in two classes: +;; mem: Insn accesssing memory +;; reg: Insn operands all in registers -; -; There are three classes of insns: -; set: instruction setting a (potential) address relevant register -; xset: instruction setting no address relevant register -; la: instruction setting a (potential) address relevant register, -; but behave 'better' on the pipeline -; +(define_attr "atype" "reg,mem" + (const_string "reg")) -(define_attr "type" "set,xset,la" (const_string "xset")) +;; Generic pipeline function unit. -; -; Set operations changing a target register, which could be used for -; address generation. Adjust cost will check, if realy applicable. -; +(define_function_unit "integer" 1 0 + (eq_attr "type" "integer") 1 1) -(define_function_unit "memory" 1 0 - (and (eq_attr "type" "set") - (eq_attr "cycle" "1")) - 5 1 [(eq_attr "atype" "mem")] ) +(define_function_unit "integer" 1 0 + (eq_attr "type" "load") 1 1) -(define_function_unit "memory" 1 0 - (and (eq_attr "type" "set") - (eq_attr "cycle" "2")) 5 2) +(define_function_unit "integer" 1 0 + (eq_attr "type" "la") 1 1) -(define_function_unit "memory" 1 0 - (and (eq_attr "type" "set") - (eq_attr "cycle" "3")) 5 3) +(define_function_unit "integer" 1 0 + (eq_attr "type" "lr") 1 1) -(define_function_unit "memory" 1 0 - (and (eq_attr "type" "set") - (eq_attr "cycle" "n")) 5 4) +(define_function_unit "integer" 1 0 + (eq_attr "type" "store") 1 1) -(define_function_unit "memory" 1 0 - (eq_attr "type" "la") 2 1) +(define_function_unit "integer" 1 0 + (eq_attr "type" "jsr") 5 5) -; -; xset insns, which don't set any valid address register. -; Only the issue delay matters. -; +(define_function_unit "integer" 1 0 + (eq_attr "type" "imul") 7 7) + +(define_function_unit "integer" 1 0 + (eq_attr "type" "fmul") 6 6) -(define_function_unit "memory" 1 0 - (and (eq_attr "type" "xset") - (eq_attr "cycle" "1")) 1 1) +(define_function_unit "integer" 1 0 + (eq_attr "type" "idiv") 33 33) -(define_function_unit "memory" 1 0 - (and (eq_attr "type" "xset") - (eq_attr "cycle" "2")) 1 2) +(define_function_unit "integer" 1 0 + (eq_attr "type" "fdiv") 33 33) -(define_function_unit "memory" 1 0 - (and (eq_attr "type" "xset") - (eq_attr "cycle" "3")) 1 3) +(define_function_unit "integer" 1 0 + (eq_attr "type" "o2") 2 2) -(define_function_unit "memory" 1 0 - (and (eq_attr "type" "xset") - (eq_attr "cycle" "n")) 1 4) +(define_function_unit "integer" 1 0 + (eq_attr "type" "o3") 3 3) -; Operand type. Used to default length attribute values +(define_function_unit "integer" 1 0 + (eq_attr "type" "other") 5 5) + +;; Operand type. Used to default length attribute values (define_attr "op_type" "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE" @@ -150,7 +132,7 @@ ;; Define attributes for `asm' insns. -(define_asm_attributes [(set_attr "type" "xset") +(define_asm_attributes [(set_attr "type" "other") (set_attr "op_type" "NN")]) ;; @@ -279,7 +261,7 @@ return \"tmhh\\t%0,%x1\"; }" [(set_attr "op_type" "RX") - (set_attr "type" "xset")]) + (set_attr "type" "integer")]) (define_insn "*cmpdi_tm" @@ -319,7 +301,7 @@ return \"tmll\\t%0,%x1\"; }" [(set_attr "op_type" "RX") - (set_attr "type" "xset")]) + (set_attr "type" "integer")]) (define_insn "*ltgr" @@ -331,7 +313,7 @@ "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" "ltgr\\t%2,%0" [(set_attr "op_type" "RRE") - (set_attr "type" "set")]) + (set_attr "type" "integer")]) (define_insn "*cmpdi_ccs_0_64" [(set (reg 33) @@ -340,7 +322,7 @@ "s390_match_ccmode(insn, CCSmode) && TARGET_64BIT" "ltgr\\t%0,%0" [(set_attr "op_type" "RRE") - (set_attr "type" "set")]) + (set_attr "type" "integer")]) (define_insn "*cmpdi_ccs_0_31" [(set (reg 33) @@ -349,7 +331,7 @@ "s390_match_ccmode(insn, CCSmode)" "srda\\t%0,0" [(set_attr "op_type" "RS") - (set_attr "type" "set")]) + (set_attr "type" "integer")]) (define_insn "*cmpdi_ccs" [(set (reg 33) @@ -403,8 +385,7 @@ operands[1] = GEN_INT (1 << (15 - INTVAL(operands[2]))); return \"tmh\\t%0,%x1\"; }" - [(set_attr "op_type" "RI") - (set_attr "type" "xset")]) + [(set_attr "op_type" "RI")]) (define_insn "*cmpsi_tm" [(set (reg 33) @@ -430,9 +411,7 @@ } return \"tml\\t%0,%x1\"; }" - [(set_attr "op_type" "RX") - (set_attr "type" "xset")]) - + [(set_attr "op_type" "RX")]) (define_insn "*ltr" [(set (reg 33) @@ -442,8 +421,7 @@ (match_dup 0))] "s390_match_ccmode(insn, CCSmode)" "ltr\\t%2,%0" - [(set_attr "op_type" "RR") - (set_attr "type" "set")]) + [(set_attr "op_type" "RR")]) (define_insn "*icm15" [(set (reg 33) @@ -454,8 +432,7 @@ "s390_match_ccmode(insn, CCSmode)" "icm\\t%2,15,%0" [(set_attr "op_type" "RS") - (set_attr "atype" "mem") - (set_attr "type" "set")]) + (set_attr "atype" "mem")]) (define_insn "*icm15_cconly" [(set (reg 33) @@ -465,8 +442,7 @@ "s390_match_ccmode(insn, CCSmode)" "icm\\t%2,15,%0" [(set_attr "op_type" "RS") - (set_attr "atype" "mem") - (set_attr "type" "set")]) + (set_attr "atype" "mem")]) (define_insn "*cmpsi_ccs_0" [(set (reg 33) @@ -474,8 +450,7 @@ (match_operand:SI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode)" "ltr\\t%0,%0" - [(set_attr "op_type" "RR") - (set_attr "type" "set")]) + [(set_attr "op_type" "RR")]) (define_insn "*cmpsidi_ccs" [(set (reg 33) @@ -484,8 +459,7 @@ "s390_match_ccmode(insn, CCSmode)" "ch\\t%0,%1" [(set_attr "op_type" "RR") - (set_attr "atype" "mem") - (set_attr "type" "xset")]) + (set_attr "atype" "mem")]) (define_insn "*cmpsi_ccs" [(set (reg 33) @@ -497,8 +471,7 @@ chi\\t%0,%c1 c\\t%0,%1" [(set_attr "op_type" "RR,RI,RX") - (set_attr "atype" "reg,reg,mem") - (set_attr "type" "xset,xset,xset")]) + (set_attr "atype" "reg,reg,mem")]) (define_insn "*cmpsi_ccu" [(set (reg 33) @@ -518,9 +491,7 @@ "s390_match_ccmode(insn, CCUmode)" "clc\\t%O0(4,%R0),%1" [(set_attr "op_type" "SS") - (set_attr "atype" "mem") - (set_attr "type" "xset")]) - + (set_attr "atype" "mem")]) ; HI instructions @@ -533,8 +504,7 @@ "s390_match_ccmode(insn, CCSmode)" "icm\\t%2,3,%0" [(set_attr "op_type" "RS") - (set_attr "atype" "mem") - (set_attr "type" "set")]) + (set_attr "atype" "mem")]) (define_insn "*cmphi_cct_0" [(set (reg 33) @@ -542,8 +512,7 @@ (match_operand:HI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCTmode)" "tml\\t%0,65535" - [(set_attr "op_type" "RX") - (set_attr "type" "xset")]) + [(set_attr "op_type" "RX")]) (define_insn "*cmphi_ccs_0" [(set (reg 33) @@ -553,8 +522,7 @@ "s390_match_ccmode(insn, CCSmode)" "icm\\t%2,3,%0" [(set_attr "op_type" "RS") - (set_attr "atype" "mem") - (set_attr "type" "set")]) + (set_attr "atype" "mem")]) (define_insn "*cmphi_ccu" [(set (reg 33) @@ -563,8 +531,7 @@ "s390_match_ccmode(insn, CCUmode)" "clm\\t%0,3,%1" [(set_attr "op_type" "RS") - (set_attr "atype" "mem") - (set_attr "type" "xset")]) + (set_attr "atype" "mem")]) (define_insn "*cmphi_ccu_mem" [(set (reg 33) @@ -573,8 +540,7 @@ "s390_match_ccmode(insn, CCUmode)" "clc\\t%O0(2,%R0),%1" [(set_attr "op_type" "SS") - (set_attr "atype" "mem") - (set_attr "type" "xset")]) + (set_attr "atype" "mem")]) ; QI instructions @@ -588,8 +554,7 @@ "s390_match_ccmode(insn, CCSmode)" "icm\\t%2,1,%0" [(set_attr "op_type" "RS") - (set_attr "atype" "mem") - (set_attr "type" "set")]) + (set_attr "atype" "mem")]) (define_insn "*tm_0" [(set (reg 33) @@ -600,8 +565,7 @@ INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256" "tm\\t%0,%1" [(set_attr "op_type" "RI") - (set_attr "atype" "mem") - (set_attr "type" "xset")]) + (set_attr "atype" "mem")]) (define_insn "*cmpqi_cct_0" [(set (reg 33) @@ -609,8 +573,7 @@ (match_operand:QI 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCTmode)" "tml\\t%0,255" - [(set_attr "op_type" "RI") - (set_attr "type" "xset")]) + [(set_attr "op_type" "RI")]) (define_insn "*cmpqi_ccs_0" [(set (reg 33) @@ -619,8 +582,7 @@ (clobber (match_scratch:QI 2 "=d"))] "s390_match_ccmode(insn, CCSmode)" "icm\\t%2,1,%0" - [(set_attr "op_type" "RS") - (set_attr "type" "xset")]) + [(set_attr "op_type" "RS")]) (define_insn "*cmpqi_ccu_0" [(set (reg 33) @@ -629,8 +591,7 @@ "s390_match_ccmode(insn, CCUmode)" "cli\\t%0,0" [(set_attr "op_type" "SI") - (set_attr "atype" "mem") - (set_attr "type" "xset")]) + (set_attr "atype" "mem")]) (define_insn "*cmpqi_ccu" [(set (reg 33) @@ -639,8 +600,7 @@ "s390_match_ccmode(insn, CCUmode)" "clm\\t%0,1,%1" [(set_attr "op_type" "RS") - (set_attr "atype" "mem") - (set_attr "type" "xset")]) + (set_attr "atype" "mem")]) (define_insn "*cmpqi_ccu_immed" [(set (reg 33) @@ -650,8 +610,7 @@ INTVAL(operands[1]) >= 0 && INTVAL(operands[1]) < 256" "cli\\t%0,%1" [(set_attr "op_type" "SI") - (set_attr "atype" "mem") - (set_attr "type" "xset")]) + (set_attr "atype" "mem")]) (define_insn "*cmpqi_ccu_mem" [(set (reg 33) @@ -660,8 +619,7 @@ "s390_match_ccmode(insn, CCUmode)" "clc\\t%O0(1,%R0),%1" [(set_attr "op_type" "SS") - (set_attr "atype" "mem") - (set_attr "type" "xset")]) + (set_attr "atype" "mem")]) ; DF instructions @@ -672,8 +630,7 @@ (match_operand:DF 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "ltdbr\\t%0,%0" - [(set_attr "op_type" "RR") - (set_attr "type" "set")]) + [(set_attr "op_type" "RR")]) (define_insn "*cmpdf_ccs_0_ibm" [(set (reg 33) @@ -681,8 +638,7 @@ (match_operand:DF 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "ltdr\\t%0,%0" - [(set_attr "op_type" "RR") - (set_attr "type" "set")]) + [(set_attr "op_type" "RR")]) (define_insn "*cmpdf_ccs" [(set (reg 33) @@ -693,8 +649,7 @@ cdbr\\t%0,%1 cdb\\t%0,%1" [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem") - (set_attr "type" "xset,xset")]) + (set_attr "atype" "reg,mem")]) (define_insn "*cmpdf_ccs_ibm" [(set (reg 33) @@ -705,8 +660,7 @@ cdr\\t%0,%1 cd\\t%0,%1" [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem") - (set_attr "type" "xset,xset")]) + (set_attr "atype" "reg,mem")]) ; SF instructions @@ -717,8 +671,7 @@ (match_operand:SF 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "ltebr\\t%0,%0" - [(set_attr "op_type" "RR") - (set_attr "type" "set")]) + [(set_attr "op_type" "RR")]) (define_insn "*cmpsf_ccs_0_ibm" [(set (reg 33) @@ -726,8 +679,7 @@ (match_operand:SF 1 "const0_operand" "")))] "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT && TARGET_IBM_FLOAT" "lter\\t%0,%0" - [(set_attr "op_type" "RR") - (set_attr "type" "set")]) + [(set_attr "op_type" "RR")]) (define_insn "*cmpsf_ccs" [(set (reg 33) @@ -738,8 +690,7 @@ cebr\\t%0,%1 ceb\\t%0,%1" [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem") - (set_attr "type" "xset,xset")]) + (set_attr "atype" "reg,mem")]) (define_insn "*cmpsf_ccs" [(set (reg 33) @@ -750,8 +701,7 @@ cer\\t%0,%1 ce\\t%0,%1" [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem") - (set_attr "type" "xset,xset")]) + (set_attr "atype" "reg,mem")]) ;; @@ -803,7 +753,7 @@ }" [(set_attr "op_type" "NN,NN,RS,RS,SS") (set_attr "atype" "reg,reg,mem,mem,mem") - (set_attr "type" "set") + (set_attr "type" "o2") (set_attr "length" "12,8,10,10,*")]) ; @@ -839,8 +789,8 @@ stg\\t%1,%0 mvc\\t%O0(8,%R0),%1" [(set_attr "op_type" "RRE,RI,RIL,RXE,RXE,SS") - (set_attr "atype" "reg,reg,reg,mem,mem,mem") - (set_attr "type" "set,set,la,set,set,set")]) + (set_attr "type" "integer,integer,la,integer,integer,integer") + (set_attr "atype" "reg,reg,reg,mem,mem,mem")]) (define_insn "*movdi_31" [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,m,Q") @@ -883,7 +833,7 @@ }" [(set_attr "op_type" "NN,NN,RS,RS,SS") (set_attr "atype" "reg,reg,mem,mem,mem") - (set_attr "type" "set") + (set_attr "type" "o2") (set_attr "length" "4,8,8,8,*")]) @@ -919,8 +869,8 @@ st\\t%1,%0 mvc\\t%O0(4,%R0),%1" [(set_attr "op_type" "RR,RI,RX,RX,SS") - (set_attr "atype" "reg,reg,mem,mem,mem") - (set_attr "type" "set")]) + (set_attr "type" "lr,*,load,store,store") + (set_attr "atype" "reg,reg,mem,mem,mem")]) ; @@ -937,9 +887,7 @@ lh\\t%0,%1 sth\\t%1,%0" [(set_attr "op_type" "RR,RI,RX,RX") - (set_attr "atype" "reg,reg,mem,mem") - (set_attr "type" "xset")]) - + (set_attr "atype" "reg,reg,mem,mem")]) ; ; movqi instruction pattern(s). @@ -956,9 +904,7 @@ stc\\t%1,%0 mvi\\t%0,%b1" [(set_attr "op_type" "RR,RI,RXE,RX,SI") - (set_attr "atype" "reg,reg,mem,mem,mem") - (set_attr "type" "xset")]) - + (set_attr "atype" "reg,reg,mem,mem,mem")]) (define_insn "movqi" [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,m,Q") @@ -971,9 +917,7 @@ stc\\t%1,%0 mvi\\t%0,%b1" [(set_attr "op_type" "RR,RX,RX,RX,SI") - (set_attr "atype" "reg,reg,mem,mem,mem") - (set_attr "type" "xset")]) - + (set_attr "atype" "reg,reg,mem,mem,mem")]) ; ; moveqstrictqi instruction pattern(s). @@ -1003,8 +947,7 @@ icm\\t%0,3,%1 stcm\\t%1,3,%0" [(set_attr "op_type" "RS,RS") - (set_attr "atype" "mem") - (set_attr "type" "xset")]) + (set_attr "atype" "mem")]) ; @@ -1020,8 +963,7 @@ l\\t%0,%1 st\\t%1,%0" [(set_attr "op_type" "RR,RS,RS") - (set_attr "atype" "reg,mem,mem") - (set_attr "type" "xset")]) + (set_attr "atype" "reg,mem,mem")]) ; @@ -1051,8 +993,7 @@ lgr\\t%0,%1 mvc\\t%O0(8,%R0),%1" [(set_attr "op_type" "RR,RX,RX,RXE,RXE,RR,SS") - (set_attr "atype" "reg,mem,mem,mem,mem,mem,mem") - (set_attr "type" "xset")]) + (set_attr "atype" "reg,mem,mem,mem,mem,mem,mem")]) (define_insn "*movdf_31" [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,m,d,m,d,Q") @@ -1110,8 +1051,7 @@ lgr\\t%0,%1 mvc\\t%O0(8,%R0),%1" [(set_attr "op_type" "RXE,RXE,RR,SS") - (set_attr "atype" "mem,mem,mem,mem") - (set_attr "type" "xset")]) + (set_attr "atype" "mem,mem,mem,mem")]) (define_insn "*movdf_soft_31" [(set (match_operand:DF 0 "nonimmediate_operand" "=!d,d,m,Q") @@ -1261,8 +1201,7 @@ return \"lmg\\t%1,%0,%2\"; }" [(set_attr "op_type" "RXE") - (set_attr "atype" "mem") - (set_attr "type" "set")]) + (set_attr "atype" "mem")]) (define_insn "*load_multiple_si" [(match_parallel 0 "load_multiple_operation" @@ -1280,8 +1219,7 @@ return \"lm\\t%1,%0,%2\"; }" [(set_attr "op_type" "RXE") - (set_attr "atype" "mem") - (set_attr "type" "set")]) + (set_attr "atype" "mem")]) ; ; store multiple pattern(s). @@ -1340,7 +1278,7 @@ }" [(set_attr "op_type" "RXE") (set_attr "atype" "mem") - (set_attr "type" "xset")]) + (set_attr "type" "other")]) (define_insn "*store_multiple_si" @@ -1360,7 +1298,7 @@ }" [(set_attr "op_type" "RXE") (set_attr "atype" "mem") - (set_attr "type" "xset")]) + (set_attr "type" "other")]) ;; ;; String instructions. @@ -1739,7 +1677,7 @@ "mvcle\\t%0,%1,0\;jo\\t.-4" [(set_attr "op_type" "NN") (set_attr "atype" "mem") - (set_attr "cycle" "n") + (set_attr "type" "other") (set_attr "length" "8")]) (define_insn "clrstrsi_31" @@ -1753,7 +1691,7 @@ "mvcle\\t%0,%1,0\;jo\\t.-4" [(set_attr "op_type" "NN") (set_attr "atype" "mem") - (set_attr "cycle" "n") + (set_attr "type" "other") (set_attr "length" "8")]) ; @@ -1905,7 +1843,7 @@ "clc\\t%O0(%c2,%R0),%1" [(set_attr "op_type" "SS") (set_attr "atype" "mem") - (set_attr "type" "xset")]) + (set_attr "type" "other")]) ; Compare a block that is larger than 255 bytes in length. @@ -1921,7 +1859,7 @@ "clcl\\t%0,%1" [(set_attr "op_type" "RR") (set_attr "atype" "mem") - (set_attr "type" "xset")]) + (set_attr "type" "other")]) (define_insn "cmpstr_31" [(set (reg:CCU 33) @@ -1935,7 +1873,7 @@ "clcl\\t%0,%1" [(set_attr "op_type" "RR") (set_attr "atype" "mem") - (set_attr "type" "xset")]) + (set_attr "type" "other")]) ; Convert condition code to integer in range (-1, 0, 1) @@ -1954,7 +1892,7 @@ [(set_attr "op_type" "NN") (set_attr "length" "16") (set_attr "atype" "reg") - (set_attr "type" "xset")]) + (set_attr "type" "other")]) (define_insn "cmpint_di" [(set (match_operand:DI 0 "register_operand" "=d") @@ -1971,7 +1909,7 @@ [(set_attr "op_type" "NN") (set_attr "length" "22") (set_attr "atype" "reg") - (set_attr "type" "xset")]) + (set_attr "type" "other")]) ;; ;;- Conversion instructions. @@ -1989,8 +1927,7 @@ lgfr\\t%0,%1 lgf\\t%0,%1" [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,mem")]) ; @@ -2005,9 +1942,7 @@ "sllg\\t%0,%1,48\;srag\\t%0,%0,48" [(set_attr "op_type" "NN") (set_attr "length" "12") - (set_attr "cycle" "2") - (set_attr "type" "set")]) - + (set_attr "type" "o2")]) ; ; extendqidi2 instruction pattern(s). @@ -2021,9 +1956,7 @@ "sllg\\t%0,%1,56\;srag\\t%0,%0,56" [(set_attr "op_type" "NN") (set_attr "length" "12") - (set_attr "cycle" "2") - (set_attr "type" "set")]) - + (set_attr "type" "o2")]) ; ; extendhisi2 instruction pattern(s). @@ -2039,9 +1972,8 @@ lr\\t%0,%1\;sll\\t%0,16\;sra\\t%0,16 lh\\t%0,%1" [(set_attr "op_type" "NN,NN,RX") - (set_attr "cycle" "2,3,1") + (set_attr "type" "o2,o3,integer") (set_attr "atype" "reg,reg,mem") - (set_attr "type" "set") (set_attr "length" "8,10,*")]) @@ -2058,9 +1990,8 @@ sll\\t%0,24\;sra\\t%0,24 icm\\t%0,8,%1\;sra\\t%0,24" [(set_attr "op_type" "NN,NN") - (set_attr "cycle" "2") + (set_attr "type" "o2") (set_attr "atype" "reg,mem") - (set_attr "type" "set") (set_attr "length" "8,8")]) @@ -2077,9 +2008,8 @@ sll\\t%0,24\;sra\\t%0,24 icm\\t%0,8,%1\;sra\\t%0,24" [(set_attr "op_type" "NN,NN") - (set_attr "cycle" "2") + (set_attr "type" "o2") (set_attr "atype" "reg,mem") - (set_attr "type" "set") (set_attr "length" "8,8")]) @@ -2095,8 +2025,7 @@ llgfr\\t%0,%1 llgf\\t%0,%1" [(set_attr "op_type" "RRE,RXE") - (set_attr "atype" "reg,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,mem")]) ; @@ -2111,11 +2040,9 @@ llgfr\\t%0,%1\;iilh\\t%0,0 llgh\\t%0,%1" [(set_attr "op_type" "NN,RXE") - (set_attr "cycle" "2,1") + (set_attr "type" "o2,integer") (set_attr "atype" "reg,mem") - (set_attr "length" "12,*") - (set_attr "type" "set")]) - + (set_attr "length" "12,*")]) ; ; zero_extendqidi2 instruction pattern(s) @@ -2130,9 +2057,8 @@ sllg\\t%0,%1,56\;srlg\\t%0,%0,56 llgc\\t%0,%1" [(set_attr "op_type" "NN,RXE") - (set_attr "cycle" "2,1") + (set_attr "type" "o2,integer") (set_attr "atype" "reg,mem") - (set_attr "type" "set") (set_attr "length" "12,*")]) @@ -2174,9 +2100,8 @@ icm\\t%0,12,%2 icm\\t%0,12,%1\;srl\\t%0,16" [(set_attr "op_type" "RX,NN") - (set_attr "cycle" "1,2") + (set_attr "type" "integer,o2") (set_attr "atype" "reg,mem") - (set_attr "type" "set") (set_attr "length" "*,8")]) @@ -2192,9 +2117,8 @@ "" "sr\\t%0,%0\;ic\\t%0,%1" [(set_attr "op_type" "NN") - (set_attr "cycle" "2") + (set_attr "type" "o2") (set_attr "atype" "mem") - (set_attr "type" "set") (set_attr "length" "6")]) (define_insn "zero_extendqisi2_reg_31" @@ -2205,8 +2129,7 @@ "" "icm\\t%0,14,%2" [(set_attr "op_type" "RX") - (set_attr "atype" "mem") - (set_attr "type" "set")]) + (set_attr "atype" "mem")]) (define_insn "*zero_extendqisi2_64" [(set (match_operand:SI 0 "register_operand" "=!d,d") @@ -2216,7 +2139,7 @@ sllg\\t%0,%1,56\;srlg\\t%0,%0,56 llgc\\t%0,%1" [(set_attr "op_type" "NN,RXE") - (set_attr "cycle" "2,1") + (set_attr "type" "o2,integer") (set_attr "atype" "reg,mem") (set_attr "length" "12,*")]) @@ -2319,7 +2242,7 @@ "TARGET_64BIT" "sllg\\t%0,%1,56\;srlg\\t%0,%0,56" [(set_attr "op_type" "NN") - (set_attr "cycle" "2") + (set_attr "type" "o2") (set_attr "length" "12")]) @@ -2370,7 +2293,7 @@ "TARGET_64BIT" "iilh\\t%0,0\;nill\\t%0,0x00FF" [(set_attr "op_type" "NN") - (set_attr "cycle" "2") + (set_attr "type" "o2") (set_attr "length" "8")]) @@ -2436,7 +2359,7 @@ "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "cgdbr\\t%0,%h2,%1" [(set_attr "op_type" "RRE") - (set_attr "cycle" "n")]) + (set_attr "type" "other")]) ; ; fixuns_truncdfsi2 and fix_truncdfsi2 instruction pattern(s). @@ -2506,7 +2429,7 @@ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "cfdbr\\t%0,%h2,%1" [(set_attr "op_type" "RRE") - (set_attr "cycle" "n" )]) + (set_attr "type" "other" )]) (define_insn "fix_truncdfsi2_ibm" [(set (match_operand:SI 0 "register_operand" "=d") @@ -2525,7 +2448,7 @@ return \"l\\t%0,%N4\"; }" [(set_attr "op_type" "NN") - (set_attr "cycle" "n") + (set_attr "type" "other") (set_attr "length" "20")]) ; @@ -2577,7 +2500,7 @@ "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "cgebr\\t%0,%h2,%1" [(set_attr "op_type" "RRE") - (set_attr "cycle" "n")]) + (set_attr "type" "other")]) ; ; fixuns_truncsfsi2 and fix_truncsfsi2 instruction pattern(s). @@ -2638,7 +2561,7 @@ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "cfebr\\t%0,%h2,%1" [(set_attr "op_type" "RRE") - (set_attr "cycle" "n")]) + (set_attr "type" "other")]) ; ; floatdidf2 instruction pattern(s). @@ -2650,7 +2573,7 @@ "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "cdgbr\\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "cycle" "n" )]) + (set_attr "type" "other" )]) ; ; floatdisf2 instruction pattern(s). @@ -2662,7 +2585,7 @@ "TARGET_64BIT && TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "cegbr\\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "cycle" "n" )]) + (set_attr "type" "other" )]) ; ; floatsidf2 instruction pattern(s). @@ -2694,7 +2617,7 @@ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "cdfbr\\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "cycle" "n" )]) + (set_attr "type" "other" )]) (define_insn "floatsidf2_ibm" [(set (match_operand:DF 0 "register_operand" "=f") @@ -2712,7 +2635,7 @@ return \"sd\\t%0,%2\"; }" [(set_attr "op_type" "NN") - (set_attr "cycle" "n" ) + (set_attr "type" "other" ) (set_attr "length" "20")]) ; @@ -2741,7 +2664,7 @@ "TARGET_HARD_FLOAT && TARGET_IEEE_FLOAT" "cefbr\\t%0,%1" [(set_attr "op_type" "RRE") - (set_attr "cycle" "n" )]) + (set_attr "type" "other" )]) ; ; truncdfsf2 instruction pattern(s). @@ -2851,8 +2774,7 @@ aghi\\t%0,%h2 ag\\t%0,%2" [(set_attr "op_type" "RRE,RI,RXE") - (set_attr "atype" "reg,reg,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,reg,mem")]) ; ; For weakness of reload, need (set (reg x) (plus (reg y) (reg x))) @@ -2869,8 +2791,7 @@ aghi\\t%0,%h1 ag\\t%0,%1" [(set_attr "op_type" "RRE,RI,RXE") - (set_attr "atype" "reg,reg,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,reg,mem")]) (define_insn "adddi3_31" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -2930,8 +2851,7 @@ "TARGET_64BIT" "brxlg\\t%0,%2,.+6" [(set_attr "op_type" "RIE") - (set_attr "atype" "reg") - (set_attr "type" "set")]) + (set_attr "atype" "reg")]) (define_insn "*reload_la_64" [(set (match_operand:DI 0 "register_operand" "=d") @@ -3029,8 +2949,7 @@ ahi\\t%0,%h2 a\\t%0,%2" [(set_attr "op_type" "RR,RI,RX") - (set_attr "atype" "reg,reg,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,reg,mem")]) (define_insn "*addsi3_cconly" [(set (reg 33) @@ -3044,8 +2963,7 @@ ahi\\t%0,%h2 a\\t%0,%2" [(set_attr "op_type" "RR,RI,RX") - (set_attr "atype" "reg,reg,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,reg,mem")]) (define_insn "*addsi3_cconly2" [(set (reg 33) @@ -3058,8 +2976,7 @@ ahi\\t%0,%h2 a\\t%0,%2" [(set_attr "op_type" "RR,RI,RX") - (set_attr "atype" "reg,reg,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,reg,mem")]) (define_insn "addsi3" [(set (match_operand:SI 0 "register_operand" "=d,d,d") @@ -3072,8 +2989,7 @@ ahi\\t%0,%h2 a\\t%0,%2" [(set_attr "op_type" "RR,RI,RX") - (set_attr "atype" "reg,reg,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,reg,mem")]) (define_insn "do_la" [(set (match_operand:SI 0 "register_operand" "=a") @@ -3091,8 +3007,7 @@ "" "brxle\\t%0,%2,.+4" [(set_attr "op_type" "RSI") - (set_attr "atype" "reg") - (set_attr "type" "set")]) + (set_attr "atype" "reg")]) (define_insn "*reload_la_31" [(set (match_operand:SI 0 "register_operand" "=d") @@ -3265,8 +3180,7 @@ sgr\\t%0,%2 sg\\t%0,%2" [(set_attr "op_type" "RRE,RRE") - (set_attr "atype" "reg,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,mem")]) (define_insn "subdi3" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -3311,8 +3225,7 @@ sr\\t%0,%2 s\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,mem")]) (define_insn "*subsi3_cconly" [(set (reg 33) @@ -3325,8 +3238,7 @@ sr\\t%0,%2 s\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,mem")]) (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=d,d") @@ -3338,8 +3250,7 @@ sr\\t%0,%2 s\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,mem")]) ; ; subhi3 instruction pattern(s). @@ -3469,7 +3380,7 @@ rtx temp1_1 = gen_reg_rtx (SImode); rtx temp2_0 = gen_reg_rtx (SImode); rtx temp2_1 = gen_reg_rtx (SImode); - + emit_move_insn (temp1_0, operand_subword (operands[1], 0 ,1, DImode)); emit_move_insn (temp1_1, operand_subword (operands[1], 1 ,1, DImode)); emit_move_insn (temp2_0, operand_subword (operands[2], 0 ,1, DImode)); @@ -3507,9 +3418,37 @@ mghi\\t%0,%h2 msg\\t%0,%2" [(set_attr "op_type" "RRE,RI,RX") - (set_attr "cycle" "n") (set_attr "atype" "reg,reg,mem") - (set_attr "type" "set")]) + (set_attr "type" "imul")]) + +; +; mulsidi3 instruction pattern(s). +; + +;(define_expand "mulsidi3" +; [(set (match_operand:DI 0 "register_operand" "") +; (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) +; (sign_extend:DI (match_operand:SI 2 "general_operand" ""))))] +; "" +; " +;{ +; emit_insn (gen_extendsidi2 (operands[0], operands[1])); +; emit_insn (gen_muldisidi3 (operands[0], operands[0], operands[2])); +; DONE; +;}") + +;(define_insn "muldisidi3" +; [(set (match_operand:DI 0 "register_operand" "=d,d") +; (mult:DI (match_operand:DI 1 "register_operand" "0,0") +; (sign_extend:DI (match_operand:SI 2 "general_operand" "d,m")))) +; (clobber (reg:CC 33))] +; "!TARGET_64BIT" +; "@ +; mr\\t%0,%2 +; m\\t%0,%2" +; [(set_attr "op_type" "RR,RX") +; (set_attr "atype" "reg,mem") +; (set_attr "type" "imul")]) ; ; mulsi3 instruction pattern(s). @@ -3526,9 +3465,8 @@ mhi\\t%0,%h2 ms\\t%0,%2" [(set_attr "op_type" "RRE,RI,RX") - (set_attr "cycle" "n") (set_attr "atype" "reg,reg,mem") - (set_attr "type" "set")]) + (set_attr "type" "imul")]) (define_insn "mulsi_6432" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -3542,9 +3480,8 @@ mr\\t%0,%2 m\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "cycle" "n") (set_attr "atype" "reg,mem") - (set_attr "type" "set")]) + (set_attr "type" "imul")]) ; @@ -3570,7 +3507,7 @@ mdbr\\t%0,%2 mdb\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "cycle" "n") + (set_attr "type" "fmul") (set_attr "atype" "reg,mem")]) (define_insn "*muldf3_ibm" @@ -3583,7 +3520,7 @@ mdr\\t%0,%2 md\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "cycle" "n") + (set_attr "type" "fmul") (set_attr "atype" "reg,mem")]) ; @@ -3609,7 +3546,7 @@ meebr\\t%0,%2 meeb\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "cycle" "n") + (set_attr "type" "fmul") (set_attr "atype" "reg,mem")]) (define_insn "*mulsf3_ibm" @@ -3622,7 +3559,7 @@ mer\\t%0,%2 me\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "cycle" "n") + (set_attr "type" "fmul") (set_attr "atype" "reg,mem")]) @@ -3686,7 +3623,7 @@ dsgr\\t%0,%2 dsg\\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "cycle" "n") + (set_attr "type" "idiv") (set_attr "atype" "reg,mem")]) ; @@ -3745,7 +3682,7 @@ dlgr\\t%0,%2 dlg\\t%0,%2" [(set_attr "op_type" "RRE,RXE") - (set_attr "cycle" "n") + (set_attr "type" "idiv") (set_attr "atype" "reg,mem")]) ; @@ -3810,7 +3747,7 @@ dr\\t%0,%2 d\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "cycle" "n") + (set_attr "type" "idiv") (set_attr "atype" "reg,mem")]) ; @@ -3972,7 +3909,7 @@ ddbr\\t%0,%2 ddb\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "cycle" "n") + (set_attr "type" "fdiv") (set_attr "atype" "reg,mem")]) (define_insn "*divdf3_ibm" @@ -3985,7 +3922,7 @@ ddr\\t%0,%2 dd\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "cycle" "n") + (set_attr "type" "fdiv") (set_attr "atype" "reg,mem")]) ; @@ -4011,7 +3948,7 @@ debr\\t%0,%2 deb\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "cycle" "n") + (set_attr "type" "fdiv") (set_attr "atype" "reg,mem")]) (define_insn "*divsf3" @@ -4024,7 +3961,7 @@ der\\t%0,%2 de\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "cycle" "n") + (set_attr "type" "fdiv") (set_attr "atype" "reg,mem")]) @@ -4049,8 +3986,7 @@ ng\\t%0,%2 nc\\t%O0(8,%R0),%2" [(set_attr "op_type" "RR,RX,SS") - (set_attr "atype" "reg,mem,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,mem,mem")]) (define_insn "*anddi3_cconly" [(set (reg 33) @@ -4063,8 +3999,7 @@ ngr\\t%0,%2 ng\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,mem")]) (define_insn "anddi3" [(set (match_operand:DI 0 "r_or_s_operand" "=d,d,Q") @@ -4077,8 +4012,7 @@ ng\\t%0,%2 nc\\t%O0(8,%R0),%2" [(set_attr "op_type" "RR,RX,SS") - (set_attr "atype" "reg,mem,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,mem,mem")]) ; ; andsi3 instruction pattern(s). @@ -4097,8 +4031,7 @@ n\\t%0,%2 nc\\t%O0(4,%R0),%2" [(set_attr "op_type" "RR,RX,SS") - (set_attr "atype" "reg,mem,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,mem,mem")]) (define_insn "*andsi3_cconly" [(set (reg 33) @@ -4111,8 +4044,7 @@ nr\\t%0,%2 n\\t%0,%2" [(set_attr "op_type" "RR,RX") - (set_attr "atype" "reg,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,mem")]) (define_insn "andsi3" [(set (match_operand:SI 0 "r_or_s_operand" "=d,d,Q") @@ -4125,8 +4057,7 @@ n\\t%0,%2 nc\\t%O0(4,%R0),%2" [(set_attr "op_type" "RR,RX,SS") - (set_attr "atype" "reg,mem,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,mem,mem")]) ; ; andhi3 instruction pattern(s). @@ -4195,8 +4126,7 @@ oc\\t%O0(8,%R0),%2 oill\\t%0,%2" [(set_attr "op_type" "RRE,RXE,SS,RI") - (set_attr "atype" "reg,mem,mem,reg") - (set_attr "type" "set")]) + (set_attr "atype" "reg,mem,mem,reg")]) ; ; iorsi3 instruction pattern(s). @@ -4226,8 +4156,7 @@ o\\t%0,%2 oc\\t%O0(4,%R0),%2" [(set_attr "op_type" "RR,RX,SS") - (set_attr "atype" "reg,mem,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,mem,mem")]) ; ; iorhi3 instruction pattern(s). @@ -4295,8 +4224,7 @@ xg\\t%0,%2 xc\\t%O0(8,%R0),%2" [(set_attr "op_type" "RRE,RXE,SS") - (set_attr "atype" "reg,mem,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,mem,mem")]) ; ; xorsi3 instruction pattern(s). @@ -4326,8 +4254,7 @@ x\\t%0,%2 xc\\t%O0(4,%R0),%2" [(set_attr "op_type" "RR,RX,SS") - (set_attr "atype" "reg,mem,mem") - (set_attr "type" "set")]) + (set_attr "atype" "reg,mem,mem")]) ; ; xorhi3 instruction pattern(s). @@ -4398,8 +4325,7 @@ (clobber (reg:CC 33))] "TARGET_64BIT" "lcgr\\t%0,%1" - [(set_attr "op_type" "RR") - (set_attr "type" "set")]) + [(set_attr "op_type" "RR")]) (define_insn "*negdi2_31" [(set (match_operand:DI 0 "register_operand" "=d") @@ -4431,8 +4357,7 @@ (clobber (reg:CC 33))] "" "lcr\\t%0,%1" - [(set_attr "op_type" "RR") - (set_attr "type" "set")]) + [(set_attr "op_type" "RR")]) ; ; negdf2 instruction pattern(s). @@ -4505,8 +4430,7 @@ (clobber (reg:CC 33))] "TARGET_64BIT" "lpgr\\t%0,%1" - [(set_attr "op_type" "RRE") - (set_attr "type" "set")]) + [(set_attr "op_type" "RRE")]) ; ; abssi2 instruction pattern(s). @@ -4518,8 +4442,7 @@ (clobber (reg:CC 33))] "" "lpr\\t%0,%1" - [(set_attr "op_type" "RR") - (set_attr "type" "set")]) + [(set_attr "op_type" "RR")]) ; ; abshi2 instruction pattern(s). @@ -4532,7 +4455,7 @@ "" "sll\\t%1,16\;sra\\t%1,16\;lpr\\t%0,%1" [(set_attr "op_type" "NN") - (set_attr "cycle" "3") + (set_attr "type" "o3") (set_attr "length" "10")]) ; @@ -4701,8 +4624,7 @@ "@ rllg\\t%0,%1,%c2 rllg\\t%0,%1,0(%2)" - [(set_attr "op_type" "RSE") - (set_attr "type" "set")]) + [(set_attr "op_type" "RSE")]) ; ; rotlsi3 instruction pattern(s). @@ -4717,8 +4639,7 @@ "@ rll\\t%0,%1,%c2 rll\\t%0,%1,0(%2)" - [(set_attr "op_type" "RSE") - (set_attr "type" "set")]) + [(set_attr "op_type" "RSE")]) ;; @@ -4748,8 +4669,7 @@ "@ sldl\\t%0,%c2 sldl\\t%0,0(%2)" - [(set_attr "op_type" "RS") - (set_attr "type" "set")]) + [(set_attr "op_type" "RS")]) (define_insn "*ashldi3_64" [(set (match_operand:DI 0 "register_operand" "=d,d") @@ -4760,8 +4680,7 @@ "@ sllg\\t%0,%1,%2 sllg\\t%0,%1,0(%2)" - [(set_attr "op_type" "RSE") - (set_attr "type" "set")]) + [(set_attr "op_type" "RSE")]) ; ; ashrdi3 instruction pattern(s). @@ -4796,8 +4715,7 @@ "@ srag\\t%0,%1,%c2 srag\\t%0,%1,0(%2)" - [(set_attr "op_type" "RSE") - (set_attr "type" "set")]) + [(set_attr "op_type" "RSE")]) ; ; ashlsi3 instruction pattern(s). @@ -4813,8 +4731,7 @@ "@ sll\\t%0,%c2 sll\\t%0,0(%2)" - [(set_attr "op_type" "RS") - (set_attr "type" "set")]) + [(set_attr "op_type" "RS")]) ; ; ashrsi3 instruction pattern(s). @@ -4829,8 +4746,7 @@ "@ sra\\t%0,%c2 sra\\t%0,0(%2)" - [(set_attr "op_type" "RS") - (set_attr "type" "set")]) + [(set_attr "op_type" "RS")]) ; ; ashlhi3 instruction pattern(s). @@ -4901,8 +4817,7 @@ "@ srlg\\t%0,%1,%c2 srlg\\t%0,%1,0(%2)" - [(set_attr "op_type" "RS,RS") - (set_attr "type" "set")]) + [(set_attr "op_type" "RS,RS")]) ; ; lshrsi3 instruction pattern(s). @@ -4917,8 +4832,7 @@ "@ srl\\t%0,%c2 srl\\t%0,0(%2)" - [(set_attr "op_type" "RS") - (set_attr "type" "set")]) + [(set_attr "op_type" "RS")]) ; ; lshrhi3 instruction pattern(s). @@ -5368,7 +5282,7 @@ "TARGET_64BIT" "brasl\\t%2,%0" [(set_attr "op_type" "RIL") - (set_attr "cycle" "n")]) + (set_attr "type" "jsr")]) (define_insn "bras" [(call (mem:QI (match_operand:SI 0 "bras_sym_operand" "X")) @@ -5377,7 +5291,7 @@ "TARGET_SMALL_EXEC" "bras\\t%2,%0" [(set_attr "op_type" "RI") - (set_attr "cycle" "n")]) + (set_attr "type" "jsr")]) (define_insn "basr_64" [(call (mem:QI (match_operand:DI 0 "register_operand" "a")) @@ -5386,7 +5300,7 @@ "TARGET_64BIT" "basr\\t%2,%0" [(set_attr "op_type" "RR") - (set_attr "cycle" "n") + (set_attr "type" "jsr") (set_attr "atype" "mem")]) (define_insn "basr_31" @@ -5396,7 +5310,7 @@ "!TARGET_64BIT" "basr\\t%2,%0" [(set_attr "op_type" "RR") - (set_attr "cycle" "n") + (set_attr "type" "jsr") (set_attr "atype" "mem")]) (define_insn "bas_64" @@ -5406,7 +5320,7 @@ "TARGET_64BIT" "bas\\t%2,%a0" [(set_attr "op_type" "RX") - (set_attr "cycle" "n") + (set_attr "type" "jsr") (set_attr "atype" "mem")]) (define_insn "bas_31" @@ -5416,7 +5330,7 @@ "!TARGET_64BIT" "bas\\t%2,%a0" [(set_attr "op_type" "RX") - (set_attr "cycle" "n") + (set_attr "type" "jsr") (set_attr "atype" "mem")]) @@ -5475,7 +5389,7 @@ "TARGET_64BIT" "brasl\\t%3,%1" [(set_attr "op_type" "RIL") - (set_attr "cycle" "n")]) + (set_attr "type" "jsr")]) (define_insn "bras_r" [(set (match_operand 0 "register_operand" "=df") @@ -5485,7 +5399,7 @@ "TARGET_SMALL_EXEC" "bras\\t%3,%1" [(set_attr "op_type" "RI") - (set_attr "cycle" "n")]) + (set_attr "type" "jsr")]) (define_insn "basr_r_64" [(set (match_operand 0 "register_operand" "=df") @@ -5495,7 +5409,7 @@ "TARGET_64BIT" "basr\\t%3,%1" [(set_attr "op_type" "RR") - (set_attr "cycle" "n")]) + (set_attr "type" "jsr")]) (define_insn "basr_r_31" [(set (match_operand 0 "register_operand" "=df") @@ -5505,7 +5419,7 @@ "!TARGET_64BIT" "basr\\t%3,%1" [(set_attr "op_type" "RR") - (set_attr "cycle" "n") + (set_attr "type" "jsr") (set_attr "atype" "mem")]) (define_insn "bas_r_64" @@ -5516,7 +5430,7 @@ "TARGET_64BIT" "bas\\t%3,%a1" [(set_attr "op_type" "RX") - (set_attr "cycle" "n") + (set_attr "type" "jsr") (set_attr "atype" "mem")]) (define_insn "bas_r_31" @@ -5527,7 +5441,7 @@ "!TARGET_64BIT" "bas\\t%3,%a1" [(set_attr "op_type" "RX") - (set_attr "cycle" "n") + (set_attr "type" "jsr") (set_attr "atype" "mem")]) @@ -5720,7 +5634,7 @@ return \"basr\\t13,0\;ahi\\t13,%Y0\"; }" [(set_attr "op_type" "NN") - (set_attr "cycle" "2") + (set_attr "type" "o2") (set_attr "length" "8")]) (define_insn "ltorg" @@ -5733,7 +5647,7 @@ return \"0:\"; }" [(set_attr "op_type" "NN") - (set_attr "cycle" "n") + (set_attr "type" "branch") (set_attr "length" "4096")]) -- 2.7.4