From f2cd2e5d861245dbf40e9b919e4734123164d8f4 Mon Sep 17 00:00:00 2001 From: Sung Lee Date: Mon, 30 Mar 2020 17:19:01 -0400 Subject: [PATCH] drm/amd/display: Set meta_chunk_value to 0 in DML if DCC disabled in DCN2.1 [WHY]: Calculating refcyc_per_meta_chunk_vblank_l when DCC is disabled may lead to a large number causing an assert to get hit. In VBA, this value is 0 when DCC is disabled. [HOW]: Set value to 0 to avoid hitting the assert. Signed-off-by: Sung Lee Reviewed-by: Dmytro Laktyushkin Acked-by: Rodrigo Siqueira Signed-off-by: Alex Deucher --- drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c index a38baa7..5430ced 100644 --- a/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c +++ b/drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c @@ -1500,9 +1500,12 @@ static void dml_rq_dlg_get_dlg_params( < (unsigned int)dml_pow(2, 13)); } - disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = + if (src->dcc) + disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = (unsigned int) (dst_y_per_row_vblank * (double) htotal * ref_freq_to_pix_freq / (double) meta_chunks_per_row_ub_l); + else + disp_dlg_regs->refcyc_per_meta_chunk_vblank_l = 0; ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13)); disp_dlg_regs->refcyc_per_meta_chunk_vblank_c = -- 2.7.4