From f2c1b1a7f54ee74018d369f449a26e3d0cce5806 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Tue, 7 Mar 2023 19:52:57 -0800 Subject: [PATCH] [RISCV] Add test case for Zfa fli.s miscompile. NFC The f32 matching code for fli was hacked to allow the f16 minimum value to match for the fli.h instruction in the assembler. This was done because the assembler parses the floating point literal for fli.h, fli.s, and fli.d as a single precision value. Unfortunately, this function is also used by CodeGen and causes this value to be miscompiled for f32. --- llvm/test/CodeGen/RISCV/float-zfa.ll | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/llvm/test/CodeGen/RISCV/float-zfa.ll b/llvm/test/CodeGen/RISCV/float-zfa.ll index fe8359d..7700f57 100644 --- a/llvm/test/CodeGen/RISCV/float-zfa.ll +++ b/llvm/test/CodeGen/RISCV/float-zfa.ll @@ -77,6 +77,15 @@ define float @loadfpimm9() { ret float 255.0 } +; FIXME: This is the f16 minimum value. It should not be supported for f32. +define float @loadfpimm10() { +; CHECK-LABEL: loadfpimm10: +; CHECK: # %bb.0: +; CHECK-NEXT: fli.s fa0, min +; CHECK-NEXT: ret + ret float 0.00006103515625 +} + declare float @llvm.minimum.f32(float, float) define float @fminm_s(float %a, float %b) nounwind { -- 2.7.4