From f287bb8cf5e48a22b5d1be47da803f73c5aa8186 Mon Sep 17 00:00:00 2001
From: David Green <david.green@arm.com>
Date: Mon, 24 Feb 2020 11:15:09 +0000
Subject: [PATCH] [ARM] FP16 bitcast test. NFC

---
 llvm/test/CodeGen/ARM/fp16-bitcast.ll | 60 +++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)
 create mode 100644 llvm/test/CodeGen/ARM/fp16-bitcast.ll

diff --git a/llvm/test/CodeGen/ARM/fp16-bitcast.ll b/llvm/test/CodeGen/ARM/fp16-bitcast.ll
new file mode 100644
index 0000000..450e534
--- /dev/null
+++ b/llvm/test/CodeGen/ARM/fp16-bitcast.ll
@@ -0,0 +1,60 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple thumbv8m.main-arm-unknown-eabi -mattr=+vfp4d16sp < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-VFPV4
+; RUN: llc -mtriple thumbv8.1m.main-arm-unknown-eabi -mattr=+fullfp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=CHECK-FP16
+
+target triple = "thumbv8.1m.main-arm-unknown-eabi"
+
+define float @add(float %a, float %b) {
+; CHECK-VFPV4-LABEL: add:
+; CHECK-VFPV4:       @ %bb.0: @ %entry
+; CHECK-VFPV4-NEXT:    vmov s0, r1
+; CHECK-VFPV4-NEXT:    vmov s2, r0
+; CHECK-VFPV4-NEXT:    vadd.f32 s0, s2, s0
+; CHECK-VFPV4-NEXT:    vmov r0, s0
+; CHECK-VFPV4-NEXT:    bx lr
+;
+; CHECK-FP16-LABEL: add:
+; CHECK-FP16:       @ %bb.0: @ %entry
+; CHECK-FP16-NEXT:    .pad #4
+; CHECK-FP16-NEXT:    sub sp, #4
+; CHECK-FP16-NEXT:    vmov s0, r1
+; CHECK-FP16-NEXT:    vmov s2, r0
+; CHECK-FP16-NEXT:    vadd.f32 s0, s2, s0
+; CHECK-FP16-NEXT:    vstr s0, [sp]
+; CHECK-FP16-NEXT:    ldr r0, [sp], #4
+; CHECK-FP16-NEXT:    bx lr
+entry:
+  %add = fadd float %a, %b
+  ret float %add
+}
+
+define i32 @addf16(i32 %a.coerce, i32 %b.coerce) {
+; CHECK-VFPV4-LABEL: addf16:
+; CHECK-VFPV4:       @ %bb.0: @ %entry
+; CHECK-VFPV4-NEXT:    vmov s2, r1
+; CHECK-VFPV4-NEXT:    vmov s0, r0
+; CHECK-VFPV4-NEXT:    vcvtb.f32.f16 s2, s2
+; CHECK-VFPV4-NEXT:    vcvtb.f32.f16 s0, s0
+; CHECK-VFPV4-NEXT:    vadd.f32 s0, s0, s2
+; CHECK-VFPV4-NEXT:    vcvtb.f16.f32 s0, s0
+; CHECK-VFPV4-NEXT:    vmov r0, s0
+; CHECK-VFPV4-NEXT:    uxth r0, r0
+; CHECK-VFPV4-NEXT:    bx lr
+;
+; CHECK-FP16-LABEL: addf16:
+; CHECK-FP16:       @ %bb.0: @ %entry
+; CHECK-FP16-NEXT:    vmov.f16 s0, r1
+; CHECK-FP16-NEXT:    vmov.f16 s2, r0
+; CHECK-FP16-NEXT:    vadd.f16 s0, s2, s0
+; CHECK-FP16-NEXT:    vmov.f16 r0, s0
+; CHECK-FP16-NEXT:    bx lr
+entry:
+  %tmp.0.extract.trunc = trunc i32 %a.coerce to i16
+  %0 = bitcast i16 %tmp.0.extract.trunc to half
+  %tmp1.0.extract.trunc = trunc i32 %b.coerce to i16
+  %1 = bitcast i16 %tmp1.0.extract.trunc to half
+  %add = fadd half %0, %1
+  %2 = bitcast half %add to i16
+  %tmp4.0.insert.ext = zext i16 %2 to i32
+  ret i32 %tmp4.0.insert.ext
+}
-- 
2.7.4