From f248468359df3f31e8deaad92e0685cd60e169f1 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Mon, 17 Apr 2017 01:51:19 +0000 Subject: [PATCH] [InstCombine] Add support for turning vector sdiv into udiv. llvm-svn: 300435 --- .../InstCombine/InstCombineMulDivRem.cpp | 34 ++++++++++------------ llvm/test/Transforms/InstCombine/div-shift.ll | 4 +-- llvm/test/Transforms/InstCombine/div.ll | 9 ++---- 3 files changed, 21 insertions(+), 26 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp index f1ac820..de0c2a1 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp @@ -1238,25 +1238,23 @@ Instruction *InstCombiner::visitSDiv(BinaryOperator &I) { // If the sign bits of both operands are zero (i.e. we can prove they are // unsigned inputs), turn this into a udiv. - if (I.getType()->isIntegerTy()) { - APInt Mask(APInt::getSignBit(I.getType()->getPrimitiveSizeInBits())); - if (MaskedValueIsZero(Op0, Mask, 0, &I)) { - if (MaskedValueIsZero(Op1, Mask, 0, &I)) { - // X sdiv Y -> X udiv Y, iff X and Y don't have sign bit set - auto *BO = BinaryOperator::CreateUDiv(Op0, Op1, I.getName()); - BO->setIsExact(I.isExact()); - return BO; - } + APInt Mask(APInt::getSignBit(I.getType()->getScalarSizeInBits())); + if (MaskedValueIsZero(Op0, Mask, 0, &I)) { + if (MaskedValueIsZero(Op1, Mask, 0, &I)) { + // X sdiv Y -> X udiv Y, iff X and Y don't have sign bit set + auto *BO = BinaryOperator::CreateUDiv(Op0, Op1, I.getName()); + BO->setIsExact(I.isExact()); + return BO; + } - if (isKnownToBeAPowerOfTwo(Op1, DL, /*OrZero*/ true, 0, &AC, &I, &DT)) { - // X sdiv (1 << Y) -> X udiv (1 << Y) ( -> X u>> Y) - // Safe because the only negative value (1 << Y) can take on is - // INT_MIN, and X sdiv INT_MIN == X udiv INT_MIN == 0 if X doesn't have - // the sign bit set. - auto *BO = BinaryOperator::CreateUDiv(Op0, Op1, I.getName()); - BO->setIsExact(I.isExact()); - return BO; - } + if (isKnownToBeAPowerOfTwo(Op1, DL, /*OrZero*/ true, 0, &AC, &I, &DT)) { + // X sdiv (1 << Y) -> X udiv (1 << Y) ( -> X u>> Y) + // Safe because the only negative value (1 << Y) can take on is + // INT_MIN, and X sdiv INT_MIN == X udiv INT_MIN == 0 if X doesn't have + // the sign bit set. + auto *BO = BinaryOperator::CreateUDiv(Op0, Op1, I.getName()); + BO->setIsExact(I.isExact()); + return BO; } } diff --git a/llvm/test/Transforms/InstCombine/div-shift.ll b/llvm/test/Transforms/InstCombine/div-shift.ll index 5642241..b5a6504 100644 --- a/llvm/test/Transforms/InstCombine/div-shift.ll +++ b/llvm/test/Transforms/InstCombine/div-shift.ll @@ -20,8 +20,8 @@ define <2 x i32> @t1vec(<2 x i16> %x, <2 x i32> %y) { ; CHECK-LABEL: @t1vec( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[CONV:%.*]] = zext <2 x i16> [[X:%.*]] to <2 x i32> -; CHECK-NEXT: [[S:%.*]] = shl nuw <2 x i32> , [[Y:%.*]] -; CHECK-NEXT: [[D:%.*]] = sdiv <2 x i32> [[CONV]], [[S]] +; CHECK-NEXT: [[TMP0:%.*]] = add <2 x i32> [[Y:%.*]], +; CHECK-NEXT: [[D:%.*]] = lshr <2 x i32> [[CONV]], [[TMP0]] ; CHECK-NEXT: ret <2 x i32> [[D]] ; entry: diff --git a/llvm/test/Transforms/InstCombine/div.ll b/llvm/test/Transforms/InstCombine/div.ll index 99cd696..66ffa50d 100644 --- a/llvm/test/Transforms/InstCombine/div.ll +++ b/llvm/test/Transforms/InstCombine/div.ll @@ -391,7 +391,7 @@ define i32 @test35(i32 %A) { define <2 x i32> @test35vec(<2 x i32> %A) { ; CHECK-LABEL: @test35vec( ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[A:%.*]], -; CHECK-NEXT: [[MUL:%.*]] = sdiv exact <2 x i32> [[AND]], +; CHECK-NEXT: [[MUL:%.*]] = udiv exact <2 x i32> [[AND]], ; CHECK-NEXT: ret <2 x i32> [[MUL]] ; %and = and <2 x i32> %A, @@ -411,13 +411,10 @@ define i32 @test36(i32 %A) { ret i32 %mul } -; FIXME: Vector should get same transform as scalar. - define <2 x i32> @test36vec(<2 x i32> %A) { ; CHECK-LABEL: @test36vec( -; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> %A, -; CHECK-NEXT: [[SHL:%.*]] = shl nuw nsw <2 x i32> , %A -; CHECK-NEXT: [[MUL:%.*]] = sdiv exact <2 x i32> [[AND]], [[SHL]] +; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[A:%.*]], +; CHECK-NEXT: [[MUL:%.*]] = lshr exact <2 x i32> [[AND]], [[A]] ; CHECK-NEXT: ret <2 x i32> [[MUL]] ; %and = and <2 x i32> %A, -- 2.7.4