From f241265fdcc37a171ba246780462e19960a49e7f Mon Sep 17 00:00:00 2001 From: Ralf Baechle Date: Wed, 13 Apr 2016 01:17:57 +0200 Subject: [PATCH] MIPS: BMIPS: Make whitespacely correct. Signed-off-by: Ralf Baechle --- arch/mips/kernel/bmips_5xxx_init.S | 272 ++++++++++++++++++------------------- 1 file changed, 136 insertions(+), 136 deletions(-) diff --git a/arch/mips/kernel/bmips_5xxx_init.S b/arch/mips/kernel/bmips_5xxx_init.S index 788ebf9..adaa82e 100644 --- a/arch/mips/kernel/bmips_5xxx_init.S +++ b/arch/mips/kernel/bmips_5xxx_init.S @@ -27,16 +27,16 @@ #define cacheop(kva, size, linesize, op) \ .set noreorder ; \ - addu t1, kva, size ; \ - subu t2, linesize, 1 ; \ - not t2 ; \ - and t0, kva, t2 ; \ - addiu t1, t1, -1 ; \ - and t1, t2 ; \ -9: cache op, 0(t0) ; \ - bne t0, t1, 9b ; \ - addu t0, linesize ; \ - .set reorder ; + addu t1, kva, size ; \ + subu t2, linesize, 1 ; \ + not t2 ; \ + and t0, kva, t2 ; \ + addiu t1, t1, -1 ; \ + and t1, t2 ; \ +9: cache op, 0(t0) ; \ + bne t0, t1, 9b ; \ + addu t0, linesize ; \ + .set reorder ; @@ -59,13 +59,13 @@ #define CP0_BRCM_MODE $22, 1 #define CP0_CONFIG_K0_MASK 7 -#define CP0_ICACHE_TAG_LO $28 -#define CP0_ICACHE_DATA_LO $28, 1 -#define CP0_DCACHE_TAG_LO $28, 2 +#define CP0_ICACHE_TAG_LO $28 +#define CP0_ICACHE_DATA_LO $28, 1 +#define CP0_DCACHE_TAG_LO $28, 2 #define CP0_D_SEC_CACHE_DATA_LO $28, 3 -#define CP0_ICACHE_TAG_HI $29 -#define CP0_ICACHE_DATA_HI $29, 1 -#define CP0_DCACHE_TAG_HI $29, 2 +#define CP0_ICACHE_TAG_HI $29 +#define CP0_ICACHE_DATA_HI $29, 1 +#define CP0_DCACHE_TAG_HI $29, 2 #define CP0_BRCM_MODE_Luc_MASK (1 << 11) #define CP0_BRCM_CONFIG0_CWF_MASK (1 << 20) @@ -78,7 +78,7 @@ #define CP0_BRCM_MODE_BrHIST_SHIFT 20 /* ZSC L2 Cache Register Access Register Definitions */ -#define BRCM_ZSC_ALL_REGS_SELECT 0x7 << 24 +#define BRCM_ZSC_ALL_REGS_SELECT 0x7 << 24 #define BRCM_ZSC_CONFIG_REG 0 << 3 #define BRCM_ZSC_REQ_BUFFER_REG 2 << 3 @@ -117,9 +117,9 @@ */ LEAF(size_i_cache) - .set noreorder + .set noreorder - mfc0 a0, CP0_CONFIG, 1 + mfc0 a0, CP0_CONFIG, 1 move t0, a0 /* @@ -131,13 +131,13 @@ LEAF(size_i_cache) * vi) 0x5 - 0x7: Reserved. */ - srl a0, a0, IS_SHIFT - and a0, a0, IS_MASK + srl a0, a0, IS_SHIFT + and a0, a0, IS_MASK /* sets per way = (64<